arm/errata: Update required bits for A57 cores erratas
This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>utp
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dbe94dd11c
commit
f299b5b0d2
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@ -115,18 +115,18 @@ apply_a57_core_errata:
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#ifdef CONFIG_ARM_ERRATA_828024
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#ifdef CONFIG_ARM_ERRATA_828024
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable non-allocate hint of w-b-n-a memory type */
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/* Disable non-allocate hint of w-b-n-a memory type */
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mov x0, #0x1 << 49
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orr x0, x0, #1 << 49
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/* Disable write streaming no L1-allocate threshold */
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/* Disable write streaming no L1-allocate threshold */
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mov x0, #0x3 << 25
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orr x0, x0, #3 << 25
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/* Disable write streaming no-allocate threshold */
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/* Disable write streaming no-allocate threshold */
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mov x0, #0x3 << 27
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orr x0, x0, #3 << 27
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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#endif
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#endif
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#ifdef CONFIG_ARM_ERRATA_826974
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#ifdef CONFIG_ARM_ERRATA_826974
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable speculative load execution ahead of a DMB */
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/* Disable speculative load execution ahead of a DMB */
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mov x0, #0x1 << 59
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orr x0, x0, #1 << 59
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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#endif
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#endif
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