ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patch
This patch fixes some minor issues introduced with the patch: ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika: - Rework memory-queue and PLB arbiter optimization code, that the local variable is not needed anymore. This removes one #ifdef. - Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead of XXX+ 0x01). This was not introduced by Prodyut, just a copy-paste problem. Signed-off-by: Stefan Roese <sr@denx.de>
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@ -2172,11 +2172,6 @@ static void program_memory_queue(unsigned long *dimm_populated,
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unsigned long i;
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unsigned long bank_0_populated = 0;
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phys_size_t total_size = 0;
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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unsigned long val;
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#endif
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/*------------------------------------------------------------------
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* Reset the rank_base_address.
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@ -2257,7 +2252,6 @@ static void program_memory_queue(unsigned long *dimm_populated,
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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/*
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* Enable high bandwidth access
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* This is currently not used, but with this setup
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@ -2270,15 +2264,11 @@ static void program_memory_queue(unsigned long *dimm_populated,
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/*
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* Set optimal value for Memory Queue HB/LL Configuration registers
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*/
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val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
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mtdcr(SDRAM_CONF1HB, val);
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val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
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mtdcr(SDRAM_CONF1LL, val);
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val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
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mtdcr(SDRAM_CONFPATHB, val);
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mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
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SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
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mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
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SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
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mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
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#endif
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}
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@ -138,9 +138,7 @@ void reconfigure_pll(u32 new_cpu_freq)
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void
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cpu_init_f (void)
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{
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#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \
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defined(CONFIG_460GT) || defined(CONFIG_460SX)
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#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
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u32 val;
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#endif
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@ -304,16 +302,17 @@ cpu_init_f (void)
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mtsdr(SDR0_USB2HOST_CFG, val);
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#endif /* CONFIG_460EX */
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#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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#if defined(CONFIG_405EX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_405EX) || defined(CONFIG_460SX)
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defined(CONFIG_460SX)
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/*
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* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
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*/
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val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
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mtdcr(plb0_acr, val);
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val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
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mtdcr(plb1_acr, val);
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mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) |
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plb0_acr_rdp_4deep);
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mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) |
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plb1_acr_rdp_4deep);
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#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
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}
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@ -56,8 +56,8 @@
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#define PLB_ARBITER_BASE 0x80
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#define plb0_revid (PLB_ARBITER_BASE+ 0x00)
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#define plb0_acr (PLB_ARBITER_BASE+ 0x01)
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#define plb0_revid (PLB_ARBITER_BASE + 0x00)
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#define plb0_acr (PLB_ARBITER_BASE + 0x01)
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#define plb0_acr_ppm_mask 0xF0000000
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#define plb0_acr_ppm_fixed 0x00000000
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#define plb0_acr_ppm_fair 0xD0000000
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@ -73,13 +73,13 @@
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#define plb0_acr_wrp_disabled 0x00000000
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#define plb0_acr_wrp_2deep 0x01000000
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#define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
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#define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
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#define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
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#define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
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#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
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#define plb0_besrl (PLB_ARBITER_BASE + 0x02)
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#define plb0_besrh (PLB_ARBITER_BASE + 0x03)
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#define plb0_bearl (PLB_ARBITER_BASE + 0x04)
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#define plb0_bearh (PLB_ARBITER_BASE + 0x05)
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#define plb0_ccr (PLB_ARBITER_BASE + 0x08)
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#define plb1_acr (PLB_ARBITER_BASE+ 0x09)
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#define plb1_acr (PLB_ARBITER_BASE + 0x09)
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#define plb1_acr_ppm_mask 0xF0000000
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#define plb1_acr_ppm_fixed 0x00000000
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#define plb1_acr_ppm_fair 0xD0000000
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@ -95,10 +95,10 @@
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#define plb1_acr_wrp_disabled 0x00000000
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#define plb1_acr_wrp_2deep 0x01000000
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#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
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#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
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#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
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#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
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#define plb1_besrl (PLB_ARBITER_BASE + 0x0A)
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#define plb1_besrh (PLB_ARBITER_BASE + 0x0B)
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#define plb1_bearl (PLB_ARBITER_BASE + 0x0C)
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#define plb1_bearh (PLB_ARBITER_BASE + 0x0D)
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#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
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