powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code
Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -1,5 +1,5 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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* Copyright 2008,2010 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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@ -51,17 +51,9 @@
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*/
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struct law_entry law_table[] = {
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#ifdef CONFIG_SYS_PCI1_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
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SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
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#endif
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#ifdef CONFIG_SYS_PCI2_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
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SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
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#endif
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#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
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SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
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SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
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#endif
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
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SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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@ -215,20 +215,13 @@ static struct pci_controller pci1_hose = {
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static struct pci_controller pci2_hose;
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#endif /* CONFIG_PCI2 */
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCIE1 */
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void pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info[4];
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struct fsl_pci_info pci_info;
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u32 devdisr, pordevsr, io_sel;
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u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
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int first_free_busno = 0;
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int num = 0;
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int pcie_ep, pcie_configured;
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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@ -244,8 +237,13 @@ void pci_init_board(void)
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pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info[num], 1);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
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SET_STD_PCI_INFO(pci_info, 1);
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set_next_law(pci_info.mem_phys,
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law_size_bits(pci_info.mem_size), pci_info.law);
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set_next_law(pci_info.io_phys,
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law_size_bits(pci_info.io_size), pci_info.law);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
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printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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@ -253,9 +251,9 @@ void pci_init_board(void)
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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pci_info[num].regs);
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pci_info.regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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first_free_busno = fsl_pci_init_port(&pci_info,
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&pci1_hose, first_free_busno);
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#ifdef CONFIG_PCIX_CHECK
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@ -293,26 +291,7 @@ void pci_init_board(void)
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
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#endif /* CONFIG_PCI2 */
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#ifdef CONFIG_PCIE1
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pcie_configured = is_serdes_configured(PCIE1);
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if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
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SET_STD_PCIE_INFO(pci_info[num], 1);
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pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
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printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
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pcie_ep ? "Endpoint" : "Root Complex",
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pci_info[num].regs);
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first_free_busno = fsl_pci_init_port(&pci_info[num++],
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&pcie1_hose, first_free_busno);
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} else {
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printf("PCIE1: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
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#endif
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fsl_pcie_init_board(first_free_busno);
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}
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int last_stage_init(void)
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@ -1,5 +1,5 @@
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/*
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* Copyright 2004, 2007 Freescale Semiconductor.
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* Copyright 2004, 2007, 2010 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -353,6 +353,7 @@ extern unsigned long get_clock_freq(void);
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#endif
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#ifdef CONFIG_PCIE1
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#define CONFIG_SYS_PCIE1_NAME "Slot"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
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