spi, spi_mxc: do not hang in spi_xchg_single
if status register do never set MXC_CSPICTRL_TC, spi_xchg_single endless loops. Add a timeout here to prevent endless hang. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>utp
parent
22052c6236
commit
f659b57361
4
README
4
README
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@ -2597,6 +2597,10 @@ CBFS (Coreboot Filesystem) support
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Enables the driver for the SPI controllers on i.MX and MXC
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Enables the driver for the SPI controllers on i.MX and MXC
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SoCs. Currently i.MX31/35/51 are supported.
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SoCs. Currently i.MX31/35/51 are supported.
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CONFIG_SYS_SPI_MXC_WAIT
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Timeout for waiting until spi transfer completed.
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default: (CONFIG_SYS_HZ/100) /* 10 ms */
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- FPGA Support: CONFIG_FPGA
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- FPGA Support: CONFIG_FPGA
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Enables FPGA subsystem.
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Enables FPGA subsystem.
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@ -30,6 +30,10 @@ static unsigned long spi_bases[] = {
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#define reg_read readl
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#define reg_read readl
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#define reg_write(a, v) writel(v, a)
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#define reg_write(a, v) writel(v, a)
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#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
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#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
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#endif
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struct mxc_spi_slave {
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struct mxc_spi_slave {
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struct spi_slave slave;
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struct spi_slave slave;
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unsigned long base;
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unsigned long base;
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@ -212,6 +216,8 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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int nbytes = DIV_ROUND_UP(bitlen, 8);
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int nbytes = DIV_ROUND_UP(bitlen, 8);
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u32 data, cnt, i;
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u32 data, cnt, i;
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
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u32 ts;
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int status;
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debug("%s: bitlen %d dout 0x%x din 0x%x\n",
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debug("%s: bitlen %d dout 0x%x din 0x%x\n",
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__func__, bitlen, (u32)dout, (u32)din);
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__func__, bitlen, (u32)dout, (u32)din);
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@ -272,9 +278,16 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
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reg_write(®s->ctrl, mxcs->ctrl_reg |
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reg_write(®s->ctrl, mxcs->ctrl_reg |
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MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
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MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
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ts = get_timer(0);
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status = reg_read(®s->stat);
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/* Wait until the TC (Transfer completed) bit is set */
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/* Wait until the TC (Transfer completed) bit is set */
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while ((reg_read(®s->stat) & MXC_CSPICTRL_TC) == 0)
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while ((status & MXC_CSPICTRL_TC) == 0) {
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;
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if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
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printf("spi_xchg_single: Timeout!\n");
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return -1;
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}
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status = reg_read(®s->stat);
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}
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/* Transfer completed, clear any pending request */
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/* Transfer completed, clear any pending request */
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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reg_write(®s->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
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