redonkable
/
remarkable-uboot
1
0
Fork 0
Code Releases Activity

Replace DCD with one from Kaifa

utp
Martin T. H. Sandsmark 2016-08-04 11:59:40 +02:00 committed by Martin T. H. Sandsmark
parent f3695d5c01
commit f6eaee96b1
1 changed files with 81 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

187
board/reMarkable/zero-gravitas/imximage.cfg
View File

@ -1,7 +1,7 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
* Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
@ -9,6 +9,9 @@
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
@ -18,7 +21,16 @@ IMAGE_VERSION 2
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
BOOT_FROM sd
#ifdef CONFIG_USE_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx6slevk/plugin.bin 0x00907000
#else
#ifdef CONFIG_SECURE_BOOT
CSF 0x2000
#endif
/*
* Device Configuration Data (DCD)
@ -27,15 +39,10 @@ BOOT_FROM sd
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* ============================================================================= */
/* Enable all clocks (they are disabled by ROM code) */
/* Full speed until we get calibrations */
/* ============================================================================= */
DATA 4 0x020c4068 0xffffffff
DATA 4 0x020c406c 0xffffffff
DATA 4 0x020c4070 0xffffffff
@ -43,117 +50,85 @@ DATA 4 0x020c4074 0xffffffff
DATA 4 0x020c4078 0xffffffff
DATA 4 0x020c407c 0xffffffff
DATA 4 0x020c4080 0xffffffff
DATA 4 0x020c4084 0xffffffff
/* ============================================================================= */
/* IOMUX */
/* ============================================================================= */
/* DDR IO TYPE: */
DATA 4 0x020e0774 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
DATA 4 0x020e0754 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
DATA 4 0x020c4018 0x00260324
/* CLOCK: */
DATA 4 0x020e04ac 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
DATA 4 0x020e04b0 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
DATA 4 0x020e05c0 0x00020000
DATA 4 0x020e05b4 0x00000000
/* ADDRESS: */
DATA 4 0x020e0464 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
DATA 4 0x020e0490 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
DATA 4 0x020e074c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
DATA 4 0x020e0338 0x00000030
/* Control: */
DATA 4 0x020e0494 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
DATA 4 0x020e04a0 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */
DATA 4 0x020e04b4 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
DATA 4 0x020e04b8 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
DATA 4 0x020e076c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
DATA 4 0x020e0300 0x00000030
DATA 4 0x020e031c 0x00000030
DATA 4 0x020e0320 0x00000030
DATA 4 0x020e032c 0x00000000
DATA 4 0x020e05ac 0x00000030
DATA 4 0x020e05c8 0x00000030
/* Data Strobes: */
DATA 4 0x020e0750 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
DATA 4 0x020e04bc 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
DATA 4 0x020e04c0 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
DATA 4 0x020e04c4 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
DATA 4 0x020e04c8 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
/* DATA 4 0x020e04cc 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
/* DATA 4 0x020e04d0 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
/* DATA 4 0x020e04d4 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
/* DATA 4 0x020e04d8 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
DATA 4 0x020e05b0 0x00020000
DATA 4 0x020e0344 0x00000030
DATA 4 0x020e0348 0x00000030
DATA 4 0x020e034c 0x00000030
DATA 4 0x020e0350 0x00000030
/* Data: */
DATA 4 0x020e0760 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
DATA 4 0x020e0764 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
DATA 4 0x020e0770 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
DATA 4 0x020e0778 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B2DS */
DATA 4 0x020e077c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B3DS */
/* DATA 4 0x020e0780 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B4DS */
/* DATA 4 0x020e0784 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B5DS */
/* DATA 4 0x020e078c 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B6DS */
/* DATA 4 0x020e0748 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B7DS */
DATA 4 0x020e05d0 0x000C0000
DATA 4 0x020e05c4 0x00000030
DATA 4 0x020e05cc 0x00000030
DATA 4 0x020e05d4 0x00000030
DATA 4 0x020e05d8 0x00000030
DATA 4 0x020e0470 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
DATA 4 0x020e0474 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
DATA 4 0x020e0478 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
DATA 4 0x020e047c 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
/* DATA 4 0x020e0480 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
/* DATA 4 0x020e0484 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
/* DATA 4 0x020e0488 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
/* DATA 4 0x020e048c 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
DATA 4 0x020e030c 0x00000030
DATA 4 0x020e0310 0x00000030
DATA 4 0x020e0314 0x00000030
DATA 4 0x020e0318 0x00000030
DATA 4 0x021b0800 0xa1390003
/* ============================================================================= */
/* DDR Controller Registers */
/* ============================================================================= */
/* Manufacturer: Micron */
/* Device Part Number: MT41K128M16JT-125 */
/* Clock Freq.: 400MHz */
/* Density per CS in Gb: 4 */
/* Chip Selects used: 1 */
/* Number of Banks: 8 */
/* Row address: 14 */
/* Column address: 10 */
/* Data bus width 32 */
/* ============================================================================= */
DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
DATA 4 0x021b080c 0x0029001F
DATA 4 0x021b0810 0x0022001F
/* MMDC init: */
DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
DATA 4 0x021b0008 0x00333040 /* MMDC0_MDOTC */
DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
DATA 4 0x021b0010 0xB66D8B63 /* MMDC0_MDCFG1 */
DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
DATA 4 0x021b083c 0x0144013C
DATA 4 0x021b0840 0x01280124
DATA 4 0x021b0848 0x3C3A4044
DATA 4 0x021b0850 0x36363830
/* MDMISC: RALAT kept to the high level of 5. */
/* MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: */
/* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 */
/* b. Small performence improvment */
DATA 4 0x021b0018 0x00011740 /* MMDC0_MDMISC */
DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
DATA 4 0x021b0040 0x00000017 /* Chan0 CS0_END */
DATA 4 0x021b0000 0x83190000 /* MMDC0_MDCTL */
DATA 4 0x021b081c 0x33333333
DATA 4 0x021b0820 0x33333333
DATA 4 0x021b0824 0x33333333
DATA 4 0x021b0828 0x33333333
/* Mode register writes */
DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0write, CS0 */
DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
DATA 4 0x021b08b8 0x00000800
/* DATA 4 0x021b001c 0x0200803A # MMDC0_MDSCR, MR2 write, CS1 */
/* DATA 4 0x021b001c 0x0000803B # MMDC0_MDSCR, MR3 write, CS1 */
/* DATA 4 0x021b001c 0x00048039 # MMDC0_MDSCR, MR1 write, CS1 */
/* DATA 4 0x021b001c 0x15208038 # MMDC0_MDSCR, MR0write, CS1 */
/* DATA 4 0x021b001c 0x04008048 # MMDC0_MDSCR, ZQ calibration command sent to device on CS1 */
DATA 4 0x021b0004 0x0002002D
DATA 4 0x021b0008 0x1B444040
DATA 4 0x021b000c 0x8B8F5333
DATA 4 0x021b0010 0xB68E0B64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b0018 0x00081740
DATA 4 0x021b0020 0x00007800 /* MMDC0_MDREF */
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b002c 0x000026d2
DATA 4 0x021b0030 0x008F1023
DATA 4 0x021b0040 0x0000004f
DATA 4 0x021b0000 0x84190000
DATA 4 0x021b0818 0x00022227 /* DDR_PHY_P0_MPODTCTRL */
/* DATA 4 0x021b4818 0x00022227 # DDR_PHY_P1_MPODTCTRL */
DATA 4 0x021b001c 0x04088032
DATA 4 0x021b001c 0x00008033
DATA 4 0x021b001c 0x00048031
DATA 4 0x021b001c 0x05208030
DATA 4 0x021b001c 0x04008040
DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
DATA 4 0x021b001c 0x0408803A
DATA 4 0x021b001c 0x0000803B
DATA 4 0x021b001c 0x00048039
DATA 4 0x021b001c 0x05208038
DATA 4 0x021b001c 0x04008048
DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached. */
DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00011117
DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete) */
DATA 4 0x021b0004 0x0002556D
DATA 4 0x021b0404 0x00011006
DATA 4 0x021b001c 0x00000000
#endif