sf: Add dual memories support - DUAL_STACKED
This patch added support for accessing dual memories in stacked connection with single chipselect line from controller. For more info - see doc/SPI/README.dual-flash Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>utp
Jagannadha Sutradharudu Teki
parent
ab92224f45
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f77f469117
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@ -0,0 +1,65 @@
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SPI/QSPI Dual flash connection modes:
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=====================================
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This describes how SPI/QSPI flash memories are connected to a given
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controller in a single chip select line.
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Current spi_flash framework supports, single flash memory connected
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to a given controller with single chip select line, but there are some
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hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
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connected with a single chip select line from a controller.
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"dual_flash" from include/spi.h describes these types of connection mode
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Possible connections:
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--------------------
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SF_SINGLE_FLASH:
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- single spi flash memory connected with single chip select line.
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+------------+ CS +---------------+
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| |----------------------->| |
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| Controller | I0[3:0] | Flash memory |
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| SPI/QSPI |<======================>| (SPI/QSPI) |
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| | CLK | |
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| |----------------------->| |
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+------------+ +---------------+
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SF_DUAL_STACKED_FLASH:
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- dual spi/qspi flash memories are connected with a single chipselect
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line and these two memories are operating stacked fasion with shared buses.
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- xilinx zynq qspi controller has implemented this feature [1]
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+------------+ CS +---------------+
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| |---------------------->| |
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| | I0[3:0] | Upper Flash |
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| | +=========>| memory |
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| | | CLK | (SPI/QSPI) |
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| | | +---->| |
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| Controller | CS | | +---------------+
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| SPI/QSPI |------------|----|---->| |
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| | I0[3:0] | | | Lower Flash |
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| |<===========+====|====>| memory |
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| | CLK | | (SPI/QSPI) |
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| |-----------------+---->| |
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+------------+ +---------------+
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- two memory flash devices should has same hw part attributes (like size,
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vendor..etc)
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- Configurations:
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on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
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Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
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Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
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- Operation:
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accessing memories serially like one after another.
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by default, if U_PAGE is unset lower memory should accessible,
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once user wants to access upper memory need to set U_PAGE.
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Note: Technically there is only one CS line from the controller, but
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zynq qspi controller has an internal hw logic to enable additional CS
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when controller is configured for dual memories.
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[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
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--
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Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
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05-01-2014.
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@ -18,6 +18,9 @@ static int spi_flash_read_write(struct spi_slave *spi,
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unsigned long flags = SPI_XFER_BEGIN;
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int ret;
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if (spi->flags & SPI_XFER_U_PAGE)
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flags |= SPI_XFER_U_PAGE;
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if (data_len == 0)
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flags |= SPI_XFER_END;
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@ -131,10 +131,28 @@ static int spi_flash_bank(struct spi_flash *flash, u32 offset)
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}
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#endif
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static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
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{
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switch (flash->dual_flash) {
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case SF_DUAL_STACKED_FLASH:
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if (*addr >= (flash->size >> 1)) {
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*addr -= flash->size >> 1;
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flash->spi->flags |= SPI_XFER_U_PAGE;
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} else {
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flash->spi->flags &= ~SPI_XFER_U_PAGE;
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}
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break;
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default:
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debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
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break;
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}
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}
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int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
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{
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struct spi_slave *spi = flash->spi;
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unsigned long timebase;
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unsigned long flags = SPI_XFER_BEGIN;
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int ret;
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u8 status;
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u8 check_status = 0x0;
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@ -146,7 +164,10 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
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check_status = poll_bit;
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}
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ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
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if (spi->flags & SPI_XFER_U_PAGE)
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flags |= SPI_XFER_U_PAGE;
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ret = spi_xfer(spi, 8, &cmd, NULL, flags);
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if (ret) {
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debug("SF: fail to read %s status register\n",
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cmd == CMD_READ_STATUS ? "read" : "flag");
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@ -219,7 +240,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
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int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
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{
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u32 erase_size;
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u32 erase_size, erase_addr;
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u8 cmd[SPI_FLASH_CMD_LEN];
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int ret = -1;
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@ -231,15 +252,20 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
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cmd[0] = flash->erase_cmd;
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while (len) {
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erase_addr = offset;
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if (flash->dual_flash > SF_SINGLE_FLASH)
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spi_flash_dual_flash(flash, &erase_addr);
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#ifdef CONFIG_SPI_FLASH_BAR
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ret = spi_flash_bank(flash, offset);
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ret = spi_flash_bank(flash, erase_addr);
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if (ret < 0)
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return ret;
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#endif
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spi_flash_addr(offset, cmd);
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spi_flash_addr(erase_addr, cmd);
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debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
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cmd[2], cmd[3], offset);
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cmd[2], cmd[3], erase_addr);
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ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
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if (ret < 0) {
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@ -258,6 +284,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
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size_t len, const void *buf)
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{
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unsigned long byte_addr, page_size;
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u32 write_addr;
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size_t chunk_len, actual;
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u8 cmd[SPI_FLASH_CMD_LEN];
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int ret = -1;
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@ -266,8 +293,13 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
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cmd[0] = flash->write_cmd;
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for (actual = 0; actual < len; actual += chunk_len) {
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write_addr = offset;
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if (flash->dual_flash > SF_SINGLE_FLASH)
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spi_flash_dual_flash(flash, &write_addr);
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#ifdef CONFIG_SPI_FLASH_BAR
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ret = spi_flash_bank(flash, offset);
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ret = spi_flash_bank(flash, write_addr);
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if (ret < 0)
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return ret;
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#endif
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@ -277,7 +309,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
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if (flash->spi->max_write_size)
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chunk_len = min(chunk_len, flash->spi->max_write_size);
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spi_flash_addr(offset, cmd);
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spi_flash_addr(write_addr, cmd);
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debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
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buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
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@ -322,7 +354,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
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size_t len, void *data)
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{
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u8 *cmd, cmdsz;
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u32 remain_len, read_len;
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u32 remain_len, read_len, read_addr;
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int bank_sel = 0;
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int ret = -1;
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@ -346,8 +378,13 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
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cmd[0] = flash->read_cmd;
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while (len) {
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read_addr = offset;
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if (flash->dual_flash > SF_SINGLE_FLASH)
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spi_flash_dual_flash(flash, &read_addr);
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#ifdef CONFIG_SPI_FLASH_BAR
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bank_sel = spi_flash_bank(flash, offset);
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bank_sel = spi_flash_bank(flash, read_addr);
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if (bank_sel < 0)
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return ret;
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#endif
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@ -357,7 +394,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
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else
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read_len = remain_len;
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spi_flash_addr(offset, cmd);
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spi_flash_addr(read_addr, cmd);
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ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
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if (ret < 0) {
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@ -134,6 +134,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
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flash->spi = spi;
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flash->name = params->name;
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flash->memory_map = spi->memory_map;
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flash->dual_flash = flash->spi->option;
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/* Assign spi_flash ops */
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flash->write = spi_flash_cmd_write_ops;
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@ -148,6 +149,8 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
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flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
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flash->sector_size = params->sector_size;
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flash->size = flash->sector_size * params->nr_sectors;
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if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
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flash->size <<= 1;
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/* Compute erase sector and command */
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if (params->flags & SECT_4K) {
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@ -324,7 +327,10 @@ static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
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puts("\n");
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#endif
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#ifndef CONFIG_SPI_FLASH_BAR
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if (flash->size > SPI_FLASH_16MB_BOUN) {
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if (((flash->dual_flash == SF_SINGLE_FLASH) &&
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(flash->size > SPI_FLASH_16MB_BOUN)) ||
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((flash->dual_flash > SF_SINGLE_FLASH) &&
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(flash->size > SPI_FLASH_16MB_BOUN << 1))) {
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puts("SF: Warning - Only lower 16MiB accessible,");
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puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
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}
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@ -30,6 +30,7 @@
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#define SPI_XFER_MMAP 0x08 /* Memory Mapped start */
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#define SPI_XFER_MMAP_END 0x10 /* Memory Mapped End */
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#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
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#define SPI_XFER_U_PAGE (1 << 5)
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/* SPI TX operation modes */
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#define SPI_OPM_TX_QPP 1 << 0
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@ -44,6 +45,9 @@
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SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
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SPI_OPM_RX_QIOF
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/* SPI bus connection options */
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#define SPI_CONN_DUAL_SHARED 1 << 0
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/* Header byte that marks the start of the message */
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#define SPI_PREAMBLE_END_BYTE 0xec
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@ -62,6 +66,8 @@
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* @max_write_size: If non-zero, the maximum number of bytes which can
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* be written at once, excluding command bytes.
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* @memory_map: Address of read-only SPI flash access.
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* @option: Varies SPI bus options - separate bus.
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* @flags: Indication of SPI flags.
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*/
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struct spi_slave {
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unsigned int bus;
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@ -71,6 +77,8 @@ struct spi_slave {
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unsigned int wordlen;
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unsigned int max_write_size;
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void *memory_map;
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u8 option;
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u8 flags;
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};
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/**
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@ -36,6 +36,12 @@ enum spi_read_cmds {
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#define RD_EXTN ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
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#define RD_FULL RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
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/* Dual SPI flash memories */
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enum spi_dual_flash {
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SF_SINGLE_FLASH = 0,
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SF_DUAL_STACKED_FLASH = 1 << 0,
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};
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/**
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* struct spi_flash_params - SPI/QSPI flash device params structure
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*
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@ -64,6 +70,7 @@ extern const struct spi_flash_params spi_flash_params_table[];
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*
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* @spi: SPI slave
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* @name: Name of SPI flash
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* @dual_flash: Indicates dual flash memories - dual stacked
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* @size: Total flash size
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* @page_size: Write (page) size
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* @sector_size: Sector size
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@ -88,6 +95,7 @@ extern const struct spi_flash_params spi_flash_params_table[];
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struct spi_flash {
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struct spi_slave *spi;
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const char *name;
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u8 dual_flash;
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u32 size;
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u32 page_size;
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