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ARM: tegra: add Venice2 (Tegra124) board 

These are the board files for Venice2 (Tegra124), plus the AS3722 PMIC
files. PMIC init will be moved to pmic_common_init later.

This builds/boots on Venice2, SPI/MMC/USB/I2C all work. Audio, display
and WB/LP0 are not supported yet.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
utp
Tom Warren 2014-01-24 12:46:18 -07:00 committed by Tom Warren
parent a57c5846a2
commit f7dc4ac37c
8 changed files with 672 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
board/nvidia/venice2/Makefile 100644
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#
# (C) Copyright 2013-2014
# NVIDIA Corporation <www.nvidia.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += as3722_init.o
obj-y += venice2.o

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board/nvidia/venice2/as3722_init.c 100644
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/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch-tegra/tegra_i2c.h>
#include "as3722_init.h"
/* AS3722-PMIC-specific early init code - get CPU rails up, etc */
void tegra_i2c_ll_write_addr(uint addr, uint config)
{
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
writel(addr, &reg->cmd_addr0);
writel(config, &reg->cnfg);
}
void tegra_i2c_ll_write_data(uint data, uint config)
{
struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
writel(data, &reg->cmd_data1);
writel(config, &reg->cnfg);
}
void pmic_enable_cpu_vdd(void)
{
debug("%s entry\n", __func__);
/* Don't need to set up VDD_CORE - already done - by OTP */
debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
/*
* Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.0V, then enable the VDD regulator.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
/*
* Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.0V, then enable the VDD regulator.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
/*
* Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
* First set VDD to 1.2V, then enable the VDD regulator.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
/*
* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
* First set it to bypass 3.3V straight thru, then enable the regulator
*
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
/*
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
* tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
*/
udelay(10 * 1000);
}

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board/nvidia/venice2/as3722_init.h 100644
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/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* AS3722-PMIC-specific early init regs */
#define AS3722_I2C_ADDR 0x80
#define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */
#define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */
#define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */
#define AS3722_SDCONTROL_REG 0x4D
#define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */
#define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
#define AS3722_LDCONTROL_REG 0x4E
#define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
#define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)
#define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG)
#define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG)
#define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG)
#define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG)
#define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG)
#define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG)
#define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG)
#define I2C_SEND_2_BYTES 0x0A02
void pmic_enable_cpu_vdd(void);

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board/nvidia/venice2/pinmux-config-venice2.h 100644
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/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PINMUX_CONFIG_VENICE2_H_
#define _PINMUX_CONFIG_VENICE2_H_
#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
{ \
.pingroup = PINGRP_##_pingroup, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_DEFAULT, \
.od = PMUX_PIN_OD_DEFAULT, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingroup = PINGRP_##_pingroup, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_##_lock, \
.od = PMUX_PIN_OD_##_od, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
.pingroup = PINGRP_##_pingroup, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_##_lock, \
.rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
.pingroup = PINGRP_##_pingroup, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_##_lock, \
.od = PMUX_PIN_OD_DEFAULT, \
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingroup = PINGRP_##_pingroup, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
.io = PMUX_PIN_##_io, \
.lock = PMUX_PIN_LOCK_##_lock, \
.od = PMUX_PIN_OD_##_od, \
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define USB_PINMUX CEC_PINMUX
#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.padgrp = PDRIVE_PINGROUP_##_padgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
.lpmd = PGRP_LPMD_##_lpmd, \
.schmt = PGRP_SCHMT_##_schmt, \
.hsm = PGRP_HSM_##_hsm, \
}
static struct pingroup_config tegra124_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
/* I2S0 pinmux */
DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT),
/* I2S1 pinmux */
DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
/* I2S3 pinmux */
DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
/* CLDVFS pinmux */
DEFAULT_PINMUX(DVFS_PWM, CLDVFS, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(DVFS_CLK, CLDVFS, NORMAL, NORMAL, OUTPUT),
/* ULPI pinmux */
DEFAULT_PINMUX(ULPI_DATA0, ULPI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA1, ULPI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA2, ULPI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA3, ULPI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA4, ULPI, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA5, ULPI, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT),
/* EC KBC/SPI */
DEFAULT_PINMUX(ULPI_CLK, SPI1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DIR, SPI1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT),
/* I2C3 (TPM) pinmux */
I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* I2C2 pinmux */
I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* UARTD pinmux (UART4 on Servo board, unused) */
DEFAULT_PINMUX(GPIO_PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_PB0, UARTD, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PB1, UARTD, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PK7, UARTD, NORMAL, NORMAL, OUTPUT),
/* SPI4 (Winbond 'boot ROM') */
DEFAULT_PINMUX(GPIO_PG5, SPI4, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PG6, SPI4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PG7, SPI4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PI3, SPI4, NORMAL, NORMAL, INPUT),
/* Touch IRQ */
DEFAULT_PINMUX(GPIO_W3_AUD, RSVD1, NORMAL, NORMAL, INPUT),
/* PWM1 pinmux */
DEFAULT_PINMUX(GPIO_PH1, PWM1, NORMAL, NORMAL, OUTPUT),
/* SDMMC1 pinmux */
DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP, NORMAL, INPUT),
/* SDMMC3 pinmux */
DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_CLK_LB_IN, SDMMC3, UP, TRISTATE, INPUT),
DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT, SDMMC3, DOWN, NORMAL, INPUT),
/* SDMMC4 pinmux */
DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, UP, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, UP, NORMAL, INPUT),
/* BLINK pinmux */
DEFAULT_PINMUX(CLK_32K_OUT, BLINK, NORMAL, NORMAL, OUTPUT),
/* KBC pinmux */
DEFAULT_PINMUX(KB_COL0, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_COL1, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_COL2, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_ROW0, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_ROW1, KBC, UP, NORMAL, INPUT),
/* Misc */
DEFAULT_PINMUX(GPIO_PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
DEFAULT_PINMUX(KB_ROW7, RSVD1, UP, NORMAL, INPUT),
/* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
DEFAULT_PINMUX(KB_ROW9, UARTA, UP, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_ROW10, UARTA, UP, TRISTATE, INPUT),
/* I2CPWR pinmux (I2C5) */
I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* RTCK pinmux */
DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
/* CLK pinmux */
DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT),
/* PWRON pinmux */
DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT),
/* CPU pinmux */
DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT),
/* PMI pinmux */
DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT),
/* RESET_OUT_N pinmux */
DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
/* EXTPERIPH3 pinmux */
DEFAULT_PINMUX(CLK3_OUT, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
/* I2C1 pinmux */
I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* UARTB, GPS */
DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART2_RXD, UARTB, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(UART2_TXD, UARTB, NORMAL, NORMAL, OUTPUT),
/* UARTC (WIFI/BT) */
DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT),
/* CEC pinmux */
CEC_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
/* I2C4 (HDMI_DDC) pinmux */
DDC_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
DDC_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
/* USB pinmux */
USB_PINMUX(USB_VBUS_EN0, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
USB_PINMUX(USB_VBUS_EN1, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
/* Unused, marked SNN_ on schematic, TRISTATE 'em */
DEFAULT_PINMUX(GPIO_PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PH3, GMI, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PI7, GMI, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_X5_AUD, RSVD3, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_X6_AUD, GMI, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(GPIO_PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(USB_VBUS_EN2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_COL5, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW2, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW3, KBC, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW5, RSVD2, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW13, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW14, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(KB_ROW16, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP3_DIN, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP3_FS, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(DAP3_SCLK, RSVD2, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(CLK2_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(SDMMC1_WP_N, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(CAM_MCLK, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(CLK3_REQ, RSVD1, NORMAL, TRISTATE, INPUT),
DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
};
static struct pingroup_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_X3_AUD, RSVD3, UP, NORMAL, INPUT),
/* EN_VDD_BL */
DEFAULT_PINMUX(DAP3_DOUT, I2S2, DOWN, NORMAL, OUTPUT),
/* MODEM */
DEFAULT_PINMUX(GPIO_PV0, RSVD3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PV1, RSVD1, NORMAL, NORMAL, INPUT),
/* BOOT_SEL0-3 */
DEFAULT_PINMUX(GPIO_PG0, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PG1, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PG2, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PG3, GMI, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(CLK2_REQ, RSVD3, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_COL3, KBC, UP, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_COL4, SDMMC3, UP, NORMAL, INPUT),
DEFAULT_PINMUX(KB_COL6, KBC, UP, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_COL7, KBC, UP, NORMAL, OUTPUT),
DEFAULT_PINMUX(KB_ROW4, KBC, DOWN, NORMAL, INPUT),
DEFAULT_PINMUX(KB_ROW8, KBC, UP, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PU4, RSVD3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_PU6, RSVD3, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(HDMI_INT, RSVD1, DOWN, NORMAL, INPUT),
DEFAULT_PINMUX(SPDIF_IN, USB, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
/* TS_SHDN_L */
DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT),
};
static struct padctrl_config venice2_padctrl[] = {
/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
};
#endif /* PINMUX_CONFIG_VENICE2_H */

33
board/nvidia/venice2/venice2.c 100644
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@ -0,0 +1,33 @@
/*
* (C) Copyright 2013-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm-generic/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include "pinmux-config-venice2.h"
#include <i2c.h>
/*
* Routine: pinmux_init
* Description: Do individual peripheral pinmux configs
*/
void pinmux_init(void)
{
pinmux_config_table(tegra124_pinmux_set_nontristate,
ARRAY_SIZE(tegra124_pinmux_set_nontristate));
pinmux_config_table(tegra124_pinmux_common,
ARRAY_SIZE(tegra124_pinmux_common));
pinmux_config_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
}

1
boards.cfg
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@ -364,6 +364,7 @@ Active arm armv7 zynq xilinx zynq
Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren <twarren@nvidia.com>
Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de>

82
include/configs/tegra124-common.h 100644
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/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA124_COMMON_H_
#define _TEGRA124_COMMON_H_
#include "tegra-common.h"
/* Cortex-A15 uses a cache line size of 64 bytes */
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
/*
* High Level Configuration Options
*/
#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TEXT_BASE 0x8010E000
/*
* Memory layout for where various images get loaded by boot scripts:
*
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it above BOOTMAPSZ to eliminate conflicts.
*
* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
* something else. Put it above BOOTMAPSZ to eliminate conflicts.
*
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
* this up to 16M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
* the compressed kernel to be up to 16M too.
*
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=0x81000000\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x80108000
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
#define CONFIG_SPL_STACK 0x800ffffc
/* Total I2C ports on Tegra124 */
#define TEGRA_I2C_NUM_CONTROLLERS 5
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#endif /* _TEGRA124_COMMON_H_ */

79
include/configs/venice2.h 100644
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/*
* (C) Copyright 2013-2014
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/sizes.h>
#include "tegra124-common.h"
/* Enable fdt support for Venice2. Flash the image in u-boot-dtb.bin */
#define CONFIG_DEFAULT_DEVICE_TREE tegra124-venice2
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
#define V_PROMPT "Tegra124 (Venice2) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_BOARD_EARLY_INIT_F
/* I2C */
#define CONFIG_SYS_I2C_TEGRA
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
/* SD/MMC */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_TEGRA_MMC
#define CONFIG_CMD_MMC
/* Environment in eMMC, at the end of 2nd "boot sector" */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
/* SPI */
#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
#define CONFIG_TEGRA114_SPI_CTRLS 6
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SF_DEFAULT_SPEED 24000000
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_SIZE (4 << 20)
/* USB Host support */
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_TEGRA
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_USB
/* USB networking support */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
/* General networking support */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#include "tegra-common-post.h"
#endif /* __CONFIG_H */