83xx/85xx: further localbus cleanups
move the BRx_* and ORx_* left behind in mpc85xx.h The same is needed for mpc8xx.h and mpc8260.h (defines are almost the same, just few differences which needs some attention though). But the bad news for mpc8xx and mpc8260 is that there are a lot of users of these defines. So this cleanup I'll leave for the "better times". Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>utp
Anton Vorontsov
Kim Phillips
parent
bf30bb1f7c
commit
f9023afbdf
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@ -44,7 +44,11 @@
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#define BR_MSEL_SHIFT 5
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#define BR_MS_GPCM 0x00000000 /* GPCM */
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#define BR_MS_FCM 0x00000020 /* FCM */
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#ifdef CONFIG_MPC83xx
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#define BR_MS_SDRAM 0x00000060 /* SDRAM */
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#elif defined(CONFIG_MPC85xx)
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#define BR_MS_SDRAM 0x00000000 /* SDRAM */
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#endif
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#define BR_MS_UPMA 0x00000080 /* UPMA */
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#define BR_MS_UPMB 0x000000A0 /* UPMB */
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#define BR_MS_UPMC 0x000000C0 /* UPMC */
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@ -80,8 +84,8 @@
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#define OR_GPCM_CSNT_SHIFT 11
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#define OR_GPCM_ACS 0x00000600
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#define OR_GPCM_ACS_SHIFT 9
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#define OR_GPCM_ACS_0b10 0x00000400
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#define OR_GPCM_ACS_0b11 0x00000600
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#define OR_GPCM_ACS_DIV2 0x00000600
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#define OR_GPCM_ACS_DIV4 0x00000400
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#define OR_GPCM_XACS 0x00000100
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#define OR_GPCM_XACS_SHIFT 8
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#define OR_GPCM_SCY 0x000000F0
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@ -110,6 +114,10 @@
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#define OR_GPCM_EAD 0x00000001
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#define OR_GPCM_EAD_SHIFT 0
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/* helpers to convert values into an OR address mask (GPCM mode) */
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#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
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#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
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#define OR_FCM_AM 0xFFFF8000
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#define OR_FCM_AM_SHIFT 15
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#define OR_FCM_BCTLD 0x00001000
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@ -153,6 +161,11 @@
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#define OR_UPM_EAD 0x00000001
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#define OR_UPM_EAD_SHIFT 0
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#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
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#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
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#define MxMR_OP_WARR 0x10000000 /* Write to Array */
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#define MxMR_BSEL 0x80000000 /* Bus Select */
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#define OR_SDRAM_AM 0xFFFF8000
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#define OR_SDRAM_AM_SHIFT 15
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#define OR_SDRAM_XAM 0x00006000
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@ -203,7 +203,7 @@
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#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_0b11 \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX \
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@ -157,7 +157,7 @@
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
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#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */
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@ -211,7 +211,7 @@ boards, we say we have two, but don't display a message if we find only one. */
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#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V)
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE
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#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT))
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@ -236,7 +236,7 @@ boards, we say we have two, but don't display a message if we find only one. */
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#define CFG_LED_BASE 0xF9000000
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#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V)
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#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
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#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \
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OR_GPCM_EHTR | OR_GPCM_EAD)
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@ -203,7 +203,7 @@
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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@ -195,7 +195,7 @@
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(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
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BR_V) /* valid */
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#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
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OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_XACS | OR_GPCM_SCY_15 | \
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OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
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@ -239,7 +239,7 @@
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#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_0b11 \
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| OR_GPCM_ACS_DIV2 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX \
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@ -113,7 +113,7 @@ extern int tqm834x_num_flash_banks;
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BR_MS_GPCM | BR_PS_32 | BR_V)
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/* FLASH timing (0x0000_0c54) */
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#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_0b10 | \
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#define CFG_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
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OR_GPCM_SCY_5 | OR_GPCM_TRLX)
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#define CFG_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
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@ -28,39 +28,4 @@
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#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
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#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
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/*
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* Local Bus Controller - memory controller registers
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*/
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#define BRx_V 0x00000001 /* Bank Valid */
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#define BRx_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
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#define BRx_MS_SDRAM 0x00000000 /* SDRAM Machine Select */
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#define BRx_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
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#define BRx_MS_UPMB 0x000000a0 /* U.P.M.B Machine Select */
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#define BRx_MS_UPMC 0x000000c0 /* U.P.M.C Machine Select */
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#define BRx_PS_8 0x00000800 /* 8 bit port size */
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#define BRx_PS_32 0x00001800 /* 32 bit port size */
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#define BRx_BA_MSK 0xffff8000 /* Base Address Mask */
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#define ORxG_EAD 0x00000001 /* External addr latch delay */
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#define ORxG_EHTR 0x00000002 /* Extended hold time on read */
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#define ORxG_TRLX 0x00000004 /* Timing relaxed */
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#define ORxG_SETA 0x00000008 /* External address termination */
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#define ORxG_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
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#define ORxG_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
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#define ORxG_XACS 0x00000100 /* Extra addr to CS setup */
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#define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/
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#define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */
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#define ORxU_BI 0x00000100 /* Burst Inhibit */
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#define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */
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#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
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#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
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#define MxMR_OP_WARR 0x10000000 /* Write to Array */
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#define MxMR_BSEL 0x80000000 /* Bus Select */
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/* helpers to convert values into an OR address mask (GPCM mode) */
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#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
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#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
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#endif /* __MPC85xx_H__ */
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