ARM: mxs: Add PPC-AG BG0900 board
This board supports FEC Ethernet, SPI NOR and NAND flash. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Christoph Baumann <c.baumann@ppc-ag.de>utp
Marek Vasut
Stefano Babic
parent
0c5e26678b
commit
f97271612b
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@ -0,0 +1,31 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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ifndef CONFIG_SPL_BUILD
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COBJS := bg0900.o
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else
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COBJS := spl_boot.o
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endif
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,86 @@
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/*
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* PPC-AG BG0900 board
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*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Functions
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*/
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int board_early_init_f(void)
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{
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/* IO0 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK0, 480000);
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/* IO1 clock at 480MHz */
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mxs_set_ioclk(MXC_IOCLK1, 480000);
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/* SSP2 clock at 160MHz */
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mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
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return 0;
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}
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int dram_init(void)
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{
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return mxs_dram_init();
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}
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int board_init(void)
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{
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/* Adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct eth_device *dev;
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int ret;
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ret = cpu_eth_init(bis);
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/* BG0900 uses ENET_CLK PAD to drive FEC clock */
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writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
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&clkctrl_regs->hw_clkctrl_enet);
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/* Reset FEC PHYs */
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gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
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udelay(200);
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gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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puts("FEC MXS: Unable to init FEC0\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC0");
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if (!dev) {
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puts("FEC MXS: Unable to get FEC0 device entry\n");
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return -EINVAL;
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}
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return ret;
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}
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#endif
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@ -0,0 +1,140 @@
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/*
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* PPC-AG BG0900 Boot setup
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*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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const iomux_cfg_t iomux_setup[] = {
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/* DUART */
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MX28_PAD_PWM0__DUART_RX,
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MX28_PAD_PWM1__DUART_TX,
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/* GPMI NAND */
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MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_RDN__GPMI_RDN |
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(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
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MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
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MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
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/* FEC0 */
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MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
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MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
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MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
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/* FEC0 Reset */
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MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
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/* EMI */
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MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
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/* SPI2 (for SPI flash) */
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MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_SS0__SSP2_D3 |
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(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
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};
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void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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dram_vals[0x98 / 4] = 0x04005003;
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dram_vals[0x9c / 4] = 0x090000c8;
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dram_vals[0xa8 / 4] = 0x0036b009;
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dram_vals[0xac / 4] = 0x03270612;
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dram_vals[0xb0 / 4] = 0x02020202;
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dram_vals[0xb4 / 4] = 0x00c80029;
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dram_vals[0xc0 / 4] = 0x00011900;
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dram_vals[0x12c / 4] = 0x07400300;
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dram_vals[0x130 / 4] = 0x07400300;
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dram_vals[0x2c4 / 4] = 0x02030303;
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}
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void board_init_ll(const uint32_t arg, const uint32_t *resptr)
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{
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mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
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}
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@ -207,6 +207,7 @@ Active arm arm926ejs mxs freescale mx28evk
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Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
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Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
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Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com>
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Active arm arm926ejs mxs ppcag bg0900 bg0900 bg0900 Marek Vasut <marex@denx.de>
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Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
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Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
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Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
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@ -0,0 +1,97 @@
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/*
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* Copyright (C) 2013 Marek Vasut <marex@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIGS_BG0900_H__
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#define __CONFIGS_BG0900_H__
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/* System configurations */
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#define CONFIG_MX28 /* i.MX28 SoC */
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/* U-Boot Commands */
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#define CONFIG_SYS_NO_FLASH
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#include <config_cmd_default.h>
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_BOOTZ
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_GPIO
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND_TRIMFFS
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_SETEXPR
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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/* Memory configuration */
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#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x40000000 /* Base address */
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#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Environment */
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#define CONFIG_ENV_SIZE (16 * 1024)
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_IS_NOWHERE
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/* FEC Ethernet on SoC */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_MXC
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#define CONFIG_NET_MULTI
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#endif
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/* SPI */
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#ifdef CONFIG_CMD_SPI
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#define CONFIG_DEFAULT_SPI_BUS 2
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#define CONFIG_DEFAULT_SPI_CS 0
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#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
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/* SPI FLASH */
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#ifdef CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_BAR
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SF_DEFAULT_BUS 2
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_SPEED 40000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_ENV_SPI_BUS 2
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 40000000
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#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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#endif
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#endif
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/* Boot Linux */
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTFILE "uImage"
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#define CONFIG_BOOTARGS "console=ttyAMA0,115200"
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#define CONFIG_BOOTCOMMAND "bootm"
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#define CONFIG_LOADADDR 0x42000000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/* Extra Environment */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"update_spi_firmware_filename=u-boot.sb\0" \
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"update_spi_firmware_maxsz=0x80000\0" \
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"update_spi_firmware=" /* Update the SPI flash firmware */ \
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"if sf probe 2:0 ; then " \
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"if tftp ${update_spi_firmware_filename} ; then " \
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"sf erase 0x0 +${filesize} ; " \
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"sf write ${loadaddr} 0x0 ${filesize} ; " \
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"fi ; " \
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"fi\0"
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/* The rest of the configuration is shared */
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#include <configs/mxs.h>
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#endif /* __CONFIGS_BG0900_H__ */
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