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mtd: nand: omap_gpmc: Always use ready/busy pin 

The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.

Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to detect the NAND chip state. Here the values tested on
Draco with Hynix 4GBit NAND:

Without NAND ready pin:

U-Boot# time nand read 80400000 0 400000

NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK

time: 2.947 seconds, 2947 ticks

With NAND ready pin:

U-Boot# time nand read 80400000 0 400000

NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK

time: 2.795 seconds, 2795 ticks

So an increase of approx. 5%.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
utp
Stefan Roese 2014-11-13 03:43:39 +01:00 committed by Tom Rini
parent e49631afa0
commit fb384c4720
1 changed files with 4 additions and 5 deletions
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9
drivers/mtd/nand/omap_gpmc.c
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@ -73,14 +73,11 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
writeb(cmd, this->IO_ADDR_W);
}
#ifdef CONFIG_SPL_BUILD
/* Check wait pin as dev ready indicator */
static int omap_spl_dev_ready(struct mtd_info *mtd)
static int omap_dev_ready(struct mtd_info *mtd)
{
return gpmc_cfg->status & (1 << 8);
}
#endif
/*
* gen_true_ecc - This function will generate true ECC value, which
@ -887,7 +884,9 @@ int board_nand_init(struct nand_chip *nand)
nand->read_buf = nand_read_buf16;
else
nand->read_buf = nand_read_buf;
nand->dev_ready = omap_spl_dev_ready;
#endif
nand->dev_ready = omap_dev_ready;
return 0;
}