powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet
Added descriptions about boot from PCIE in the files README and doc/README.srio-pcie-boot-corenet, and changed the name of the doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>utp
Liu Gang
Andy Fleming
parent
81fa73bab0
commit
fc54c7fa0a
12
README
12
README
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@ -3092,12 +3092,12 @@ to save the current settings.
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These two #defines specify the address and size of the
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environment area within the remote memory space. The
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local device can get the environment from remote memory
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space by SRIO or other links.
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space by SRIO or PCIE links.
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BE CAREFUL! For some special cases, the local device can not use
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"saveenv" command. For example, the local device will get the
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environment stored in a remote NOR flash by SRIO link, but it can
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not erase, write this NOR flash by SRIO interface.
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environment stored in a remote NOR flash by SRIO or PCIE link,
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but it can not erase, write this NOR flash by SRIO or PCIE interface.
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- CONFIG_ENV_IS_IN_NAND:
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@ -3538,9 +3538,9 @@ within that device.
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- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
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Specifies that QE/FMAN firmware is located in the remote (master)
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memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
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can be mapped from slave TLB->slave LAW->slave SRIO outbound window
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->master inbound window->master LAW->the ucode address in master's
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NOR flash.
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can be mapped from slave TLB->slave LAW->slave SRIO or PCIE outbound
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window->master inbound window->master LAW->the ucode address in
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master's memory space.
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Building the Software:
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======================
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@ -1,99 +0,0 @@
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------------------------------
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SRIO Boot on Corenet Platforms
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------------------------------
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For some PowerPC processors with SRIO interface, boot location can be configured
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to SRIO by RCW. The processor booting from SRIO can do without flash for u-boot
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image, ucode and ENV. All the images can be fetched from another processor's
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memory space by SRIO link connected between them.
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This document describes the processes based on an example implemented on P4080DS
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platforms and a RCW example with boot from SRIO configuration.
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Environment of the SRIO boot:
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a) Master and slave can be SOCs in one board or SOCs in separate boards.
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b) They are connected with SRIO links, whether 1x or 4x, and directly or
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through switch system.
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c) Only Master has NorFlash for booting, and all the Master's and Slave's
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U-Boot images, UCodes will be stored in this flash.
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d) Slave has its own EEPROM for RCW and PBI.
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e) Slave's RCW should configure the SerDes for SRIO boot port, set the boot
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location to SRIO, and holdoff all the cores.
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---------- ----------- -----------
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| | | | | |
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| NorFlash|<----->| Master | SRIO | Slave |<---->[EEPROM]
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| | | |<===========>| |
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| | | | | |
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---------- ----------- -----------
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The example based on P4080DS platform:
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Two P4080DS platforms can be used to implement the boot from SRIO. Their SRIO
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ports 1 will be connected directly and will be used for the boot from SRIO.
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1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
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00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
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00000010: 1818 1818 0000 8888 7440 4000 0000 2000
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00000020: f440 0000 0100 0000 0000 0000 0000 0000
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00000030: 0000 0000 0083 0000 0000 0000 0000 0000
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00000040: 0000 0000 0000 0000 0813 8040 063c 778f
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2. Sequence in Step by Step.
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a) Update RCW for slave with boot from SRIO port 1 configuration.
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b) Program slave's U-Boot image, UCode, and ENV parameters into master's
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NorFlash.
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c) Set environment variable "bootmaster" to "SRIO1" and save environment
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for master.
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setenv bootmaster SRIO1
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saveenv
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d) Restart up master and it will boot up normally from its NorFlash.
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Then, it will finish necessary configurations for slave's boot from
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SRIO port 1.
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e) Master will set inbound SRIO windows covered slave's U-Boot image stored
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in master's NorFlash.
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f) Master will set an inbound SRIO window covered slave's UCode and ENV
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stored in master's NorFlash.
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g) Master will set outbound SRIO windows in order to configure slave's
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registers for the core's releasing.
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h) Since all cores of slave in holdoff, slave should be powered on before all
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the above master's steps, and wait to be released by master. In the
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startup phase of the slave from SRIO, it will finish some necessary
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configurations.
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i) Slave will set a specific TLB entry for the boot process.
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j) Slave will set a LAW entry with the TargetID SRIO port 1 for the boot.
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k) Slave will set a specific TLB entry in order to fetch UCode and ENV
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from master.
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l) Slave will set a LAW entry with the TargetID SRIO port 1 for UCode and ENV.
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How to use this feature:
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To use this feature, you need to focus those points.
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1. Slave's RCW with SRIO boot configurations, and all cores in holdoff
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configurations.
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Please refer to the examples given above.
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2. U-Boot image's compilation.
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For master, U-Boot image should be generated normally.
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For example, master U-Boot image used on P4080DS should be compiled with
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make P4080DS_config.
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For slave, U-Boot image should be generated specifically by
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make xxxx_SRIOBOOT_SLAVE_config.
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For example, slave U-Boot image used on P4080DS should be compiled with
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make P4080DS_SRIOBOOT_SLAVE_config.
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3. Necessary modifications based on a specific environment.
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For a specific environment, the addresses of the slave's U-Boot image,
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UCode, ENV stored in master's NorFlash, and any other configurations
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can be modified in the file:
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include/configs/corenet_ds.h.
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4. Set and save the environment variable "bootmaster" with "SRIO1" or "SRIO2"
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for master, and then restart it in order to perform the role as a master
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for boot from SRIO.
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@ -0,0 +1,112 @@
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---------------------------------------
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SRIO and PCIE Boot on Corenet Platforms
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---------------------------------------
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For some PowerPC processors with SRIO or PCIE interface, boot location can be
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configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
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do without flash for u-boot image, ucode and ENV. All the images can be fetched
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from another processor's memory space by SRIO or PCIE link connected between
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them.
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This document describes the processes based on an example implemented on P4080DS
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platforms and a RCW example with boot from SRIO or PCIE configuration.
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Environment of the SRIO or PCIE boot:
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a) Master and slave can be SOCs in one board or SOCs in separate boards.
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b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
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directly or through switch system.
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c) Only Master has NorFlash for booting, and all the Master's and Slave's
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U-Boot images, UCodes will be stored in this flash.
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d) Slave has its own EEPROM for RCW and PBI.
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e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
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the boot location to SRIO or PCIE, and holdoff all the cores.
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---------- ----------- -----------
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| | | | | |
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| NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
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| | | |<===========>| |
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| | | | | |
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---------- ----------- -----------
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The example based on P4080DS platform:
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Two P4080DS platforms can be used to implement the boot from SRIO or PCIE.
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Their SRIO or PCIE ports 1 will be connected directly and will be used for
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the boot from SRIO or PCIE.
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1. Slave's RCW example for boot from SRIO port 1 and all cores in holdoff.
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00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
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00000010: 1818 1818 0000 8888 7440 4000 0000 2000
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00000020: f440 0000 0100 0000 0000 0000 0000 0000
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00000030: 0000 0000 0083 0000 0000 0000 0000 0000
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00000040: 0000 0000 0000 0000 0813 8040 063c 778f
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2. Slave's RCW example for boot from PCIE port 1 and all cores in holdoff.
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00000000: aa55 aa55 010e 0100 0c58 0000 0000 0000
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00000010: 1818 1818 0000 8888 1440 4000 0000 2000
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00000020: f040 0000 0100 0000 0020 0000 0000 0000
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00000030: 0000 0000 0083 0000 0000 0000 0000 0000
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00000040: 0000 0000 0000 0000 0813 8040 547e ffc9
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3. Sequence in Step by Step.
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a) Update RCW for slave with boot from SRIO or PCIE port 1 configuration.
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b) Program slave's U-Boot image, UCode, and ENV parameters into master's
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NorFlash.
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c) Set environment variable "bootmaster" to "SRIO1" or "PCIE1" and save
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environment for master.
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setenv bootmaster SRIO1
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or
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setenv bootmaster PCIE1
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saveenv
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d) Restart up master and it will boot up normally from its NorFlash.
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Then, it will finish necessary configurations for slave's boot from
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SRIO or PCIE port 1.
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e) Master will set inbound SRIO or PCIE windows covered slave's U-Boot
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image stored in master's NorFlash.
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f) Master will set an inbound SRIO or PCIE window covered slave's UCode
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and ENV stored in master's NorFlash.
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g) Master will set outbound SRIO or PCIE windows in order to configure
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slave's registers for the core's releasing.
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h) Since all cores of slave in holdoff, slave should be powered on before
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all the above master's steps, and wait to be released by master. In the
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startup phase of the slave from SRIO or PCIE, it will finish some
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necessary configurations.
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i) Slave will set a specific TLB entry for the boot process.
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j) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
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the boot.
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k) Slave will set a specific TLB entry in order to fetch UCode and ENV
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from master.
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l) Slave will set a LAW entry with the TargetID SRIO or PCIE port 1 for
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UCode and ENV.
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How to use this feature:
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To use this feature, you need to focus those points.
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1. Slave's RCW with SRIO or PCIE boot configurations, and all cores in holdoff
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configurations.
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Please refer to the examples given above.
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2. U-Boot image's compilation.
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For master, U-Boot image should be generated normally.
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For example, master U-Boot image used on P4080DS should be compiled with
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make P4080DS_config.
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For slave, U-Boot image should be generated specifically by
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make xxxx_SRIO_PCIE_BOOT_config.
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For example, slave U-Boot image used on P4080DS should be compiled with
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make P4080DS_SRIO_PCIE_BOOT_config.
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3. Necessary modifications based on a specific environment.
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For a specific environment, the addresses of the slave's U-Boot image,
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UCode, ENV stored in master's NorFlash, and any other configurations
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can be modified in the file:
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include/configs/corenet_ds.h.
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4. Set and save the environment variable "bootmaster" with "SRIO1", "SRIO2"
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or "PCIE1", "PCIE2", "PCIE3" for master, and then restart it in order to
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perform the role as a master for boot from SRIO or PCIE.
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