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ARM: keystone2: Use common definition for clk_get_rate 

Since all the clocks are defined common, and has the same logic to get
the frequencies, use a common definition for for clk_get_rate().

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
utp
Lokesh Vutla 2015-07-28 14:16:48 +05:30 committed by Tom Rini
parent 7531122e5c
commit fe772ebd28
8 changed files with 167 additions and 103 deletions
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3
arch/arm/mach-keystone/Makefile
View File

@ -8,9 +8,6 @@
obj-y += init.o
obj-y += psc.o
obj-y += clock.o
obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
obj-$(CONFIG_SOC_K2E) += clock-k2e.o
obj-$(CONFIG_SOC_K2L) += clock-k2l.o
obj-y += cmd_clock.o
obj-y += cmd_mon.o
obj-y += msmc.o

139
arch/arm/mach-keystone/clock.c
View File

@ -264,3 +264,142 @@ int get_max_dev_speed(void)
return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS);
}
/**
* pll_freq_get - get pll frequency
* @pll: pll identifier
*/
static unsigned long pll_freq_get(int pll)
{
unsigned long mult = 1, prediv = 1, output_div = 2;
unsigned long ret;
u32 tmp, reg;
if (pll == MAIN_PLL) {
ret = external_clk[sys_clk];
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
/* PLL mode */
tmp = __raw_readl(KS2_MAINPLLCTL0);
prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >>
CFG_PLLCTL0_PLLM_SHIFT |
(pllctl_reg_read(pll, mult) &
PLLM_MULT_LO_MASK)) + 1;
output_div = ((pllctl_reg_read(pll, secctl) &
SECCTL_OP_DIV_MASK) >>
SECCTL_OP_DIV_SHIFT) + 1;
ret = ret / prediv / output_div * mult;
}
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
reg = KS2_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
reg = KS2_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
reg = KS2_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
reg = KS2_DDR3BPLLCTL0;
break;
default:
return 0;
}
tmp = __raw_readl(reg);
if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) {
/* Bypass disabled */
prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >>
CFG_PLLCTL0_PLLM_SHIFT) + 1;
output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >>
CFG_PLLCTL0_CLKOD_SHIFT) + 1;
ret = ((ret / prediv) * mult) / output_div;
}
}
return ret;
}
unsigned long clk_get_rate(unsigned int clk)
{
unsigned long freq = 0;
switch (clk) {
case core_pll_clk:
freq = pll_freq_get(CORE_PLL);
break;
case pass_pll_clk:
freq = pll_freq_get(PASS_PLL);
break;
case tetris_pll_clk:
if (!cpu_is_k2e())
freq = pll_freq_get(TETRIS_PLL);
break;
case ddr3a_pll_clk:
freq = pll_freq_get(DDR3A_PLL);
break;
case ddr3b_pll_clk:
if (cpu_is_k2hk())
freq = pll_freq_get(DDR3B_PLL);
break;
case sys_clk0_1_clk:
case sys_clk0_clk:
freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
break;
case sys_clk1_clk:
return pll_freq_get(CORE_PLL) / pll0div_read(2);
break;
case sys_clk2_clk:
freq = pll_freq_get(CORE_PLL) / pll0div_read(3);
break;
case sys_clk3_clk:
freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
break;
case sys_clk0_2_clk:
freq = clk_get_rate(sys_clk0_clk) / 2;
break;
case sys_clk0_3_clk:
freq = clk_get_rate(sys_clk0_clk) / 3;
break;
case sys_clk0_4_clk:
freq = clk_get_rate(sys_clk0_clk) / 4;
break;
case sys_clk0_6_clk:
freq = clk_get_rate(sys_clk0_clk) / 6;
break;
case sys_clk0_8_clk:
freq = clk_get_rate(sys_clk0_clk) / 8;
break;
case sys_clk0_12_clk:
freq = clk_get_rate(sys_clk0_clk) / 12;
break;
case sys_clk0_24_clk:
freq = clk_get_rate(sys_clk0_clk) / 24;
break;
case sys_clk1_3_clk:
freq = clk_get_rate(sys_clk1_clk) / 3;
break;
case sys_clk1_4_clk:
freq = clk_get_rate(sys_clk1_clk) / 4;
break;
case sys_clk1_6_clk:
freq = clk_get_rate(sys_clk1_clk) / 6;
break;
case sys_clk1_12_clk:
freq = clk_get_rate(sys_clk1_clk) / 12;
break;
default:
break;
}
return freq;
}

7
arch/arm/mach-keystone/cmd_clock.c
View File

@ -67,7 +67,7 @@ U_BOOT_CMD(
int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int clk;
unsigned int freq;
unsigned long freq;
if (argc != 2)
goto getclk_cmd_usage;
@ -75,7 +75,10 @@ int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
clk = simple_strtoul(argv[1], NULL, 10);
freq = clk_get_rate(clk);
printf("clock index [%d] - frequency %u\n", clk, freq);
if (freq)
printf("clock index [%d] - frequency %lu\n", clk, freq);
else
printf("clock index [%d] Not available\n", clk);
return 0;
getclk_cmd_usage:

21
arch/arm/mach-keystone/include/mach/clock-k2e.h
View File

@ -10,27 +10,6 @@
#ifndef __ASM_ARCH_CLOCK_K2E_H
#define __ASM_ARCH_CLOCK_K2E_H
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
CLK(1, pass_pll_clk)\
CLK(2, ddr3_pll_clk)\
CLK(3, sys_clk0_clk)\
CLK(4, sys_clk0_1_clk)\
CLK(5, sys_clk0_2_clk)\
CLK(6, sys_clk0_3_clk)\
CLK(7, sys_clk0_4_clk)\
CLK(8, sys_clk0_6_clk)\
CLK(9, sys_clk0_8_clk)\
CLK(10, sys_clk0_12_clk)\
CLK(11, sys_clk0_24_clk)\
CLK(12, sys_clk1_clk)\
CLK(13, sys_clk1_3_clk)\
CLK(14, sys_clk1_4_clk)\
CLK(15, sys_clk1_6_clk)\
CLK(16, sys_clk1_12_clk)\
CLK(17, sys_clk2_clk)\
CLK(18, sys_clk3_clk)
#define PLLSET_CMD_LIST "<pa|ddr3>"
#define KS2_CLK1_6 sys_clk0_6_clk

23
arch/arm/mach-keystone/include/mach/clock-k2hk.h
View File

@ -10,29 +10,6 @@
#ifndef __ASM_ARCH_CLOCK_K2HK_H
#define __ASM_ARCH_CLOCK_K2HK_H
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
CLK(1, pass_pll_clk)\
CLK(2, tetris_pll_clk)\
CLK(3, ddr3a_pll_clk)\
CLK(4, ddr3b_pll_clk)\
CLK(5, sys_clk0_clk)\
CLK(6, sys_clk0_1_clk)\
CLK(7, sys_clk0_2_clk)\
CLK(8, sys_clk0_3_clk)\
CLK(9, sys_clk0_4_clk)\
CLK(10, sys_clk0_6_clk)\
CLK(11, sys_clk0_8_clk)\
CLK(12, sys_clk0_12_clk)\
CLK(13, sys_clk0_24_clk)\
CLK(14, sys_clk1_clk)\
CLK(15, sys_clk1_3_clk)\
CLK(16, sys_clk1_4_clk)\
CLK(17, sys_clk1_6_clk)\
CLK(18, sys_clk1_12_clk)\
CLK(19, sys_clk2_clk)\
CLK(20, sys_clk3_clk)
#define PLLSET_CMD_LIST "<pa|arm|ddr3a|ddr3b>"
#define KS2_CLK1_6 sys_clk0_6_clk

22
arch/arm/mach-keystone/include/mach/clock-k2l.h
View File

@ -10,28 +10,6 @@
#ifndef __ASM_ARCH_CLOCK_K2L_H
#define __ASM_ARCH_CLOCK_K2L_H
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
CLK(1, pass_pll_clk)\
CLK(2, tetris_pll_clk)\
CLK(3, ddr3_pll_clk)\
CLK(4, sys_clk0_clk)\
CLK(5, sys_clk0_1_clk)\
CLK(6, sys_clk0_2_clk)\
CLK(7, sys_clk0_3_clk)\
CLK(8, sys_clk0_4_clk)\
CLK(9, sys_clk0_6_clk)\
CLK(10, sys_clk0_8_clk)\
CLK(11, sys_clk0_12_clk)\
CLK(12, sys_clk0_24_clk)\
CLK(13, sys_clk1_clk)\
CLK(14, sys_clk1_3_clk)\
CLK(15, sys_clk1_4_clk)\
CLK(16, sys_clk1_6_clk)\
CLK(17, sys_clk1_12_clk)\
CLK(18, sys_clk2_clk)\
CLK(19, sys_clk3_clk)\
#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
#define KS2_CLK1_6 sys_clk0_6_clk

23
arch/arm/mach-keystone/include/mach/clock.h
View File

@ -27,6 +27,29 @@
#define CORE_PLL MAIN_PLL
#define DDR3_PLL DDR3A_PLL
#define CLK_LIST(CLK)\
CLK(0, core_pll_clk)\
CLK(1, pass_pll_clk)\
CLK(2, tetris_pll_clk)\
CLK(3, ddr3a_pll_clk)\
CLK(4, ddr3b_pll_clk)\
CLK(5, sys_clk0_clk)\
CLK(6, sys_clk0_1_clk)\
CLK(7, sys_clk0_2_clk)\
CLK(8, sys_clk0_3_clk)\
CLK(9, sys_clk0_4_clk)\
CLK(10, sys_clk0_6_clk)\
CLK(11, sys_clk0_8_clk)\
CLK(12, sys_clk0_12_clk)\
CLK(13, sys_clk0_24_clk)\
CLK(14, sys_clk1_clk)\
CLK(15, sys_clk1_3_clk)\
CLK(16, sys_clk1_4_clk)\
CLK(17, sys_clk1_6_clk)\
CLK(18, sys_clk1_12_clk)\
CLK(19, sys_clk2_clk)\
CLK(20, sys_clk3_clk)
#include <asm/types.h>
#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM,

32
arch/arm/mach-keystone/include/mach/clock_defs.h
View File

@ -69,38 +69,6 @@ static struct pllctl_regs *pllctl_regs[] = {
#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
#define PLLCTL_BYPASS BIT(23)
#define PLL_PLLRST BIT(14)
#define PLLCTL_PAPLL BIT(13)
#define PLLCTL_CLKMODE BIT(8)
#define PLLCTL_PLLSELB BIT(7)
#define PLLCTL_ENSAT BIT(6)
#define PLLCTL_PLLENSRC BIT(5)
#define PLLCTL_PLLDIS BIT(4)
#define PLLCTL_PLLRST BIT(3)
#define PLLCTL_PLLPWRDN BIT(1)
#define PLLCTL_PLLEN BIT(0)
#define PLLSTAT_GO BIT(0)
#define MAIN_ENSAT_OFFSET 6
#define PLLDIV_ENABLE BIT(15)
#define PLL_DIV_MASK 0x3f
#define PLL_MULT_MASK 0x1fff
#define PLL_MULT_SHIFT 6
#define PLLM_MULT_HI_MASK 0x7f
#define PLLM_MULT_HI_SHIFT 12
#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
#define PLLM_MULT_LO_MASK 0x3f
#define PLL_CLKOD_MASK 0xf
#define PLL_CLKOD_SHIFT 19
#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
#define PLL_BWADJ_LO_MASK 0xff
#define PLL_BWADJ_LO_SHIFT 24
#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
#define PLL_BWADJ_HI_MASK 0xf
/* PLLCTL Bits */
#define PLLCTL_PLLENSRC_SHIF 5
#define PLLCTL_PLLENSRC_MASK BIT(5)