Merge branch 'for-1.3.2-ver2'
Conflicts: cpu/ppc4xx/fdt.c include/configs/kilauea.h include/configs/sequoia.h Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
commit
feaa43f3a8
752
CHANGELOG
752
CHANGELOG
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@ -1,3 +1,687 @@
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||||||
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commit 467bcee11fe26ad422f2de971aa70866079870f2
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||||||
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Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Fri Dec 14 15:36:18 2007 +0100
|
||||||
|
|
||||||
|
cfi_flash: Add manufacturer-specific fixups
|
||||||
|
|
||||||
|
Run fixups based on the JEDEC manufacturer ID independent of the
|
||||||
|
command set ID.
|
||||||
|
|
||||||
|
This changes current behaviour: Previously, geometry reversal for AMD
|
||||||
|
chips were done based on the command set ID, while they are now done
|
||||||
|
based on the JEDEC manufacturer and device ID.
|
||||||
|
|
||||||
|
Also add fixup for top-boot Atmel chips. A fixup is needed for
|
||||||
|
AT49BV6416(T) too, but since u-boot currently only reads the low byte
|
||||||
|
of the device ID, there's no way to tell it apart from AT49BV642D,
|
||||||
|
which should not have this fixup. Since AT49BV642D support is
|
||||||
|
necessary to get ATNGW100 board support into mainline, I've commented
|
||||||
|
out the fixup for now.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
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||||||
|
commit 0ddf06ddf6b4bd057ad4c5f0dffea7870ba06a2a
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Fri Dec 14 15:36:17 2007 +0100
|
||||||
|
|
||||||
|
cfi_flash: Add cmdset-specific init functions
|
||||||
|
|
||||||
|
Move things like reading JEDEC IDs and fixing up geometry reversal
|
||||||
|
into separate functions. The geometry reversal fixup is now performed
|
||||||
|
by altering the qry structure directly, which makes the sector init
|
||||||
|
code slightly cleaner.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit e23741f4a6d8047520ef0d4971762749b3587d32
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Fri Dec 14 15:36:16 2007 +0100
|
||||||
|
|
||||||
|
cfi_flash: Read whole QRY structure in one go
|
||||||
|
|
||||||
|
Read out the whole CFI Standard Query structure after successful cfi
|
||||||
|
identification. This allows subsequent code to access this information
|
||||||
|
directly without having to go through flash_read_uchar() and friends.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit df9c25ea04b38a0e05d4f8c73c5cc144cdafa7db
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Mon Dec 17 11:02:44 2007 +0100
|
||||||
|
|
||||||
|
AVR32: Fix logic inversion in disable_interrupts()
|
||||||
|
|
||||||
|
disable_interrupts() should return nonzero if interrupts were
|
||||||
|
_enabled_ before, not disabled.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit acac475212cbedb17b321a363a1c878e2b47b37f
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Fri Dec 14 16:51:22 2007 +0100
|
||||||
|
|
||||||
|
AVR32: Enable interrupts at bootup
|
||||||
|
|
||||||
|
The timer code depends on the timer interrupt to keep track of the
|
||||||
|
upper 32 bits of the cycle counter. This obviously doesn't work when
|
||||||
|
interrupts are disabled the whole time.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 9570bcd87f4db255514f43b6701746c412f8fef0
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Thu Nov 15 10:03:45 2007 +0100
|
||||||
|
|
||||||
|
AVR32: Fix wrong pin setup for USART3
|
||||||
|
|
||||||
|
As reported by Gerhard Berghofer:
|
||||||
|
|
||||||
|
in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18
|
||||||
|
instead of PB18 and PB19.
|
||||||
|
|
||||||
|
which is obviously correct. There's currently no code that uses
|
||||||
|
USART3, but custom boards may run into problems.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 09ea0de03dcc3ee7af045b0b572227bda2c1c918
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Thu Nov 1 12:44:20 2007 +0100
|
||||||
|
|
||||||
|
README: Remove ATSTK1000 daughterboard list
|
||||||
|
|
||||||
|
As noted by Kim Phillips, these lists tend to become out of date.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit c81cbbad21cb0ae983e2e796211202234cdc8be2
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Tue Oct 30 14:56:36 2007 +0100
|
||||||
|
|
||||||
|
Add ATSTK100[234] to MAINTAINERS
|
||||||
|
|
||||||
|
Add all the ATSTK1000 daughterboards to MAINTAINERS along with their
|
||||||
|
"mother". Also update the entry for ATSTK1000 to be not only about the
|
||||||
|
AP7000 CPU; it's intended to handle all CPUs in the AT32AP family.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 64ff2357b1727213803591813dbc779c924bf772
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Mon Oct 29 13:02:54 2007 +0100
|
||||||
|
|
||||||
|
AVR32: Add support for the ATSTK1004 board
|
||||||
|
|
||||||
|
ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU,
|
||||||
|
which is a derivative of AT32AP7000.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 667568db157f374b85abd7e03596ddd1f0b25681
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Mon Oct 29 13:02:54 2007 +0100
|
||||||
|
|
||||||
|
AVR32: Add support for the ATSTK1003 board
|
||||||
|
|
||||||
|
ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU,
|
||||||
|
which is a derivative of AT32AP7000.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 5fee84a794a51ec830548cda485a770efb018b92
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Mon Oct 29 13:23:33 2007 +0100
|
||||||
|
|
||||||
|
AVR32: Make some AT32AP700x peripherals optional
|
||||||
|
|
||||||
|
Add a chip-features file providing definitions of the form
|
||||||
|
|
||||||
|
AT32AP700x_CHIP_HAS_<peripheral>
|
||||||
|
|
||||||
|
to indicate the availability of the given peripheral on the currently
|
||||||
|
selected chip.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 36f28f8a9605ee5dcfa330482cfc62171261af97
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Mon Oct 29 13:09:56 2007 +0100
|
||||||
|
|
||||||
|
AVR32: Rename at32ap7000 -> at32ap700x
|
||||||
|
|
||||||
|
The SoC-specific code for all the AT32AP700x CPUs is practically
|
||||||
|
identical; the only difference is that some chips have less features
|
||||||
|
than others. By doing this rename, we can add support for the AP7000
|
||||||
|
derivatives simply by making some features conditional.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 4d5fa99c73f354e7cf985efcf417ea55ca2f6a5e
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Fri Jun 29 18:22:34 2007 +0200
|
||||||
|
|
||||||
|
atmel_mci: Show SR when block read fails
|
||||||
|
|
||||||
|
Show controller status as well as card status when an error occurs
|
||||||
|
during block read.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 12d30aa79779c2aa7a998bbae4c075f822a53004
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Thu Dec 13 12:56:34 2007 +0100
|
||||||
|
|
||||||
|
cfi_flash: Use map_physmem() and unmap_physmem()
|
||||||
|
|
||||||
|
Use map_physmem() and unmap_physmem() to convert from physical to
|
||||||
|
virtual addresses. This gives the arch a chance to provide an uncached
|
||||||
|
mapping for flash accesses.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 4d7d6936eb29af7cca330937808312aa5f61454d
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Thu Dec 13 12:56:33 2007 +0100
|
||||||
|
|
||||||
|
Introduce map_physmem() and unmap_physmem()
|
||||||
|
|
||||||
|
map_physmem() returns a virtual address which can be used to access a
|
||||||
|
given physical address without involving the cache. unmap_physmem()
|
||||||
|
should be called when the virtual address returned by map_physmem() is
|
||||||
|
no longer needed.
|
||||||
|
|
||||||
|
This patch adds a stub implementation which simply returns the
|
||||||
|
physical address cast to a uchar * for all architectures except AVR32,
|
||||||
|
which converts the physical address to an uncached virtual mapping.
|
||||||
|
unmap_physmem() is a no-op on all architectures, but if any
|
||||||
|
architecture needs to do such mappings through the TLB, this is the
|
||||||
|
hook where those TLB entries can be invalidated.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit cdbaefb5f5f03e54455d0439dcf6dbd97ead1f9d
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Thu Dec 13 12:56:32 2007 +0100
|
||||||
|
|
||||||
|
cfi_flash: Introduce read and write accessors
|
||||||
|
|
||||||
|
Introduce flash_read{8,16,32,64) and flash_write{8,16,32,64} and use
|
||||||
|
them to access the flash memory. This makes it clearer when the flash
|
||||||
|
is actually being accessed; merely dereferencing a volatile pointer
|
||||||
|
looks just like any other kind of access.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 812711ce6b3a386125dcf0d6a59588e461abbb87
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Thu Dec 13 12:56:31 2007 +0100
|
||||||
|
|
||||||
|
Implement __raw_{read,write}[bwl] on all architectures
|
||||||
|
|
||||||
|
This adds implementations of __raw_read[bwl] and __raw_write[bwl] to
|
||||||
|
m68k, ppc, nios and nios2. The m68k and ppc implementations were taken
|
||||||
|
from Linux.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit be60a9021c82fc5aecd5b2b1fc96f70a9c81bbcd
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Sat Oct 6 18:55:36 2007 +0200
|
||||||
|
|
||||||
|
cfi_flash: Reorder functions and eliminate extra prototypes
|
||||||
|
|
||||||
|
Reorder the functions in cfi_flash.c so that each function only uses
|
||||||
|
functions that have been defined before it. This allows the static
|
||||||
|
prototype declarations near the top to be eliminated and might allow
|
||||||
|
gcc to do a better job inlining functions.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 3055793bcbdf24b1f8117f606ffb766d32eb766f
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Thu Dec 13 12:56:29 2007 +0100
|
||||||
|
|
||||||
|
cfi_flash: Make some needlessly global functions static
|
||||||
|
|
||||||
|
Make functions not declared in any header file static.
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 7e5b9b471518c5652febc68ba62b432193d6abf4
|
||||||
|
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
Date: Thu Dec 13 12:56:28 2007 +0100
|
||||||
|
|
||||||
|
cfi_flash: Break long lines
|
||||||
|
|
||||||
|
This patch tries to keep all lines in the cfi_flash driver below 80
|
||||||
|
columns. There are a few lines left which don't fit this requirement
|
||||||
|
because I couldn't find any trivial way to break them (i.e. it would
|
||||||
|
take some restructuring, which I intend to do in a later patch.)
|
||||||
|
|
||||||
|
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
|
commit 42026c9cb3a76849b41e6e24abfb7b56807a5c1a
|
||||||
|
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||||
|
Date: Tue Dec 11 13:59:57 2007 +0100
|
||||||
|
|
||||||
|
CFI: synchronize command offsets with Linux CFI driver
|
||||||
|
|
||||||
|
Fixes non-working CFI Flash on the Inka4x0 board.
|
||||||
|
|
||||||
|
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||||
|
|
||||||
|
commit 8ff3de61fc5f9b3b21647bce081a3b7f710f0d4d
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Fri Dec 7 12:17:34 2007 -0600
|
||||||
|
|
||||||
|
Handle MPC85xx PCIe reset errata (PCI-Ex 38)
|
||||||
|
|
||||||
|
On the MPC85xx boards that have PCIe enable the PCIe errata fix.
|
||||||
|
(MPC8544DS, MPC8548CDS, MPC8568MDS).
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 82ac8c97145a4c3bf8b3dbfad00fa96e920f9b9c
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Fri Dec 7 12:04:30 2007 -0600
|
||||||
|
|
||||||
|
Update Freescale MPC85xx ADS/CDS/MDS board config
|
||||||
|
|
||||||
|
* Enabled CONFIG_CMD_ELF
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit d435793229ce29a42797c1edc39f5b34f987f91a
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Fri Dec 7 04:59:26 2007 -0600
|
||||||
|
|
||||||
|
Handle Asynchronous DDR clock on 85xx
|
||||||
|
|
||||||
|
The MPC8572 introduces the concept of an asynchronous DDR clock with
|
||||||
|
regards to the platform clock.
|
||||||
|
|
||||||
|
Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
|
||||||
|
mode.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 22abb2d2eaf7b795a6923c6273ec9cb53fda9a10
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 10:34:28 2007 -0600
|
||||||
|
|
||||||
|
Update Freescale MPC85xx ADS/CDS/MDS board config
|
||||||
|
|
||||||
|
* Removed some misc environment setup
|
||||||
|
* Enabled CONFIG_CMDLINE_EDITING
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 415a613babb84d5e5d5b42e8e553868c71fc3a64
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 10:47:44 2007 -0600
|
||||||
|
|
||||||
|
Move the MPC8541/MPC8555/MPC8548 CDS board under board/freescale.
|
||||||
|
|
||||||
|
Minor path corrections needed to ensure buildability.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit c2d943ffbfd3359b3b45d177b437379d2cb86fbf
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 10:16:18 2007 -0600
|
||||||
|
|
||||||
|
Move the MPC8540 ADS board under board/freescale.
|
||||||
|
|
||||||
|
Minor path corrections needed to ensure buildability.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 870ceac5b3a3486c109396e005af81ae762b5710
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 10:14:50 2007 -0600
|
||||||
|
|
||||||
|
Move the MPC8560 ADS board under board/freescale.
|
||||||
|
|
||||||
|
Minor path corrections needed to ensure buildability.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit acbca876fb3fec25cd9c55b0efc81ff618ff5262
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 10:13:47 2007 -0600
|
||||||
|
|
||||||
|
Move the MPC8568 MDS board under board/freescale.
|
||||||
|
|
||||||
|
Minor path corrections needed to ensure buildability.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit a853d56c59b33415304531443633808736acfc6e
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 02:18:59 2007 -0600
|
||||||
|
|
||||||
|
Use standard LAWAR_TRGT_IF_* defines for LAW setup on 85xx
|
||||||
|
|
||||||
|
We already had defines for LAWAR_TRGT_IF_* that we should use
|
||||||
|
rather than creating new ones. Also, added some missing defines for
|
||||||
|
PCIE targets.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 04db400892da37b76a585e332a0c137954ad2015
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 02:10:09 2007 -0600
|
||||||
|
|
||||||
|
Stop using immap_t on 85xx
|
||||||
|
|
||||||
|
In the future the offsets to various blocks may not be in same location.
|
||||||
|
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
|
||||||
|
instead of getting it via &immap.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 2714223f8e04ab3e4133ff65872eef366d90bfea
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 01:23:09 2007 -0600
|
||||||
|
|
||||||
|
Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdt
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit c480861bf000156e6a3e932c258db59ff2212dd3
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 01:06:19 2007 -0600
|
||||||
|
|
||||||
|
Update MPC8568 MDS to use libfdt
|
||||||
|
|
||||||
|
Updated the MPC8568 MDS config to use libfdt and assume use of aliases for
|
||||||
|
ethernet, pci, and serial for the various fixups that are done.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 1563f56e0c68f6920f956382d6d13bee3f01c0f7
|
||||||
|
Author: Haiying Wang <Haiying.Wang@freescale.com>
|
||||||
|
Date: Wed Nov 14 15:52:06 2007 -0500
|
||||||
|
|
||||||
|
Add PCI Express support on MPC8568MDS
|
||||||
|
|
||||||
|
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit b90d25497625b90ffa3f2911a0895ca237556ff5
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 00:11:44 2007 -0600
|
||||||
|
|
||||||
|
Update MPC85xx CDS to use libfdt
|
||||||
|
|
||||||
|
Updated the MPC85xx CDS config to use libfdt and assume use of aliases for
|
||||||
|
ethernet, pci, and serial for the various fixups that are done.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 0fd5ec66b10521a057ad73e69ab5f0f9eafba255
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Wed Nov 28 22:54:27 2007 -0600
|
||||||
|
|
||||||
|
Update MPC8540 ADS to use libfdt
|
||||||
|
|
||||||
|
Updated the MPC8540 ADS config to use libfdt and assume use of aliases for
|
||||||
|
ethernet, pci, and serial for the various fixups that are done.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 5ce715802f6c50dc78b3405b92f184b1e3710519
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Wed Nov 28 22:40:31 2007 -0600
|
||||||
|
|
||||||
|
Update MPC8560 ADS to use libfdt
|
||||||
|
|
||||||
|
Updated the MPC8560 ADS config to use libfdt and assume use of aliases for
|
||||||
|
ethernet, pci, and serial for the various fixups that are done.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit aafeefbdb8b029f5ca2a195598d0a501a606eea9
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Wed Nov 28 00:36:33 2007 -0600
|
||||||
|
|
||||||
|
Stop using immap_t for cpm offset on 85xx
|
||||||
|
|
||||||
|
In the future the offsets to various blocks may not be in same location.
|
||||||
|
Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers
|
||||||
|
instead of getting it via &immap->im_cpm.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit f59b55a5b8fcadaa99781ba48e7a38e956afa527
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Tue Nov 27 23:25:02 2007 -0600
|
||||||
|
|
||||||
|
Stop using immap_t for guts offset on 85xx
|
||||||
|
|
||||||
|
In the future the offsets to various blocks may not be in same location.
|
||||||
|
Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers
|
||||||
|
instead of getting it via &immap->im_gur.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 50c03c8cf494d91cdec39670d95337c743e16ec9
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Tue Nov 27 22:42:34 2007 -0600
|
||||||
|
|
||||||
|
Update MPC8544 DS config
|
||||||
|
|
||||||
|
* Removed HAS_ETH2/HAS_ETH3 - MPC8544 only has TSEC1/2
|
||||||
|
* Removed some misc environment setup
|
||||||
|
* Moved to using fdtfile & fdtaddr as fdt env var names
|
||||||
|
* Enabled CONFIG_CMDLINE_EDITING
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit addce57e2e4c49e77ffb2020a84690713bb18b47
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Mon Nov 26 17:12:24 2007 -0600
|
||||||
|
|
||||||
|
Update MPC8544DS to use libfdt
|
||||||
|
|
||||||
|
Updated the MPC8544DS config to use libfdt and assume use of aliases for
|
||||||
|
ethernet, pci, and serial for the various fixups that are done.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit f852ce72f100cabd1f11c21c085a0ad8eca9fb65
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Thu Nov 29 00:15:30 2007 -0600
|
||||||
|
|
||||||
|
Add libfdt based ft_cpu_setup for mpc85xx
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 9692c2734a47f23b44a0f68042a3e2ca8d1bfb39
|
||||||
|
Author: Stefan Roese <sr@denx.de>
|
||||||
|
Date: Sat Dec 8 08:25:09 2007 +0100
|
||||||
|
|
||||||
|
CFI: Coding style cleanup
|
||||||
|
|
||||||
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||||
|
|
||||||
|
commit 81b20ccc2d795ae9a1199db5a50ad9c28d1e4d22
|
||||||
|
Author: Michael Schwingen <michael@schwingen.org>
|
||||||
|
Date: Fri Dec 7 23:35:02 2007 +0100
|
||||||
|
|
||||||
|
CFI: support JEDEC flash roms in CFI-flash framework
|
||||||
|
|
||||||
|
The following patch adds support for non-CFI flash ROMS, by hooking into the
|
||||||
|
CFI flash code and using most of its code, as recently discussed here in the
|
||||||
|
thread "Mixing CFI and non-CFI flashs".
|
||||||
|
|
||||||
|
Signed-off-by: Michael Schwingen <michael@schwingen.org>
|
||||||
|
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||||
|
|
||||||
|
commit c01b17dd856fa120b2970f50d9598546a4927ec3
|
||||||
|
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||||
|
Date: Wed Nov 28 21:24:50 2007 -0500
|
||||||
|
|
||||||
|
Conditionally compile fdt_fixup_ethernet()
|
||||||
|
|
||||||
|
Fix compiler warnings: On boards that don't have ethernets defined,
|
||||||
|
don't compile fdt_fixup_ethernet().
|
||||||
|
|
||||||
|
commit 246d4ae6bc282bc1841224e1c5fc49dc925e0bf7
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Tue Nov 27 21:59:46 2007 -0600
|
||||||
|
|
||||||
|
Convert boards that set memory node to use fdt_fixup_memory()
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 151c8b09b35eebe8fd9139cb6c1d91c27b22f058
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Mon Nov 26 17:06:15 2007 -0600
|
||||||
|
|
||||||
|
Added fdt_fixup_stdout that uses aliases to set linux,stdout-path
|
||||||
|
|
||||||
|
We use a combination of the serialN alias and CONFIG_CONS_INDEX to
|
||||||
|
determine which serial alias we should set linux,stdout-path to.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 3c9272813fad84c691d0e4989bb18a3ffebdebfc
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Mon Nov 26 14:57:45 2007 -0600
|
||||||
|
|
||||||
|
Add common memory fixup function
|
||||||
|
|
||||||
|
Add the function fdt_fixup_memory() to fixup the /memory node of the fdt
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 9c9109e7fcf7ac2ca19c95b8ac54b8d1c773b157
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Mon Nov 26 11:19:12 2007 -0600
|
||||||
|
|
||||||
|
Conditionally compile fdt_support.c
|
||||||
|
|
||||||
|
Modify common/Makefile to conditionally compile fdt_support.c based
|
||||||
|
on CONFIG_OF_LIBFDT.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit d88e7ba0980773479e1a64badb293116071b7ef0
|
||||||
|
Author: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
Date: Mon Nov 26 10:41:40 2007 -0600
|
||||||
|
|
||||||
|
Fix build breakage due to libfdt import
|
||||||
|
|
||||||
|
The IDS8247 got lost in the update and need an API update
|
||||||
|
do to rename of functions in libfdt.
|
||||||
|
|
||||||
|
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
||||||
|
|
||||||
|
commit 28f384b171bbf1fb2dafb1046e6d259a6b2f8714
|
||||||
|
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||||
|
Date: Fri Nov 23 19:43:20 2007 -0500
|
||||||
|
|
||||||
|
Add spaces around the = in the fdt print format.
|
||||||
|
|
||||||
|
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
|
||||||
|
|
||||||
|
commit 29592ecba3b932b9b152bcec6c0c0806412db4a3
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Fri Dec 7 01:25:38 2007 +0900
|
||||||
|
|
||||||
|
sh: Moved driver of the SuperH dependence
|
||||||
|
|
||||||
|
The composition of the directory in the drivers/ changed.
|
||||||
|
I moved SuperH serial driver and marubun PCMCIA driver.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit 41be969f4957115ed7b1fe8b890bfaee99d7a7a2
|
||||||
|
Author: Wolfgang Denk <wd@denx.de>
|
||||||
|
Date: Thu Dec 6 10:21:19 2007 +0100
|
||||||
|
|
||||||
|
Release v1.3.1
|
||||||
|
|
||||||
|
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||||
|
|
||||||
|
commit cf5933ba1e97a1cd8f5f24070e820f21d976eaeb
|
||||||
|
Author: Wolfgang Denk <wd@denx.de>
|
||||||
|
Date: Thu Dec 6 10:21:03 2007 +0100
|
||||||
|
|
||||||
|
ADS5121 Board: fix compile problem.
|
||||||
|
|
||||||
|
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||||
|
|
||||||
|
commit 8d4f040a3c15036a6ea25a9c39e7d89fefa8440d
|
||||||
|
Author: Wolfgang Denk <wd@denx.de>
|
||||||
|
Date: Mon Dec 3 00:15:28 2007 +0100
|
||||||
|
|
||||||
|
Prepare for 1.3.1-rc1
|
||||||
|
|
||||||
|
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||||
|
|
||||||
|
commit 260eea5676ca46903a335686cc020b29c4ca46fe
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Thu Nov 29 01:21:54 2007 +0900
|
||||||
|
|
||||||
|
sh: Add SuperH boards maintainer to MAINTAINERS file
|
||||||
|
|
||||||
|
Add MS7750SE and MS7722SE's board maintainer to MAINTAINERS file.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit aa9c4f1d22701a92347c1c81f34d12c8ad3a3747
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Thu Nov 29 00:13:04 2007 +0900
|
||||||
|
|
||||||
|
sh: Add ms7750se support in MAKEALL
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit c7144373427a178332bf9754131c8c34c52c200a
|
||||||
|
Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||||
|
Date: Tue Nov 27 09:44:53 2007 +0100
|
||||||
|
|
||||||
|
sh: Add sh3 and sh4 support in MAKEALL
|
||||||
|
|
||||||
|
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit 130080874a3d28450098481a262c5f7c855e908d
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Nov 25 02:51:17 2007 +0900
|
||||||
|
|
||||||
|
sh: Add document for SuperH.
|
||||||
|
|
||||||
|
This document is a summary of information concerning SuperH of U-Boot.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit 33ecdc2f9d64926e1a6067b28f3a0aefc3b6d23d
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Nov 25 02:39:31 2007 +0900
|
||||||
|
|
||||||
|
sh: Add marubun's pcmcia driver
|
||||||
|
|
||||||
|
Marubun pcmcia is a chip for PCMCIA used with SuperH.
|
||||||
|
Of course, this can be used even by other architectures.
|
||||||
|
When use this driver, came to be able to use CompactFlash
|
||||||
|
and Ethernet.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit febd86b969b975289ed948f1ac0eb9722da41ced
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Nov 25 02:32:13 2007 +0900
|
||||||
|
|
||||||
|
sh: Update SuperH SCIF driver
|
||||||
|
|
||||||
|
- Changed volatile unsigned to vu_.
|
||||||
|
- Changed Makefile for kconfig.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
commit a5f601fd1b1278deae5aa9fc27a232b0d1c1c788
|
commit a5f601fd1b1278deae5aa9fc27a232b0d1c1c788
|
||||||
Author: Wolfgang Denk <wd@denx.de>
|
Author: Wolfgang Denk <wd@denx.de>
|
||||||
Date: Mon Nov 26 19:18:21 2007 +0100
|
Date: Mon Nov 26 19:18:21 2007 +0100
|
||||||
|
@ -1927,6 +2611,56 @@ Date: Mon Sep 24 00:08:37 2007 +0200
|
||||||
|
|
||||||
synchronizition with mainline
|
synchronizition with mainline
|
||||||
|
|
||||||
|
commit eda3e1e6619ad0bee94ae4b16c99d88e77e2af13
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Sep 23 02:42:38 2007 +0900
|
||||||
|
|
||||||
|
sh: Add support command of ide with sh
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit d91ea45d15cf8e0987456bd211ffbb650824b6f1
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Sep 23 02:38:42 2007 +0900
|
||||||
|
|
||||||
|
sh: Update Makefile
|
||||||
|
|
||||||
|
Add support MS7722SE01 to Makefile.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit 6c0bbdccd379f5c8702af9e0765294c2fb7472a6
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Sep 23 02:31:13 2007 +0900
|
||||||
|
|
||||||
|
sh: Add support Renesas sh7722 processor and Hitachi MS7722SE01 board
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit 047375bfa4c3052fa50a748da7ff89e9dad3b364
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Sep 23 02:19:24 2007 +0900
|
||||||
|
|
||||||
|
sh: Update MS7750SE01 platform
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit 516ad760db3553766267ada01b7d5d727faa4bbd
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Sep 23 02:17:08 2007 +0900
|
||||||
|
|
||||||
|
sh: Remove comment out code from include/asm-sh/cpu_sh4.h
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit b02bad128669e567fce87d8df823b06a0144b8db
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
Date: Sun Sep 23 02:12:30 2007 +0900
|
||||||
|
|
||||||
|
sh: Update core code of SuperH.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
commit 66dcad3a9a53e0766d90e0084123bd8529522fb0
|
commit 66dcad3a9a53e0766d90e0084123bd8529522fb0
|
||||||
Author: Wolfgang Denk <wd@denx.de>
|
Author: Wolfgang Denk <wd@denx.de>
|
||||||
Date: Thu Sep 20 00:04:14 2007 +0200
|
Date: Thu Sep 20 00:04:14 2007 +0200
|
||||||
|
@ -8634,6 +9368,24 @@ Date: Tue May 15 07:55:42 2007 -0700
|
||||||
|
|
||||||
Fix to compile JSE against 20070514 git of u-boot
|
Fix to compile JSE against 20070514 git of u-boot
|
||||||
|
|
||||||
|
commit 69df3c4da0c93017cceb25a366e794570bd0ed98
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@rahute.(none)>
|
||||||
|
Date: Sun May 13 21:01:03 2007 +0900
|
||||||
|
|
||||||
|
sh: MS7750SE support.
|
||||||
|
|
||||||
|
This adds support for the Hitachi MS7750SE.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
commit 0b135cfc2e524dc249b75057b55dd4cc09842e27
|
||||||
|
Author: Nobuhiro Iwamatsu <iwamatsu@rahute.(none)>
|
||||||
|
Date: Sun May 13 20:58:00 2007 +0900
|
||||||
|
|
||||||
|
sh: First support code of SuperH.
|
||||||
|
|
||||||
|
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
commit 61936667e86a250ae12fd2dc189d3588f0a59e0b
|
commit 61936667e86a250ae12fd2dc189d3588f0a59e0b
|
||||||
Author: Stefan Roese <sr@denx.de>
|
Author: Stefan Roese <sr@denx.de>
|
||||||
Date: Fri May 11 12:01:49 2007 +0200
|
Date: Fri May 11 12:01:49 2007 +0200
|
||||||
|
|
11
CREDITS
11
CREDITS
|
@ -117,7 +117,7 @@ N: Arun Dharankar
|
||||||
E: ADharankar@ATTBI.Com
|
E: ADharankar@ATTBI.Com
|
||||||
D: threads / scheduler example code
|
D: threads / scheduler example code
|
||||||
|
|
||||||
N: Kári Davíðsson
|
N: K?ri Dav??sson
|
||||||
E: kd@flaga.is
|
E: kd@flaga.is
|
||||||
D: FLAGA DM Support
|
D: FLAGA DM Support
|
||||||
|
|
||||||
|
@ -143,7 +143,7 @@ E: info@elste.org
|
||||||
D: Port for the ModNET50 Board, NET+50 CPU Port
|
D: Port for the ModNET50 Board, NET+50 CPU Port
|
||||||
W: http://www.imms.de
|
W: http://www.imms.de
|
||||||
|
|
||||||
N: Daniel Engström
|
N: Daniel Engstr?m
|
||||||
E: daniel@omicron.se
|
E: daniel@omicron.se
|
||||||
D: x86 port, Support for sc520_cdp board
|
D: x86 port, Support for sc520_cdp board
|
||||||
|
|
||||||
|
@ -334,7 +334,7 @@ N: Frank Morauf
|
||||||
E: frank.morauf@salzbrenner.com
|
E: frank.morauf@salzbrenner.com
|
||||||
D: Support for Embedded Planet RPX Super Board
|
D: Support for Embedded Planet RPX Super Board
|
||||||
|
|
||||||
N: David Müller
|
N: David M?ller
|
||||||
E: d.mueller@elsoft.ch
|
E: d.mueller@elsoft.ch
|
||||||
D: Support for Samsung ARM920T SMDK2410 eval board
|
D: Support for Samsung ARM920T SMDK2410 eval board
|
||||||
|
|
||||||
|
@ -499,3 +499,8 @@ N: Alex Zuepke
|
||||||
E: azu@sysgo.de
|
E: azu@sysgo.de
|
||||||
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
|
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
|
||||||
W: www.elinos.com
|
W: www.elinos.com
|
||||||
|
|
||||||
|
N: Nobuhiro Iwamatsu
|
||||||
|
E: iwamatsu@nigauri.org
|
||||||
|
D: Support for SuperH, MS7750SE01 and MS7722SE01 boards.
|
||||||
|
W: http://www.nigauri.org/~iwamatsu/
|
||||||
|
|
23
MAINTAINERS
23
MAINTAINERS
|
@ -146,7 +146,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
|
||||||
CPCI4052 PPC405GP
|
CPCI4052 PPC405GP
|
||||||
CPCI405AB PPC405GP
|
CPCI405AB PPC405GP
|
||||||
CPCI405DT PPC405GP
|
CPCI405DT PPC405GP
|
||||||
CPCI440 PPC440GP
|
|
||||||
CPCIISER4 PPC405GP
|
CPCIISER4 PPC405GP
|
||||||
DASA_SIM IOP480 (PPC401)
|
DASA_SIM IOP480 (PPC401)
|
||||||
DP405 PPC405EP
|
DP405 PPC405EP
|
||||||
|
@ -159,6 +158,7 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
|
||||||
PCI405 PPC405GP
|
PCI405 PPC405GP
|
||||||
PLU405 PPC405EP
|
PLU405 PPC405EP
|
||||||
PMC405 PPC405GP
|
PMC405 PPC405GP
|
||||||
|
PMC440 PPC440EPx
|
||||||
VOH405 PPC405EP
|
VOH405 PPC405EP
|
||||||
VOM405 PPC405EP
|
VOM405 PPC405EP
|
||||||
WUH405 PPC405EP
|
WUH405 PPC405EP
|
||||||
|
@ -204,6 +204,10 @@ Murray Jensen <Murray.Jensen@csiro.au>
|
||||||
cogent_mpc8260 MPC8260
|
cogent_mpc8260 MPC8260
|
||||||
hymod MPC8260
|
hymod MPC8260
|
||||||
|
|
||||||
|
Larry Johnson <lrj@acm.org>
|
||||||
|
|
||||||
|
korat PPC440EPx
|
||||||
|
|
||||||
Brad Kemp <Brad.Kemp@seranoa.com>
|
Brad Kemp <Brad.Kemp@seranoa.com>
|
||||||
|
|
||||||
ppmc8260 MPC8260
|
ppmc8260 MPC8260
|
||||||
|
@ -633,7 +637,22 @@ Hayden Fraser <Hayden.Fraser@freescale.com>
|
||||||
|
|
||||||
Haavard Skinnemoen <hskinnemoen@atmel.com>
|
Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||||
|
|
||||||
ATSTK1000 AT32AP7000
|
ATSTK1000 AT32AP7xxx
|
||||||
|
ATSTK1002 AT32AP7000
|
||||||
|
ATSTK1003 AT32AP7001
|
||||||
|
ATSTK1004 AT32AP7002
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
# SuperH Systems: #
|
||||||
|
# #
|
||||||
|
# Maintainer Name, Email Address #
|
||||||
|
# Board CPU #
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
Nobuhiro Iwmaatsu <iwamatsu@nigauri.org>
|
||||||
|
|
||||||
|
MS7750SE SH7750
|
||||||
|
MS7722SE SH7722
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
# End of MAINTAINERS list #
|
# End of MAINTAINERS list #
|
||||||
|
|
26
MAKEALL
26
MAKEALL
|
@ -168,7 +168,6 @@ LIST_4xx=" \
|
||||||
CPCI4052 \
|
CPCI4052 \
|
||||||
CPCI405AB \
|
CPCI405AB \
|
||||||
CPCI405DT \
|
CPCI405DT \
|
||||||
CPCI440 \
|
|
||||||
CPCIISER4 \
|
CPCIISER4 \
|
||||||
CRAYL1 \
|
CRAYL1 \
|
||||||
csb272 \
|
csb272 \
|
||||||
|
@ -191,6 +190,7 @@ LIST_4xx=" \
|
||||||
katmai \
|
katmai \
|
||||||
kilauea \
|
kilauea \
|
||||||
kilauea_nand \
|
kilauea_nand \
|
||||||
|
korat \
|
||||||
luan \
|
luan \
|
||||||
lwmon5 \
|
lwmon5 \
|
||||||
makalu \
|
makalu \
|
||||||
|
@ -208,6 +208,7 @@ LIST_4xx=" \
|
||||||
PIP405 \
|
PIP405 \
|
||||||
PLU405 \
|
PLU405 \
|
||||||
PMC405 \
|
PMC405 \
|
||||||
|
PMC440 \
|
||||||
PPChameleonEVB \
|
PPChameleonEVB \
|
||||||
rainier \
|
rainier \
|
||||||
sbc405 \
|
sbc405 \
|
||||||
|
@ -647,6 +648,8 @@ LIST_coldfire=" \
|
||||||
|
|
||||||
LIST_avr32=" \
|
LIST_avr32=" \
|
||||||
atstk1002 \
|
atstk1002 \
|
||||||
|
atstk1003 \
|
||||||
|
atstk1004 \
|
||||||
"
|
"
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
@ -660,6 +663,23 @@ LIST_blackfin=" \
|
||||||
bf561-ezkit \
|
bf561-ezkit \
|
||||||
"
|
"
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
## SH Systems
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
LIST_sh4=" \
|
||||||
|
ms7750se \
|
||||||
|
ms7722se \
|
||||||
|
"
|
||||||
|
|
||||||
|
LIST_sh3=""
|
||||||
|
|
||||||
|
|
||||||
|
LIST_sh=" \
|
||||||
|
${LIST_sh3} \
|
||||||
|
${LIST_sh4} \
|
||||||
|
"
|
||||||
|
|
||||||
#-----------------------------------------------------------------------
|
#-----------------------------------------------------------------------
|
||||||
|
|
||||||
#----- for now, just run PPC by default -----
|
#----- for now, just run PPC by default -----
|
||||||
|
@ -694,7 +714,9 @@ do
|
||||||
mips|mips_el| \
|
mips|mips_el| \
|
||||||
nios|nios2| \
|
nios|nios2| \
|
||||||
ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
|
ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
|
||||||
x86|I486|TSEC)
|
x86|I486|TSEC| \
|
||||||
|
sh|sh4|sh3 \
|
||||||
|
)
|
||||||
for target in `eval echo '$LIST_'${arg}`
|
for target in `eval echo '$LIST_'${arg}`
|
||||||
do
|
do
|
||||||
build_target ${target}
|
build_target ${target}
|
||||||
|
|
49
Makefile
49
Makefile
|
@ -152,6 +152,9 @@ endif
|
||||||
ifeq ($(ARCH),avr32)
|
ifeq ($(ARCH),avr32)
|
||||||
CROSS_COMPILE = avr32-linux-
|
CROSS_COMPILE = avr32-linux-
|
||||||
endif
|
endif
|
||||||
|
ifeq ($(ARCH),sh)
|
||||||
|
CROSS_COMPILE = sh4-linux-
|
||||||
|
endif
|
||||||
endif
|
endif
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
@ -1160,9 +1163,6 @@ CPCI405AB_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
|
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci405 esd
|
||||||
@echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk
|
@echo "BOARD_REVISION = $(@:_config=)" >> $(obj)include/config.mk
|
||||||
|
|
||||||
CPCI440_config: unconfig
|
|
||||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpci440 esd
|
|
||||||
|
|
||||||
CPCIISER4_config: unconfig
|
CPCIISER4_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
|
@$(MKCONFIG) $(@:_config=) ppc ppc4xx cpciiser4 esd
|
||||||
|
|
||||||
|
@ -1231,6 +1231,9 @@ haleakala_nand_config: unconfig
|
||||||
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp
|
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp
|
||||||
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
||||||
|
|
||||||
|
korat_config: unconfig
|
||||||
|
@$(MKCONFIG) $(@:_config=) ppc ppc4xx korat
|
||||||
|
|
||||||
luan_config: unconfig
|
luan_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
|
@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
|
||||||
|
|
||||||
|
@ -1283,6 +1286,9 @@ PLU405_config: unconfig
|
||||||
PMC405_config: unconfig
|
PMC405_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
|
@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc405 esd
|
||||||
|
|
||||||
|
PMC440_config: unconfig
|
||||||
|
@$(MKCONFIG) $(@:_config=) ppc ppc4xx pmc440 esd
|
||||||
|
|
||||||
PPChameleonEVB_config \
|
PPChameleonEVB_config \
|
||||||
PPChameleonEVB_BA_25_config \
|
PPChameleonEVB_BA_25_config \
|
||||||
PPChameleonEVB_ME_25_config \
|
PPChameleonEVB_ME_25_config \
|
||||||
|
@ -1928,7 +1934,7 @@ TQM834x_config: unconfig
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
MPC8540ADS_config: unconfig
|
MPC8540ADS_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads
|
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale
|
||||||
|
|
||||||
MPC8540EVAL_config \
|
MPC8540EVAL_config \
|
||||||
MPC8540EVAL_33_config \
|
MPC8540EVAL_33_config \
|
||||||
|
@ -1952,7 +1958,7 @@ MPC8540EVAL_66_slave_config: unconfig
|
||||||
@$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval
|
@$(MKCONFIG) -a MPC8540EVAL ppc mpc85xx mpc8540eval
|
||||||
|
|
||||||
MPC8560ADS_config: unconfig
|
MPC8560ADS_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
|
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads freescale
|
||||||
|
|
||||||
MPC8541CDS_legacy_config \
|
MPC8541CDS_legacy_config \
|
||||||
MPC8541CDS_config: unconfig
|
MPC8541CDS_config: unconfig
|
||||||
|
@ -1962,7 +1968,7 @@ MPC8541CDS_config: unconfig
|
||||||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||||
echo "... legacy" ; \
|
echo "... legacy" ; \
|
||||||
fi
|
fi
|
||||||
@$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
|
@$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds freescale
|
||||||
|
|
||||||
MPC8544DS_config: unconfig
|
MPC8544DS_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
|
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
|
||||||
|
@ -1975,7 +1981,7 @@ MPC8548CDS_config: unconfig
|
||||||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||||
echo "... legacy" ; \
|
echo "... legacy" ; \
|
||||||
fi
|
fi
|
||||||
@$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
|
@$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds freescale
|
||||||
|
|
||||||
MPC8555CDS_legacy_config \
|
MPC8555CDS_legacy_config \
|
||||||
MPC8555CDS_config: unconfig
|
MPC8555CDS_config: unconfig
|
||||||
|
@ -1985,10 +1991,10 @@ MPC8555CDS_config: unconfig
|
||||||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||||
echo "... legacy" ; \
|
echo "... legacy" ; \
|
||||||
fi
|
fi
|
||||||
@$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
|
@$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds freescale
|
||||||
|
|
||||||
MPC8568MDS_config: unconfig
|
MPC8568MDS_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
|
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds freescale
|
||||||
|
|
||||||
PM854_config: unconfig
|
PM854_config: unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
|
@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
|
||||||
|
@ -2673,7 +2679,30 @@ bf561-ezkit_config: unconfig
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
atstk1002_config : unconfig
|
atstk1002_config : unconfig
|
||||||
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap7000
|
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
|
||||||
|
|
||||||
|
atstk1003_config : unconfig
|
||||||
|
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
|
||||||
|
|
||||||
|
atstk1004_config : unconfig
|
||||||
|
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
#########################################################################
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
## sh4 (Renesas SuperH)
|
||||||
|
#########################################################################
|
||||||
|
ms7750se_config: unconfig
|
||||||
|
@ >include/config.h
|
||||||
|
@echo "#define CONFIG_MS7750SE 1" >> include/config.h
|
||||||
|
@./mkconfig -a $(@:_config=) sh sh4 ms7750se
|
||||||
|
|
||||||
|
ms7722se_config : unconfig
|
||||||
|
@ >include/config.h
|
||||||
|
@echo "#define CONFIG_MS7722SE 1" >> include/config.h
|
||||||
|
@./mkconfig -a $(@:_config=) sh sh4 ms7722se
|
||||||
|
|
||||||
#########################################################################
|
#########################################################################
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
4
README
4
README
|
@ -235,9 +235,7 @@ The following options need to be configured:
|
||||||
- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
|
- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
|
||||||
|
|
||||||
- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
|
- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
|
||||||
Define exactly one of
|
Define exactly one, e.g. CONFIG_ATSTK1002
|
||||||
CONFIG_ATSTK1002
|
|
||||||
|
|
||||||
|
|
||||||
- CPU Module Type: (if CONFIG_COGENT is defined)
|
- CPU Module Type: (if CONFIG_COGENT is defined)
|
||||||
Define exactly one of
|
Define exactly one of
|
||||||
|
|
|
@ -25,6 +25,8 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <ppc4xx.h>
|
#include <ppc4xx.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
|
#include <libfdt.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/gpio.h>
|
#include <asm/gpio.h>
|
||||||
|
@ -533,3 +535,24 @@ int post_hotkeys_pressed(void)
|
||||||
return (ctrlc());
|
return (ctrlc());
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||||
|
void ft_board_setup(void *blob, bd_t *bd)
|
||||||
|
{
|
||||||
|
u32 val[4];
|
||||||
|
int rc;
|
||||||
|
|
||||||
|
ft_cpu_setup(blob, bd);
|
||||||
|
|
||||||
|
/* Fixup NOR mapping */
|
||||||
|
val[0] = 0; /* chip select number */
|
||||||
|
val[1] = 0; /* always 0 */
|
||||||
|
val[2] = gd->bd->bi_flashstart;
|
||||||
|
val[3] = gd->bd->bi_flashsize;
|
||||||
|
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
||||||
|
val, sizeof(val), 1);
|
||||||
|
if (rc)
|
||||||
|
printf("Unable to update property NOR mapping, err=%s\n",
|
||||||
|
fdt_strerror(rc));
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
||||||
|
|
|
@ -20,57 +20,9 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
#include <ppc_asm.tmpl>
|
||||||
|
#include <asm-ppc/mmu.h>
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
|
|
||||||
/* General */
|
|
||||||
#define TLB_VALID 0x00000200
|
|
||||||
#define _256M 0x10000000
|
|
||||||
|
|
||||||
/* Supported page sizes */
|
|
||||||
|
|
||||||
#define SZ_1K 0x00000000
|
|
||||||
#define SZ_4K 0x00000010
|
|
||||||
#define SZ_16K 0x00000020
|
|
||||||
#define SZ_64K 0x00000030
|
|
||||||
#define SZ_256K 0x00000040
|
|
||||||
#define SZ_1M 0x00000050
|
|
||||||
#define SZ_8M 0x00000060
|
|
||||||
#define SZ_16M 0x00000070
|
|
||||||
#define SZ_256M 0x00000090
|
|
||||||
|
|
||||||
/* Storage attributes */
|
|
||||||
#define SA_W 0x00000800 /* Write-through */
|
|
||||||
#define SA_I 0x00000400 /* Caching inhibited */
|
|
||||||
#define SA_M 0x00000200 /* Memory coherence */
|
|
||||||
#define SA_G 0x00000100 /* Guarded */
|
|
||||||
#define SA_E 0x00000080 /* Endian */
|
|
||||||
|
|
||||||
/* Access control */
|
|
||||||
#define AC_X 0x00000024 /* Execute */
|
|
||||||
#define AC_W 0x00000012 /* Write */
|
|
||||||
#define AC_R 0x00000009 /* Read */
|
|
||||||
|
|
||||||
/* Some handy macros */
|
|
||||||
|
|
||||||
#define EPN(e) ((e) & 0xfffffc00)
|
|
||||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
|
||||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
|
||||||
#define TLB2(a) ( (a)&0x00000fbf )
|
|
||||||
|
|
||||||
#define tlbtab_start\
|
|
||||||
mflr r1 ;\
|
|
||||||
bl 0f ;
|
|
||||||
|
|
||||||
#define tlbtab_end\
|
|
||||||
.long 0, 0, 0 ; \
|
|
||||||
0: mflr r0 ; \
|
|
||||||
mtlr r1 ; \
|
|
||||||
blr ;
|
|
||||||
|
|
||||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
|
||||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
|
||||||
|
|
||||||
|
|
||||||
/**************************************************************************
|
/**************************************************************************
|
||||||
* TLB TABLE
|
* TLB TABLE
|
||||||
*
|
*
|
||||||
|
|
|
@ -395,8 +395,8 @@
|
||||||
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||||
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||||
#define DDR0_26_TREF_MASK 0x00003FFF
|
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||||
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||||
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||||
|
|
||||||
#define DDR0_27 0x1B
|
#define DDR0_27 0x1B
|
||||||
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||||
|
|
|
@ -48,31 +48,31 @@ int board_early_init_f(void)
|
||||||
* Setup the GPIO pins
|
* Setup the GPIO pins
|
||||||
*-------------------------------------------------------------------*/
|
*-------------------------------------------------------------------*/
|
||||||
/* test-only: take GPIO init from pcs440ep ???? in config file */
|
/* test-only: take GPIO init from pcs440ep ???? in config file */
|
||||||
out32(GPIO0_OR, 0x00000000);
|
out_be32((u32 *) GPIO0_OR, 0x00000000);
|
||||||
out32(GPIO0_TCR, 0x0000000f);
|
out_be32((u32 *) GPIO0_TCR, 0x0000000f);
|
||||||
out32(GPIO0_OSRL, 0x50015400);
|
out_be32((u32 *) GPIO0_OSRL, 0x50015400);
|
||||||
out32(GPIO0_OSRH, 0x550050aa);
|
out_be32((u32 *) GPIO0_OSRH, 0x550050aa);
|
||||||
out32(GPIO0_TSRL, 0x50015400);
|
out_be32((u32 *) GPIO0_TSRL, 0x50015400);
|
||||||
out32(GPIO0_TSRH, 0x55005000);
|
out_be32((u32 *) GPIO0_TSRH, 0x55005000);
|
||||||
out32(GPIO0_ISR1L, 0x50000000);
|
out_be32((u32 *) GPIO0_ISR1L, 0x50000000);
|
||||||
out32(GPIO0_ISR1H, 0x00000000);
|
out_be32((u32 *) GPIO0_ISR1H, 0x00000000);
|
||||||
out32(GPIO0_ISR2L, 0x00000000);
|
out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
|
||||||
out32(GPIO0_ISR2H, 0x00000100);
|
out_be32((u32 *) GPIO0_ISR2H, 0x00000100);
|
||||||
out32(GPIO0_ISR3L, 0x00000000);
|
out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
|
||||||
out32(GPIO0_ISR3H, 0x00000000);
|
out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
|
||||||
|
|
||||||
out32(GPIO1_OR, 0x00000000);
|
out_be32((u32 *) GPIO1_OR, 0x00000000);
|
||||||
out32(GPIO1_TCR, 0xc2000000);
|
out_be32((u32 *) GPIO1_TCR, 0xc2000000);
|
||||||
out32(GPIO1_OSRL, 0x5c280000);
|
out_be32((u32 *) GPIO1_OSRL, 0x5c280000);
|
||||||
out32(GPIO1_OSRH, 0x00000000);
|
out_be32((u32 *) GPIO1_OSRH, 0x00000000);
|
||||||
out32(GPIO1_TSRL, 0x0c000000);
|
out_be32((u32 *) GPIO1_TSRL, 0x0c000000);
|
||||||
out32(GPIO1_TSRH, 0x00000000);
|
out_be32((u32 *) GPIO1_TSRH, 0x00000000);
|
||||||
out32(GPIO1_ISR1L, 0x00005550);
|
out_be32((u32 *) GPIO1_ISR1L, 0x00005550);
|
||||||
out32(GPIO1_ISR1H, 0x00000000);
|
out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
|
||||||
out32(GPIO1_ISR2L, 0x00050000);
|
out_be32((u32 *) GPIO1_ISR2L, 0x00050000);
|
||||||
out32(GPIO1_ISR2H, 0x00000000);
|
out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
|
||||||
out32(GPIO1_ISR3L, 0x01400000);
|
out_be32((u32 *) GPIO1_ISR3L, 0x01400000);
|
||||||
out32(GPIO1_ISR3H, 0x00000000);
|
out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
/*--------------------------------------------------------------------
|
||||||
* Setup the interrupt controller polarities, triggers, etc.
|
* Setup the interrupt controller polarities, triggers, etc.
|
||||||
|
@ -102,16 +102,16 @@ int board_early_init_f(void)
|
||||||
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||||
|
|
||||||
/* 50MHz tmrclk */
|
/* 50MHz tmrclk */
|
||||||
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
|
out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
|
||||||
|
|
||||||
/* clear write protects */
|
/* clear write protects */
|
||||||
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
|
out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
|
||||||
|
|
||||||
/* enable Ethernet */
|
/* enable Ethernet */
|
||||||
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;
|
out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
|
||||||
|
|
||||||
/* enable USB device */
|
/* enable USB device */
|
||||||
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;
|
out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
|
||||||
|
|
||||||
/* select Ethernet pins */
|
/* select Ethernet pins */
|
||||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
|
@ -24,6 +24,7 @@
|
||||||
* MA 02111-1307 USA
|
* MA 02111-1307 USA
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include "asm/io.h"
|
||||||
#include "lcd.h"
|
#include "lcd.h"
|
||||||
|
|
||||||
|
|
||||||
|
@ -45,11 +46,10 @@ void lcd_setup(int lcd, int config)
|
||||||
*/
|
*/
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
|
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD0_RST); /* set reset to low */
|
||||||
udelay(10); /* wait 10us */
|
udelay(10); /* wait 10us */
|
||||||
if (config == 1) {
|
if (config == 1)
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||||
} else {
|
else
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||||
}
|
|
||||||
udelay(10); /* wait 10us */
|
udelay(10); /* wait 10us */
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
|
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD0_RST); /* set reset to high */
|
||||||
} else {
|
} else {
|
||||||
|
@ -58,11 +58,10 @@ void lcd_setup(int lcd, int config)
|
||||||
*/
|
*/
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
|
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD1_RST); /* set reset to low */
|
||||||
udelay(10); /* wait 10us */
|
udelay(10); /* wait 10us */
|
||||||
if (config == 1) {
|
if (config == 1)
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD_ENDIAN); /* big-endian */
|
||||||
} else {
|
else
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_LCD_ENDIAN); /* little-endian */
|
||||||
}
|
|
||||||
udelay(10); /* wait 10us */
|
udelay(10); /* wait 10us */
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
|
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_LCD1_RST); /* set reset to high */
|
||||||
}
|
}
|
||||||
|
@ -104,12 +103,10 @@ void lcd_bmp(uchar *logo_bmp)
|
||||||
printf("Error: malloc in gunzip failed!\n");
|
printf("Error: malloc in gunzip failed!\n");
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0) {
|
if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE, (uchar *)logo_bmp, &len) != 0)
|
||||||
return;
|
return;
|
||||||
}
|
if (len == CFG_VIDEO_LOGO_MAX_SIZE)
|
||||||
if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
|
|
||||||
printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
|
printf("Image could be truncated (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Check for bmp mark 'BM'
|
* Check for bmp mark 'BM'
|
||||||
|
@ -152,9 +149,8 @@ void lcd_bmp(uchar *logo_bmp)
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
printf("LCD: Unknown bpp (%d) im image!\n", bpp);
|
printf("LCD: Unknown bpp (%d) im image!\n", bpp);
|
||||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
|
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
|
||||||
free(dst);
|
free(dst);
|
||||||
}
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
printf(" (%d*%d, %dbpp)\n", width, height, bpp);
|
printf(" (%d*%d, %dbpp)\n", width, height, bpp);
|
||||||
|
@ -212,9 +208,8 @@ void lcd_bmp(uchar *logo_bmp)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if ((dst != NULL) && (dst != (uchar *)logo_bmp)) {
|
if ((dst != NULL) && (dst != (uchar *)logo_bmp))
|
||||||
free(dst);
|
free(dst);
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
@ -229,10 +224,10 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
||||||
/*
|
/*
|
||||||
* Detect epson
|
* Detect epson
|
||||||
*/
|
*/
|
||||||
lcd_reg[0] = 0x00;
|
out_8(&lcd_reg[0], 0x00);
|
||||||
lcd_reg[1] = 0x00;
|
out_8(&lcd_reg[1], 0x00);
|
||||||
|
|
||||||
if (lcd_reg[0] == 0x1c) {
|
if (in_8(&lcd_reg[0]) == 0x1c) {
|
||||||
/*
|
/*
|
||||||
* Big epson detected
|
* Big epson detected
|
||||||
*/
|
*/
|
||||||
|
@ -241,7 +236,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
||||||
palette_value = 0x1e4;
|
palette_value = 0x1e4;
|
||||||
lcd_depth = 16;
|
lcd_depth = 16;
|
||||||
puts("LCD: S1D13806");
|
puts("LCD: S1D13806");
|
||||||
} else if (lcd_reg[1] == 0x1c) {
|
} else if (in_8(&lcd_reg[1]) == 0x1c) {
|
||||||
/*
|
/*
|
||||||
* Big epson detected (with register swap bug)
|
* Big epson detected (with register swap bug)
|
||||||
*/
|
*/
|
||||||
|
@ -250,7 +245,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
||||||
palette_value = 0x1e5;
|
palette_value = 0x1e5;
|
||||||
lcd_depth = 16;
|
lcd_depth = 16;
|
||||||
puts("LCD: S1D13806S");
|
puts("LCD: S1D13806S");
|
||||||
} else if (lcd_reg[0] == 0x18) {
|
} else if (in_8(&lcd_reg[0]) == 0x18) {
|
||||||
/*
|
/*
|
||||||
* Small epson detected (704)
|
* Small epson detected (704)
|
||||||
*/
|
*/
|
||||||
|
@ -259,7 +254,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
||||||
palette_value = 0x17;
|
palette_value = 0x17;
|
||||||
lcd_depth = 8;
|
lcd_depth = 8;
|
||||||
puts("LCD: S1D13704");
|
puts("LCD: S1D13704");
|
||||||
} else if (lcd_reg[0x10000] == 0x24) {
|
} else if (in_8(&lcd_reg[0x10000]) == 0x24) {
|
||||||
/*
|
/*
|
||||||
* Small epson detected (705)
|
* Small epson detected (705)
|
||||||
*/
|
*/
|
||||||
|
@ -277,7 +272,7 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
|
||||||
/*
|
/*
|
||||||
* Setup lcd controller regs
|
* Setup lcd controller regs
|
||||||
*/
|
*/
|
||||||
for (i = 0; i<reg_count; i++) {
|
for (i = 0; i < reg_count; i++) {
|
||||||
s1dReg = regs[i].Index;
|
s1dReg = regs[i].Index;
|
||||||
if (reg_byte_swap) {
|
if (reg_byte_swap) {
|
||||||
if ((s1dReg & 0x0001) == 0)
|
if ((s1dReg & 0x0001) == 0)
|
||||||
|
|
|
@ -1,152 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2002
|
|
||||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
|
|
||||||
|
|
||||||
extern void lxt971_no_sleep(void);
|
|
||||||
|
|
||||||
|
|
||||||
long int fixed_sdram( void );
|
|
||||||
|
|
||||||
int board_early_init_f (void)
|
|
||||||
{
|
|
||||||
uint reg;
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup the external bus controller/chip selects
|
|
||||||
*-------------------------------------------------------------------*/
|
|
||||||
mtdcr( ebccfga, xbcfg );
|
|
||||||
reg = mfdcr( ebccfgd );
|
|
||||||
mtdcr( ebccfgd, reg | 0x04000000 ); /* Set ATC */
|
|
||||||
|
|
||||||
mtebc( pb0ap, 0x92015480 ); /* FLASH/SRAM */
|
|
||||||
mtebc( pb0cr, 0xFF87A000 ); /* BAS=0xff8 8MB R/W 16-bit */
|
|
||||||
/* test-only: other regs still missing... */
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup the interrupt controller polarities, triggers, etc.
|
|
||||||
*-------------------------------------------------------------------*/
|
|
||||||
mtdcr( uic0sr, 0xffffffff ); /* clear all */
|
|
||||||
mtdcr( uic0er, 0x00000000 ); /* disable all */
|
|
||||||
mtdcr( uic0cr, 0x00000009 ); /* SMI & UIC1 crit are critical */
|
|
||||||
mtdcr( uic0pr, 0xfffffe13 ); /* per ref-board manual */
|
|
||||||
mtdcr( uic0tr, 0x01c00008 ); /* per ref-board manual */
|
|
||||||
mtdcr( uic0vr, 0x00000001 ); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr( uic0sr, 0xffffffff ); /* clear all */
|
|
||||||
|
|
||||||
mtdcr( uic1sr, 0xffffffff ); /* clear all */
|
|
||||||
mtdcr( uic1er, 0x00000000 ); /* disable all */
|
|
||||||
mtdcr( uic1cr, 0x00000000 ); /* all non-critical */
|
|
||||||
mtdcr( uic1pr, 0xffffe0ff ); /* per ref-board manual */
|
|
||||||
mtdcr( uic1tr, 0x00ffc000 ); /* per ref-board manual */
|
|
||||||
mtdcr( uic1vr, 0x00000001 ); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr( uic1sr, 0xffffffff ); /* clear all */
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
int checkboard (void)
|
|
||||||
{
|
|
||||||
sys_info_t sysinfo;
|
|
||||||
get_sys_info(&sysinfo);
|
|
||||||
|
|
||||||
printf("Board: esd CPCI-440\n");
|
|
||||||
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz/1000000);
|
|
||||||
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000);
|
|
||||||
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000);
|
|
||||||
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000);
|
|
||||||
printf("\tEBC: %lu MHz\n", sysinfo.freqEBC/1000000);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable sleep mode in LXT971
|
|
||||||
*/
|
|
||||||
lxt971_no_sleep();
|
|
||||||
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
long int initdram (int board_type)
|
|
||||||
{
|
|
||||||
long dram_size = 0;
|
|
||||||
|
|
||||||
dram_size = fixed_sdram();
|
|
||||||
return dram_size;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*************************************************************************
|
|
||||||
* fixed sdram init -- doesn't use serial presence detect.
|
|
||||||
*
|
|
||||||
* Assumes: 64 MB, non-ECC, non-registered
|
|
||||||
* PLB @ 133 MHz
|
|
||||||
*
|
|
||||||
************************************************************************/
|
|
||||||
long int fixed_sdram( void )
|
|
||||||
{
|
|
||||||
uint reg;
|
|
||||||
|
|
||||||
#if 1 /* test-only */
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup some default
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
mtsdram( mem_uabba, 0x00000000 ); /* ubba=0 (default) */
|
|
||||||
mtsdram( mem_slio, 0x00000000 ); /* rdre=0 wrre=0 rarw=0 */
|
|
||||||
mtsdram( mem_devopt,0x00000000 ); /* dll=0 ds=0 (normal) */
|
|
||||||
mtsdram( mem_wddctr,0x40000000 ); /* wrcp=0 dcd=0 */
|
|
||||||
mtsdram( mem_clktr, 0x40000000 ); /* clkp=1 (90 deg wr) dcdt=0 */
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup for board-specific specific mem
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
/*
|
|
||||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
|
||||||
*/
|
|
||||||
mtsdram( mem_b0cr, 0x00082001 );/* SDBA=0x000, 64MB, Mode 2, enabled*/
|
|
||||||
mtsdram( mem_tr0, 0x410a4012 );/* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
|
|
||||||
/* RA=10 RD=3 */
|
|
||||||
mtsdram( mem_tr1, 0x8080082f );/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
|
|
||||||
mtsdram( mem_rtr, 0x08200000 );/* Rate 15.625 ns @ 133 MHz PLB */
|
|
||||||
mtsdram( mem_cfg1, 0x00000000 );/* Self-refresh exit, disable PM */
|
|
||||||
udelay( 400 ); /* Delay 200 usecs (min) */
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Enable the controller, then wait for DCEN to complete
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
mtsdram( mem_cfg0, 0x86000000 );/* DCEN=1, PMUD=1, 64-bit */
|
|
||||||
for(;;)
|
|
||||||
{
|
|
||||||
mfsdram( mem_mcsts, reg );
|
|
||||||
if( reg & 0x80000000 )
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return( 64 * 1024 * 1024 ); /* 64 MB */
|
|
||||||
#else
|
|
||||||
return( 32 * 1024 * 1024 ); /* 64 MB */
|
|
||||||
#endif
|
|
||||||
}
|
|
|
@ -1,94 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <config.h>
|
|
||||||
|
|
||||||
/* General */
|
|
||||||
#define TLB_VALID 0x00000200
|
|
||||||
|
|
||||||
/* Supported page sizes */
|
|
||||||
|
|
||||||
#define SZ_1K 0x00000000
|
|
||||||
#define SZ_4K 0x00000010
|
|
||||||
#define SZ_16K 0x00000020
|
|
||||||
#define SZ_64K 0x00000030
|
|
||||||
#define SZ_256K 0x00000040
|
|
||||||
#define SZ_1M 0x00000050
|
|
||||||
#define SZ_16M 0x00000070
|
|
||||||
#define SZ_256M 0x00000090
|
|
||||||
|
|
||||||
/* Storage attributes */
|
|
||||||
#define SA_W 0x00000800 /* Write-through */
|
|
||||||
#define SA_I 0x00000400 /* Caching inhibited */
|
|
||||||
#define SA_M 0x00000200 /* Memory coherence */
|
|
||||||
#define SA_G 0x00000100 /* Guarded */
|
|
||||||
#define SA_E 0x00000080 /* Endian */
|
|
||||||
|
|
||||||
/* Access control */
|
|
||||||
#define AC_X 0x00000024 /* Execute */
|
|
||||||
#define AC_W 0x00000012 /* Write */
|
|
||||||
#define AC_R 0x00000009 /* Read */
|
|
||||||
|
|
||||||
/* Some handy macros */
|
|
||||||
|
|
||||||
#define EPN(e) ((e) & 0xfffffc00)
|
|
||||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
|
||||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
|
||||||
#define TLB2(a) ( (a)&0x00000fbf )
|
|
||||||
|
|
||||||
#define tlbtab_start\
|
|
||||||
mflr r1 ;\
|
|
||||||
bl 0f ;
|
|
||||||
|
|
||||||
#define tlbtab_end\
|
|
||||||
.long 0, 0, 0 ; \
|
|
||||||
0: mflr r0 ; \
|
|
||||||
mtlr r1 ; \
|
|
||||||
blr ;
|
|
||||||
|
|
||||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
|
||||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
|
||||||
|
|
||||||
|
|
||||||
/**************************************************************************
|
|
||||||
* TLB TABLE
|
|
||||||
*
|
|
||||||
* This table is used by the cpu boot code to setup the initial tlb
|
|
||||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
|
||||||
* this table lets each board set things up however they like.
|
|
||||||
*
|
|
||||||
* Pointer to the table is returned in r1
|
|
||||||
*
|
|
||||||
*************************************************************************/
|
|
||||||
|
|
||||||
.section .bootpg,"ax"
|
|
||||||
.globl tlbtab
|
|
||||||
|
|
||||||
tlbtab:
|
|
||||||
tlbtab_start
|
|
||||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
|
||||||
tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
|
||||||
tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
|
|
||||||
tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
|
|
||||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X )
|
|
||||||
tlbtab_end
|
|
|
@ -1,755 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2002
|
|
||||||
* Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
|
|
||||||
#undef DEBUG_FLASH
|
|
||||||
/*
|
|
||||||
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
|
|
||||||
* The width of the port and the width of the chips are determined at initialization.
|
|
||||||
* These widths are used to calculate the address for access CFI data structures.
|
|
||||||
* It has been tested on an Intel Strataflash implementation.
|
|
||||||
*
|
|
||||||
* References
|
|
||||||
* JEDEC Standard JESD68 - Common Flash Interface (CFI)
|
|
||||||
* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
|
|
||||||
* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
|
|
||||||
* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
|
|
||||||
*
|
|
||||||
* TODO
|
|
||||||
* Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
|
|
||||||
* Add support for other command sets Use the PRI and ALT to determine command set
|
|
||||||
* Verify erase and program timeouts.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define FLASH_CMD_CFI 0x98
|
|
||||||
#define FLASH_CMD_READ_ID 0x90
|
|
||||||
#define FLASH_CMD_RESET 0xff
|
|
||||||
#define FLASH_CMD_BLOCK_ERASE 0x20
|
|
||||||
#define FLASH_CMD_ERASE_CONFIRM 0xD0
|
|
||||||
#define FLASH_CMD_WRITE 0x40
|
|
||||||
#define FLASH_CMD_PROTECT 0x60
|
|
||||||
#define FLASH_CMD_PROTECT_SET 0x01
|
|
||||||
#define FLASH_CMD_PROTECT_CLEAR 0xD0
|
|
||||||
#define FLASH_CMD_CLEAR_STATUS 0x50
|
|
||||||
#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
|
|
||||||
#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
|
|
||||||
|
|
||||||
#define FLASH_STATUS_DONE 0x80
|
|
||||||
#define FLASH_STATUS_ESS 0x40
|
|
||||||
#define FLASH_STATUS_ECLBS 0x20
|
|
||||||
#define FLASH_STATUS_PSLBS 0x10
|
|
||||||
#define FLASH_STATUS_VPENS 0x08
|
|
||||||
#define FLASH_STATUS_PSS 0x04
|
|
||||||
#define FLASH_STATUS_DPS 0x02
|
|
||||||
#define FLASH_STATUS_R 0x01
|
|
||||||
#define FLASH_STATUS_PROTECT 0x01
|
|
||||||
|
|
||||||
#define FLASH_OFFSET_CFI 0x55
|
|
||||||
#define FLASH_OFFSET_CFI_RESP 0x10
|
|
||||||
#define FLASH_OFFSET_WTOUT 0x1F
|
|
||||||
#define FLASH_OFFSET_WBTOUT 0x20
|
|
||||||
#define FLASH_OFFSET_ETOUT 0x21
|
|
||||||
#define FLASH_OFFSET_CETOUT 0x22
|
|
||||||
#define FLASH_OFFSET_WMAX_TOUT 0x23
|
|
||||||
#define FLASH_OFFSET_WBMAX_TOUT 0x24
|
|
||||||
#define FLASH_OFFSET_EMAX_TOUT 0x25
|
|
||||||
#define FLASH_OFFSET_CEMAX_TOUT 0x26
|
|
||||||
#define FLASH_OFFSET_SIZE 0x27
|
|
||||||
#define FLASH_OFFSET_INTERFACE 0x28
|
|
||||||
#define FLASH_OFFSET_BUFFER_SIZE 0x2A
|
|
||||||
#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
|
|
||||||
#define FLASH_OFFSET_ERASE_REGIONS 0x2D
|
|
||||||
#define FLASH_OFFSET_PROTECT 0x02
|
|
||||||
#define FLASH_OFFSET_USER_PROTECTION 0x85
|
|
||||||
#define FLASH_OFFSET_INTEL_PROTECTION 0x81
|
|
||||||
|
|
||||||
|
|
||||||
#define FLASH_MAN_CFI 0x01000000
|
|
||||||
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
unsigned char c;
|
|
||||||
unsigned short w;
|
|
||||||
unsigned long l;
|
|
||||||
} cfiword_t;
|
|
||||||
|
|
||||||
typedef union {
|
|
||||||
unsigned char * cp;
|
|
||||||
unsigned short *wp;
|
|
||||||
unsigned long *lp;
|
|
||||||
} cfiptr_t;
|
|
||||||
|
|
||||||
#define NUM_ERASE_REGIONS 4
|
|
||||||
|
|
||||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Functions
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
|
|
||||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
|
|
||||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
|
||||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
|
||||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
|
|
||||||
static int flash_detect_cfi(flash_info_t * info);
|
|
||||||
static ulong flash_get_size (ulong base, int banknum);
|
|
||||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
|
|
||||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
|
|
||||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
|
||||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
|
|
||||||
#endif
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* create an address based on the offset and the port width
|
|
||||||
*/
|
|
||||||
inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
|
|
||||||
{
|
|
||||||
return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* read a character at a port width address
|
|
||||||
*/
|
|
||||||
inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
|
|
||||||
{
|
|
||||||
uchar *cp;
|
|
||||||
cp = flash_make_addr(info, 0, offset);
|
|
||||||
return (cp[info->portwidth - 1]);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* read a short word by swapping for ppc format.
|
|
||||||
*/
|
|
||||||
ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
|
|
||||||
{
|
|
||||||
uchar * addr;
|
|
||||||
|
|
||||||
addr = flash_make_addr(info, sect, offset);
|
|
||||||
return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* read a long word by picking the least significant byte of each maiximum
|
|
||||||
* port size word. Swap for ppc format.
|
|
||||||
*/
|
|
||||||
ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
|
|
||||||
{
|
|
||||||
uchar * addr;
|
|
||||||
|
|
||||||
addr = flash_make_addr(info, sect, offset);
|
|
||||||
return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
|
|
||||||
(addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
unsigned long flash_init (void)
|
|
||||||
{
|
|
||||||
unsigned long size;
|
|
||||||
int i;
|
|
||||||
unsigned long address;
|
|
||||||
|
|
||||||
|
|
||||||
/* The flash is positioned back to back, with the demultiplexing of the chip
|
|
||||||
* based on the A24 address line.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
address = CFG_FLASH_BASE;
|
|
||||||
size = 0;
|
|
||||||
|
|
||||||
/* Init: no FLASHes known */
|
|
||||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
|
|
||||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
|
||||||
size += flash_info[i].size = flash_get_size(address, i);
|
|
||||||
address += CFG_FLASH_INCREMENT;
|
|
||||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
|
||||||
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
|
|
||||||
flash_info[0].size, flash_info[i].size<<20);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#if 0 /* test-only */
|
|
||||||
/* Monitor protection ON by default */
|
|
||||||
#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
|
|
||||||
for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
|
|
||||||
(void)flash_real_protect(&flash_info[0], i, 1);
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return (size);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
|
||||||
{
|
|
||||||
int rcode = 0;
|
|
||||||
int prot;
|
|
||||||
int sect;
|
|
||||||
|
|
||||||
if( info->flash_id != FLASH_MAN_CFI) {
|
|
||||||
printf ("Can't erase unknown flash type - aborted\n");
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
if ((s_first < 0) || (s_first > s_last)) {
|
|
||||||
printf ("- no sectors to erase\n");
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
prot = 0;
|
|
||||||
for (sect=s_first; sect<=s_last; ++sect) {
|
|
||||||
if (info->protect[sect]) {
|
|
||||||
prot++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (prot) {
|
|
||||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
|
||||||
prot);
|
|
||||||
} else {
|
|
||||||
printf ("\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
for (sect = s_first; sect<=s_last; sect++) {
|
|
||||||
if (info->protect[sect] == 0) { /* not protected */
|
|
||||||
flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
|
|
||||||
flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
|
|
||||||
flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
|
|
||||||
|
|
||||||
if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
|
|
||||||
rcode = 1;
|
|
||||||
} else
|
|
||||||
printf(".");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
printf (" done\n");
|
|
||||||
return rcode;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
void flash_print_info (flash_info_t *info)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (info->flash_id != FLASH_MAN_CFI) {
|
|
||||||
printf ("missing or unknown FLASH type\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
printf("CFI conformant FLASH (%d x %d)",
|
|
||||||
(info->portwidth << 3 ), (info->chipwidth << 3 ));
|
|
||||||
printf (" Size: %ld MB in %d Sectors\n",
|
|
||||||
info->size >> 20, info->sector_count);
|
|
||||||
printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
|
|
||||||
info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
|
|
||||||
|
|
||||||
printf (" Sector Start Addresses:");
|
|
||||||
for (i=0; i<info->sector_count; ++i) {
|
|
||||||
if ((i % 5) == 0)
|
|
||||||
printf ("\n");
|
|
||||||
printf (" %08lX%5s",
|
|
||||||
info->start[i],
|
|
||||||
info->protect[i] ? " (RO)" : " "
|
|
||||||
);
|
|
||||||
}
|
|
||||||
printf ("\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Copy memory to flash, returns:
|
|
||||||
* 0 - OK
|
|
||||||
* 1 - write timeout
|
|
||||||
* 2 - Flash not erased
|
|
||||||
*/
|
|
||||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
|
||||||
{
|
|
||||||
ulong wp;
|
|
||||||
ulong cp;
|
|
||||||
int aln;
|
|
||||||
cfiword_t cword;
|
|
||||||
int i, rc;
|
|
||||||
|
|
||||||
/* get lower aligned address */
|
|
||||||
wp = (addr & ~(info->portwidth - 1));
|
|
||||||
|
|
||||||
/* handle unaligned start */
|
|
||||||
if((aln = addr - wp) != 0) {
|
|
||||||
cword.l = 0;
|
|
||||||
cp = wp;
|
|
||||||
for(i=0;i<aln; ++i, ++cp)
|
|
||||||
flash_add_byte(info, &cword, (*(uchar *)cp));
|
|
||||||
|
|
||||||
for(; (i< info->portwidth) && (cnt > 0) ; i++) {
|
|
||||||
flash_add_byte(info, &cword, *src++);
|
|
||||||
cnt--;
|
|
||||||
cp++;
|
|
||||||
}
|
|
||||||
for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
|
|
||||||
flash_add_byte(info, &cword, (*(uchar *)cp));
|
|
||||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
|
||||||
return rc;
|
|
||||||
wp = cp;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
|
||||||
while(cnt >= info->portwidth) {
|
|
||||||
i = info->buffer_size > cnt? cnt: info->buffer_size;
|
|
||||||
if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
|
|
||||||
return rc;
|
|
||||||
wp += i;
|
|
||||||
src += i;
|
|
||||||
cnt -=i;
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
/* handle the aligned part */
|
|
||||||
while(cnt >= info->portwidth) {
|
|
||||||
cword.l = 0;
|
|
||||||
for(i = 0; i < info->portwidth; i++) {
|
|
||||||
flash_add_byte(info, &cword, *src++);
|
|
||||||
}
|
|
||||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
|
||||||
return rc;
|
|
||||||
wp += info->portwidth;
|
|
||||||
cnt -= info->portwidth;
|
|
||||||
}
|
|
||||||
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
|
|
||||||
if (cnt == 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned tail bytes
|
|
||||||
*/
|
|
||||||
cword.l = 0;
|
|
||||||
for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
|
|
||||||
flash_add_byte(info, &cword, *src++);
|
|
||||||
--cnt;
|
|
||||||
}
|
|
||||||
for (; i<info->portwidth; ++i, ++cp) {
|
|
||||||
flash_add_byte(info, & cword, (*(uchar *)cp));
|
|
||||||
}
|
|
||||||
|
|
||||||
return flash_write_cfiword(info, wp, cword);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
int flash_real_protect(flash_info_t *info, long sector, int prot)
|
|
||||||
{
|
|
||||||
int retcode = 0;
|
|
||||||
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
|
|
||||||
if(prot)
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
|
|
||||||
else
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
|
|
||||||
|
|
||||||
if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
|
|
||||||
prot?"protect":"unprotect")) == 0) {
|
|
||||||
|
|
||||||
info->protect[sector] = prot;
|
|
||||||
/* Intel's unprotect unprotects all locking */
|
|
||||||
if(prot == 0) {
|
|
||||||
int i;
|
|
||||||
for(i = 0 ; i<info->sector_count; i++) {
|
|
||||||
if(info->protect[i])
|
|
||||||
flash_real_protect(info, i, 1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return retcode;
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* wait for XSR.7 to be set. Time out with an error if it does not.
|
|
||||||
* This routine does not set the flash to read-array mode.
|
|
||||||
*/
|
|
||||||
static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
|
|
||||||
{
|
|
||||||
ulong start;
|
|
||||||
|
|
||||||
/* Wait for command completion */
|
|
||||||
start = get_timer (0);
|
|
||||||
while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
|
|
||||||
if (get_timer(start) > info->erase_blk_tout) {
|
|
||||||
printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
|
||||||
return ERR_TIMOUT;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return ERR_OK;
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
|
|
||||||
* This routine sets the flash to read-array mode.
|
|
||||||
*/
|
|
||||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
|
|
||||||
{
|
|
||||||
int retcode;
|
|
||||||
retcode = flash_status_check(info, sector, tout, prompt);
|
|
||||||
if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
|
|
||||||
retcode = ERR_INVAL;
|
|
||||||
printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
|
|
||||||
if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
|
|
||||||
printf("Command Sequence Error.\n");
|
|
||||||
} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
|
|
||||||
printf("Block Erase Error.\n");
|
|
||||||
retcode = ERR_NOT_ERASED;
|
|
||||||
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
|
|
||||||
printf("Locking Error\n");
|
|
||||||
}
|
|
||||||
if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
|
|
||||||
printf("Block locked.\n");
|
|
||||||
retcode = ERR_PROTECTED;
|
|
||||||
}
|
|
||||||
if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
|
|
||||||
printf("Vpp Low Error.\n");
|
|
||||||
}
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
|
||||||
return retcode;
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
|
|
||||||
{
|
|
||||||
switch(info->portwidth) {
|
|
||||||
case FLASH_CFI_8BIT:
|
|
||||||
cword->c = c;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_16BIT:
|
|
||||||
cword->w = (cword->w << 8) | c;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_32BIT:
|
|
||||||
cword->l = (cword->l << 8) | c;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* make a proper sized command based on the port and chip widths
|
|
||||||
*/
|
|
||||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
uchar *cp = (uchar *)cmdbuf;
|
|
||||||
for(i=0; i< info->portwidth; i++)
|
|
||||||
*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Write a proper sized command to the correct address
|
|
||||||
*/
|
|
||||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
|
||||||
{
|
|
||||||
|
|
||||||
volatile cfiptr_t addr;
|
|
||||||
cfiword_t cword;
|
|
||||||
addr.cp = flash_make_addr(info, sect, offset);
|
|
||||||
flash_make_cmd(info, cmd, &cword);
|
|
||||||
switch(info->portwidth) {
|
|
||||||
case FLASH_CFI_8BIT:
|
|
||||||
*addr.cp = cword.c;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_16BIT:
|
|
||||||
*addr.wp = cword.w;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_32BIT:
|
|
||||||
*addr.lp = cword.l;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
|
||||||
{
|
|
||||||
cfiptr_t cptr;
|
|
||||||
cfiword_t cword;
|
|
||||||
int retval;
|
|
||||||
cptr.cp = flash_make_addr(info, sect, offset);
|
|
||||||
flash_make_cmd(info, cmd, &cword);
|
|
||||||
switch(info->portwidth) {
|
|
||||||
case FLASH_CFI_8BIT:
|
|
||||||
retval = (cptr.cp[0] == cword.c);
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_16BIT:
|
|
||||||
retval = (cptr.wp[0] == cword.w);
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_32BIT:
|
|
||||||
retval = (cptr.lp[0] == cword.l);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
retval = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return retval;
|
|
||||||
}
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
|
||||||
{
|
|
||||||
cfiptr_t cptr;
|
|
||||||
cfiword_t cword;
|
|
||||||
int retval;
|
|
||||||
cptr.cp = flash_make_addr(info, sect, offset);
|
|
||||||
flash_make_cmd(info, cmd, &cword);
|
|
||||||
switch(info->portwidth) {
|
|
||||||
case FLASH_CFI_8BIT:
|
|
||||||
retval = ((cptr.cp[0] & cword.c) == cword.c);
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_16BIT:
|
|
||||||
retval = ((cptr.wp[0] & cword.w) == cword.w);
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_32BIT:
|
|
||||||
retval = ((cptr.lp[0] & cword.l) == cword.l);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
retval = 0;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return retval;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* detect if flash is compatible with the Common Flash Interface (CFI)
|
|
||||||
* http://www.jedec.org/download/search/jesd68.pdf
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
static int flash_detect_cfi(flash_info_t * info)
|
|
||||||
{
|
|
||||||
|
|
||||||
for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
|
|
||||||
info->portwidth <<= 1) {
|
|
||||||
for(info->chipwidth =FLASH_CFI_BY8;
|
|
||||||
info->chipwidth <= info->portwidth;
|
|
||||||
info->chipwidth <<= 1) {
|
|
||||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
|
||||||
flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
|
|
||||||
if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
|
|
||||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
|
|
||||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
/*
|
|
||||||
* The following code cannot be run from FLASH!
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
static ulong flash_get_size (ulong base, int banknum)
|
|
||||||
{
|
|
||||||
flash_info_t * info = &flash_info[banknum];
|
|
||||||
int i, j;
|
|
||||||
int sect_cnt;
|
|
||||||
unsigned long sector;
|
|
||||||
unsigned long tmp;
|
|
||||||
int size_ratio;
|
|
||||||
uchar num_erase_regions;
|
|
||||||
int erase_region_size;
|
|
||||||
int erase_region_count;
|
|
||||||
|
|
||||||
info->start[0] = base;
|
|
||||||
|
|
||||||
if(flash_detect_cfi(info)){
|
|
||||||
#ifdef DEBUG_FLASH
|
|
||||||
printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
|
|
||||||
#endif
|
|
||||||
size_ratio = info->portwidth / info->chipwidth;
|
|
||||||
num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
|
|
||||||
#ifdef DEBUG_FLASH
|
|
||||||
printf("found %d erase regions\n", num_erase_regions);
|
|
||||||
#endif
|
|
||||||
sect_cnt = 0;
|
|
||||||
sector = base;
|
|
||||||
for(i = 0 ; i < num_erase_regions; i++) {
|
|
||||||
if(i > NUM_ERASE_REGIONS) {
|
|
||||||
printf("%d erase regions found, only %d used\n",
|
|
||||||
num_erase_regions, NUM_ERASE_REGIONS);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
|
|
||||||
erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
|
|
||||||
tmp >>= 16;
|
|
||||||
erase_region_count = (tmp & 0xffff) +1;
|
|
||||||
for(j = 0; j< erase_region_count; j++) {
|
|
||||||
info->start[sect_cnt] = sector;
|
|
||||||
sector += (erase_region_size * size_ratio);
|
|
||||||
info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
|
|
||||||
sect_cnt++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
info->sector_count = sect_cnt;
|
|
||||||
/* multiply the size by the number of chips */
|
|
||||||
info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
|
|
||||||
info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
|
|
||||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
|
|
||||||
info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
|
|
||||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
|
|
||||||
info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
|
|
||||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
|
|
||||||
info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
|
|
||||||
info->flash_id = FLASH_MAN_CFI;
|
|
||||||
}
|
|
||||||
|
|
||||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
|
||||||
return(info->size);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
|
|
||||||
{
|
|
||||||
|
|
||||||
cfiptr_t ctladdr;
|
|
||||||
cfiptr_t cptr;
|
|
||||||
int flag;
|
|
||||||
|
|
||||||
ctladdr.cp = flash_make_addr(info, 0, 0);
|
|
||||||
cptr.cp = (uchar *)dest;
|
|
||||||
|
|
||||||
|
|
||||||
/* Check if Flash is (sufficiently) erased */
|
|
||||||
switch(info->portwidth) {
|
|
||||||
case FLASH_CFI_8BIT:
|
|
||||||
flag = ((cptr.cp[0] & cword.c) == cword.c);
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_16BIT:
|
|
||||||
flag = ((cptr.wp[0] & cword.w) == cword.w);
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_32BIT:
|
|
||||||
flag = ((cptr.lp[0] & cword.l) == cword.l);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return 2;
|
|
||||||
}
|
|
||||||
if(!flag)
|
|
||||||
return 2;
|
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */
|
|
||||||
flag = disable_interrupts();
|
|
||||||
|
|
||||||
flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
|
|
||||||
flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
|
|
||||||
|
|
||||||
switch(info->portwidth) {
|
|
||||||
case FLASH_CFI_8BIT:
|
|
||||||
cptr.cp[0] = cword.c;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_16BIT:
|
|
||||||
cptr.wp[0] = cword.w;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_32BIT:
|
|
||||||
cptr.lp[0] = cword.l;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */
|
|
||||||
if(flag)
|
|
||||||
enable_interrupts();
|
|
||||||
|
|
||||||
return flash_full_status_check(info, 0, info->write_tout, "write");
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CFG_FLASH_USE_BUFFER_WRITE
|
|
||||||
|
|
||||||
/* loop through the sectors from the highest address
|
|
||||||
* when the passed address is greater or equal to the sector address
|
|
||||||
* we have a match
|
|
||||||
*/
|
|
||||||
static int find_sector(flash_info_t *info, ulong addr)
|
|
||||||
{
|
|
||||||
int sector;
|
|
||||||
for(sector = info->sector_count - 1; sector >= 0; sector--) {
|
|
||||||
if(addr >= info->start[sector])
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
return sector;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
|
|
||||||
{
|
|
||||||
|
|
||||||
int sector;
|
|
||||||
int cnt;
|
|
||||||
int retcode;
|
|
||||||
volatile cfiptr_t src;
|
|
||||||
volatile cfiptr_t dst;
|
|
||||||
|
|
||||||
src.cp = cp;
|
|
||||||
dst.cp = (uchar *)dest;
|
|
||||||
sector = find_sector(info, dest);
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
|
|
||||||
if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
|
|
||||||
"write to buffer")) == ERR_OK) {
|
|
||||||
switch(info->portwidth) {
|
|
||||||
case FLASH_CFI_8BIT:
|
|
||||||
cnt = len;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_16BIT:
|
|
||||||
cnt = len >> 1;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_32BIT:
|
|
||||||
cnt = len >> 2;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return ERR_INVAL;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
flash_write_cmd(info, sector, 0, (uchar)cnt-1);
|
|
||||||
while(cnt-- > 0) {
|
|
||||||
switch(info->portwidth) {
|
|
||||||
case FLASH_CFI_8BIT:
|
|
||||||
*dst.cp++ = *src.cp++;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_16BIT:
|
|
||||||
*dst.wp++ = *src.wp++;
|
|
||||||
break;
|
|
||||||
case FLASH_CFI_32BIT:
|
|
||||||
*dst.lp++ = *src.lp++;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
return ERR_INVAL;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
|
|
||||||
retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
|
|
||||||
"buffer write");
|
|
||||||
}
|
|
||||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
|
||||||
return retcode;
|
|
||||||
}
|
|
||||||
#endif /* CFG_USE_FLASH_BUFFER_WRITE */
|
|
|
@ -109,8 +109,8 @@ int misc_init_f (void)
|
||||||
|
|
||||||
int misc_init_r (void)
|
int misc_init_r (void)
|
||||||
{
|
{
|
||||||
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
||||||
volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
||||||
unsigned char *dst;
|
unsigned char *dst;
|
||||||
ulong len = sizeof(fpgadata);
|
ulong len = sizeof(fpgadata);
|
||||||
int status;
|
int status;
|
||||||
|
@ -184,16 +184,28 @@ int misc_init_r (void)
|
||||||
/*
|
/*
|
||||||
* Reset external DUARTs
|
* Reset external DUARTs
|
||||||
*/
|
*/
|
||||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
||||||
udelay(10); /* wait 10us */
|
udelay(10); /* wait 10us */
|
||||||
out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||||
udelay(1000); /* wait 1ms */
|
udelay(1000); /* wait 1ms */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set NAND-FLASH GPIO signals to default
|
||||||
|
*/
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup EEPROM write protection
|
||||||
|
*/
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||||
|
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Enable interrupts in exar duart mcr[3]
|
* Enable interrupts in exar duart mcr[3]
|
||||||
*/
|
*/
|
||||||
*duart0_mcr = 0x08;
|
out_8(duart0_mcr, 0x08);
|
||||||
*duart1_mcr = 0x08;
|
out_8(duart1_mcr, 0x08);
|
||||||
|
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
@ -259,3 +271,74 @@ void reset_phy(void)
|
||||||
lxt971_no_sleep();
|
lxt971_no_sleep();
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(CFG_EEPROM_WREN)
|
||||||
|
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||||
|
* <state> -1: deliver current state
|
||||||
|
* 0: disable write
|
||||||
|
* 1: enable write
|
||||||
|
* Returns: -1: wrong device address
|
||||||
|
* 0: dis-/en- able done
|
||||||
|
* 0/1: current state if <state> was -1.
|
||||||
|
*/
|
||||||
|
int eeprom_write_enable (unsigned dev_addr, int state)
|
||||||
|
{
|
||||||
|
if (CFG_I2C_EEPROM_ADDR != dev_addr) {
|
||||||
|
return -1;
|
||||||
|
} else {
|
||||||
|
switch (state) {
|
||||||
|
case 1:
|
||||||
|
/* Enable write access, clear bit GPIO0. */
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
|
||||||
|
state = 0;
|
||||||
|
break;
|
||||||
|
case 0:
|
||||||
|
/* Disable write access, set bit GPIO0. */
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||||
|
state = 0;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
/* Read current status back. */
|
||||||
|
state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return state;
|
||||||
|
}
|
||||||
|
|
||||||
|
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
int query = argc == 1;
|
||||||
|
int state = 0;
|
||||||
|
|
||||||
|
if (query) {
|
||||||
|
/* Query write access state. */
|
||||||
|
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
|
||||||
|
if (state < 0) {
|
||||||
|
puts ("Query of write access state failed.\n");
|
||||||
|
} else {
|
||||||
|
printf ("Write access for device 0x%0x is %sabled.\n",
|
||||||
|
CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||||
|
state = 0;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
if ('0' == argv[1][0]) {
|
||||||
|
/* Disable write access. */
|
||||||
|
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
|
||||||
|
} else {
|
||||||
|
/* Enable write access. */
|
||||||
|
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
|
||||||
|
}
|
||||||
|
if (state < 0) {
|
||||||
|
puts ("Setup of write access state failed.\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return state;
|
||||||
|
}
|
||||||
|
|
||||||
|
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||||
|
"eepwren - Enable / disable / query EEPROM write access\n",
|
||||||
|
NULL);
|
||||||
|
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||||
|
|
|
@ -22,13 +22,12 @@
|
||||||
#
|
#
|
||||||
|
|
||||||
include $(TOPDIR)/config.mk
|
include $(TOPDIR)/config.mk
|
||||||
ifneq ($(OBJTREE),$(SRCTREE))
|
|
||||||
$(shell mkdir -p $(obj)../common)
|
|
||||||
endif
|
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS = $(BOARD).o strataflash.o ../common/misc.o
|
COBJS = $(BOARD).o cmd_pmc440.o sdram.o fpga.o \
|
||||||
|
../common/cmd_loadpci.o
|
||||||
|
|
||||||
SOBJS = init.o
|
SOBJS = init.o
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
|
@ -36,7 +35,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
|
||||||
$(LIB): $(OBJS) $(SOBJS)
|
$(LIB): $(OBJS) $(SOBJS)
|
||||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||||
|
|
||||||
clean:
|
clean:
|
||||||
rm -f $(SOBJS) $(OBJS)
|
rm -f $(SOBJS) $(OBJS)
|
558
board/esd/pmc440/cmd_pmc440.c
Normal file
558
board/esd/pmc440/cmd_pmc440.c
Normal file
|
@ -0,0 +1,558 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <command.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/cache.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
|
||||||
|
#include "pmc440.h"
|
||||||
|
|
||||||
|
int is_monarch(void);
|
||||||
|
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
|
||||||
|
int eeprom_write_enable(unsigned dev_addr, int state);
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_BSP)
|
||||||
|
|
||||||
|
static int got_fifoirq;
|
||||||
|
static int got_hcirq;
|
||||||
|
|
||||||
|
int fpga_interrupt(u32 arg)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
|
||||||
|
int rc = -1; /* not for us */
|
||||||
|
u32 status = FPGA_IN32(&fpga->status);
|
||||||
|
|
||||||
|
/* check for interrupt from fifo module */
|
||||||
|
if (status & STATUS_FIFO_ISF) {
|
||||||
|
/* disable this int source */
|
||||||
|
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
|
||||||
|
rc = 0;
|
||||||
|
got_fifoirq = 1; /* trigger backend */
|
||||||
|
}
|
||||||
|
|
||||||
|
if (status & STATUS_HOST_ISF) {
|
||||||
|
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
|
||||||
|
rc = 0;
|
||||||
|
got_hcirq = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
|
||||||
|
got_hcirq = 0;
|
||||||
|
|
||||||
|
FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
|
||||||
|
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
|
||||||
|
|
||||||
|
irq_install_handler(IRQ0_FPGA,
|
||||||
|
(interrupt_handler_t *)fpga_interrupt,
|
||||||
|
fpga);
|
||||||
|
|
||||||
|
FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
|
||||||
|
|
||||||
|
while (!got_hcirq) {
|
||||||
|
/* Abort if ctrl-c was pressed */
|
||||||
|
if (ctrlc()) {
|
||||||
|
puts("\nAbort\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (got_hcirq)
|
||||||
|
printf("Got interrupt!\n");
|
||||||
|
|
||||||
|
FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
|
||||||
|
irq_free_handler(IRQ0_FPGA);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(
|
||||||
|
waithci, 1, 1, do_waithci,
|
||||||
|
"waithci - Wait for host control interrupt\n",
|
||||||
|
NULL
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
|
||||||
|
{
|
||||||
|
u32 ctrl;
|
||||||
|
|
||||||
|
while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
|
||||||
|
printf("%5d %d %3d %08x",
|
||||||
|
(*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
|
||||||
|
FPGA_IN32(&fpga->fifo[f].data));
|
||||||
|
if (ctrl & FIFO_OVERFLOW) {
|
||||||
|
printf(" OVERFLOW\n");
|
||||||
|
FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
|
||||||
|
} else
|
||||||
|
printf("\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
int i;
|
||||||
|
int n = 0;
|
||||||
|
u32 ctrl, data, f;
|
||||||
|
char str[] = "\\|/-";
|
||||||
|
int abort = 0;
|
||||||
|
int count = 0;
|
||||||
|
int count2 = 0;
|
||||||
|
|
||||||
|
switch (argc) {
|
||||||
|
case 1:
|
||||||
|
/* print all fifos status information */
|
||||||
|
printf("fifo level status\n");
|
||||||
|
printf("______________________________\n");
|
||||||
|
for (i=0; i<FIFO_COUNT; i++) {
|
||||||
|
ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
|
||||||
|
printf(" %d %3d %s%s%s %s\n",
|
||||||
|
i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
|
||||||
|
ctrl & FIFO_FULL ? "FULL " : "",
|
||||||
|
ctrl & FIFO_EMPTY ? "EMPTY " : "",
|
||||||
|
ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
|
||||||
|
ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
/* completely read out fifo 'n' */
|
||||||
|
if (!strcmp(argv[1],"read")) {
|
||||||
|
printf(" # fifo level data\n");
|
||||||
|
printf("______________________________\n");
|
||||||
|
|
||||||
|
for (i=0; i<FIFO_COUNT; i++)
|
||||||
|
dump_fifo(fpga, i, &n);
|
||||||
|
|
||||||
|
} else if (!strcmp(argv[1],"wait")) {
|
||||||
|
got_fifoirq = 0;
|
||||||
|
|
||||||
|
irq_install_handler(IRQ0_FPGA,
|
||||||
|
(interrupt_handler_t *)fpga_interrupt,
|
||||||
|
fpga);
|
||||||
|
|
||||||
|
printf(" # fifo level data\n");
|
||||||
|
printf("______________________________\n");
|
||||||
|
|
||||||
|
/* enable all fifo interrupts */
|
||||||
|
FPGA_OUT32(&fpga->hostctrl,
|
||||||
|
HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
|
||||||
|
for (i=0; i<FIFO_COUNT; i++) {
|
||||||
|
/* enable interrupts from all fifos */
|
||||||
|
FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
|
||||||
|
}
|
||||||
|
|
||||||
|
while (1) {
|
||||||
|
/* wait loop */
|
||||||
|
while (!got_fifoirq) {
|
||||||
|
count++;
|
||||||
|
if (!(count % 100)) {
|
||||||
|
count2++;
|
||||||
|
putc(0x08); /* backspace */
|
||||||
|
putc(str[count2 % 4]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Abort if ctrl-c was pressed */
|
||||||
|
if ((abort = ctrlc())) {
|
||||||
|
puts("\nAbort\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
udelay(1000);
|
||||||
|
}
|
||||||
|
if (abort)
|
||||||
|
break;
|
||||||
|
|
||||||
|
/* simple fifo backend */
|
||||||
|
if (got_fifoirq) {
|
||||||
|
for (i=0; i<FIFO_COUNT; i++)
|
||||||
|
dump_fifo(fpga, i, &n);
|
||||||
|
|
||||||
|
got_fifoirq = 0;
|
||||||
|
/* unmask global fifo irq */
|
||||||
|
FPGA_OUT32(&fpga->hostctrl,
|
||||||
|
HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* disable all fifo interrupts */
|
||||||
|
FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
|
||||||
|
for (i=0; i<FIFO_COUNT; i++)
|
||||||
|
FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
|
||||||
|
|
||||||
|
irq_free_handler(IRQ0_FPGA);
|
||||||
|
|
||||||
|
} else {
|
||||||
|
printf("Usage:\nfifo %s\n", cmdtp->help);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 4:
|
||||||
|
case 5:
|
||||||
|
if (!strcmp(argv[1],"write")) {
|
||||||
|
/* get fifo number or fifo address */
|
||||||
|
f = simple_strtoul(argv[2], NULL, 16);
|
||||||
|
|
||||||
|
/* data paramter */
|
||||||
|
data = simple_strtoul(argv[3], NULL, 16);
|
||||||
|
|
||||||
|
/* get optional count parameter */
|
||||||
|
n = 1;
|
||||||
|
if (argc >= 5)
|
||||||
|
n = (int)simple_strtoul(argv[4], NULL, 10);
|
||||||
|
|
||||||
|
if (f < FIFO_COUNT) {
|
||||||
|
printf("writing %d x %08x to fifo %d\n",
|
||||||
|
n, data, f);
|
||||||
|
for (i=0; i<n; i++)
|
||||||
|
FPGA_OUT32(&fpga->fifo[f].data, data);
|
||||||
|
} else {
|
||||||
|
printf("writing %d x %08x to fifo port at address %08x\n",
|
||||||
|
n, data, f);
|
||||||
|
for (i=0; i<n; i++)
|
||||||
|
out32(f, data);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
printf("Usage:\nfifo %s\n", cmdtp->help);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
printf("Usage:\nfifo %s\n", cmdtp->help);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(
|
||||||
|
fifo, 5, 1, do_fifo,
|
||||||
|
"fifo - Fifo module operations\n",
|
||||||
|
"wait\nfifo read\n"
|
||||||
|
"fifo write fifo(0..3) data [cnt=1]\n"
|
||||||
|
"fifo write address(>=4) data [cnt=1]\n"
|
||||||
|
" - without arguments: print all fifo's status\n"
|
||||||
|
" - with 'wait' argument: interrupt driven read from all fifos\n"
|
||||||
|
" - with 'read' argument: read current contents from all fifos\n"
|
||||||
|
" - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n"
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
ulong sdsdp[5];
|
||||||
|
ulong delay;
|
||||||
|
int count=16;
|
||||||
|
|
||||||
|
if (argc < 2) {
|
||||||
|
printf("Usage:\nsbe %s\n", cmdtp->help);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (argc > 1) {
|
||||||
|
if (!strcmp(argv[1], "400")) {
|
||||||
|
/* PLB=133MHz, PLB/PCI=4 */
|
||||||
|
printf("Bootstrapping for 400MHz\n");
|
||||||
|
sdsdp[0]=0x8678624e;
|
||||||
|
sdsdp[1]=0x0947a030;
|
||||||
|
sdsdp[2]=0x40082350;
|
||||||
|
sdsdp[3]=0x0d050000;
|
||||||
|
} else if (!strcmp(argv[1], "533")) {
|
||||||
|
/* PLB=133MHz, PLB/PCI=3 */
|
||||||
|
printf("Bootstrapping for 533MHz\n");
|
||||||
|
sdsdp[0]=0x87788252;
|
||||||
|
sdsdp[1]=0x095fa030;
|
||||||
|
sdsdp[2]=0x40082350;
|
||||||
|
sdsdp[3]=0x0d050000;
|
||||||
|
} else if (!strcmp(argv[1], "667")) {
|
||||||
|
/* PLB=133MHz, PLB/PCI=4 */
|
||||||
|
printf("Bootstrapping for 667MHz\n");
|
||||||
|
sdsdp[0]=0x8778a256;
|
||||||
|
sdsdp[1]=0x0947a030;
|
||||||
|
sdsdp[2]=0x40082350;
|
||||||
|
sdsdp[3]=0x0d050000;
|
||||||
|
} else if (!strcmp(argv[1], "test")) {
|
||||||
|
/* TODO: this will replace the 667 MHz config above.
|
||||||
|
* But it needs some more testing on a real 667 MHz CPU.
|
||||||
|
*/
|
||||||
|
printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n");
|
||||||
|
sdsdp[0]=0x8778a256;
|
||||||
|
sdsdp[1]=0x095fa030;
|
||||||
|
sdsdp[2]=0x40082350;
|
||||||
|
sdsdp[3]=0x0d050000;
|
||||||
|
} else {
|
||||||
|
printf("Usage:\nsbe %s\n", cmdtp->help);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (argc > 2) {
|
||||||
|
sdsdp[4] = 0;
|
||||||
|
if (argv[2][0]=='1')
|
||||||
|
sdsdp[4]=0x19750100;
|
||||||
|
else if (argv[2][0]=='0')
|
||||||
|
sdsdp[4]=0x19750000;
|
||||||
|
if (sdsdp[4])
|
||||||
|
count += 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (argc > 3) {
|
||||||
|
delay = simple_strtoul(argv[3], NULL, 10);
|
||||||
|
if (delay > 20)
|
||||||
|
delay = 20;
|
||||||
|
sdsdp[4] |= delay;
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("Writing boot EEPROM ...\n");
|
||||||
|
if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
|
||||||
|
0, (uchar*)sdsdp, count) != 0)
|
||||||
|
printf("bootstrap_eeprom_write failed\n");
|
||||||
|
else
|
||||||
|
printf("done (dump via 'i2c md 52 0.1 14')\n");
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(
|
||||||
|
sbe, 4, 0, do_setup_bootstrap_eeprom,
|
||||||
|
"sbe - setup bootstrap eeprom\n",
|
||||||
|
"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(CONFIG_PRAM)
|
||||||
|
#include <environment.h>
|
||||||
|
extern env_t *env_ptr;
|
||||||
|
|
||||||
|
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
u32 memsize;
|
||||||
|
u32 pram, env_base;
|
||||||
|
char *v;
|
||||||
|
u32 param;
|
||||||
|
ulong *lptr;
|
||||||
|
|
||||||
|
memsize = gd->bd->bi_memsize;
|
||||||
|
|
||||||
|
v = getenv("pram");
|
||||||
|
if (v)
|
||||||
|
pram = simple_strtoul(v, NULL, 10);
|
||||||
|
else {
|
||||||
|
printf("Error: pram undefined. Please define pram in KiB\n");
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
param = memsize - (pram << 10);
|
||||||
|
printf("PARAM: @%08x\n", param);
|
||||||
|
|
||||||
|
memset((void*)param, 0, (pram << 10));
|
||||||
|
env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
|
||||||
|
memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);
|
||||||
|
|
||||||
|
lptr = (ulong*)memsize;
|
||||||
|
*(--lptr) = CFG_ENV_SIZE;
|
||||||
|
*(--lptr) = memsize - env_base;
|
||||||
|
*(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
|
||||||
|
*(--lptr) = 0;
|
||||||
|
|
||||||
|
/* make sure data can be accessed through PCI */
|
||||||
|
flush_dcache_range(param, param + (pram << 10) - 1);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(
|
||||||
|
painit, 1, 1, do_painit,
|
||||||
|
"painit - prepare PciAccess system\n",
|
||||||
|
NULL
|
||||||
|
);
|
||||||
|
#endif /* CONFIG_PRAM */
|
||||||
|
|
||||||
|
|
||||||
|
int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
if (argc > 1) {
|
||||||
|
if (argv[1][0] == '0') {
|
||||||
|
/* assert */
|
||||||
|
printf("self-reset# asserted\n");
|
||||||
|
out_be32((void*)GPIO0_TCR,
|
||||||
|
in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
|
||||||
|
} else {
|
||||||
|
/* deassert */
|
||||||
|
printf("self-reset# deasserted\n");
|
||||||
|
out_be32((void*)GPIO0_TCR,
|
||||||
|
in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
printf("self-reset# is %s\n",
|
||||||
|
in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
|
||||||
|
"active" : "inactive");
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(
|
||||||
|
selfreset, 2, 1, do_selfreset,
|
||||||
|
"selfreset- assert self-reset# signal\n",
|
||||||
|
NULL
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
|
||||||
|
/* requiers bootet FPGA and PLD_IOEN_N active */
|
||||||
|
if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
|
||||||
|
printf("Error: resetout requires a bootet FPGA\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (argc > 1) {
|
||||||
|
if (argv[1][0] == '0') {
|
||||||
|
/* assert */
|
||||||
|
printf("PMC-RESETOUT# asserted\n");
|
||||||
|
FPGA_OUT32(&fpga->hostctrl,
|
||||||
|
HOSTCTRL_PMCRSTOUT_GATE);
|
||||||
|
} else {
|
||||||
|
/* deassert */
|
||||||
|
printf("PMC-RESETOUT# deasserted\n");
|
||||||
|
FPGA_OUT32(&fpga->hostctrl,
|
||||||
|
HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
printf("PMC-RESETOUT# is %s\n",
|
||||||
|
FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
|
||||||
|
"inactive" : "active");
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(
|
||||||
|
resetout, 2, 1, do_resetout,
|
||||||
|
"resetout - assert PMC-RESETOUT# signal\n",
|
||||||
|
NULL
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
if (is_monarch()) {
|
||||||
|
printf("This command is only supported in non-monarch mode\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (argc > 1) {
|
||||||
|
if (argv[1][0] == '0') {
|
||||||
|
/* assert */
|
||||||
|
printf("inta# asserted\n");
|
||||||
|
out_be32((void*)GPIO1_TCR,
|
||||||
|
in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
|
||||||
|
} else {
|
||||||
|
/* deassert */
|
||||||
|
printf("inta# deasserted\n");
|
||||||
|
out_be32((void*)GPIO1_TCR,
|
||||||
|
in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive");
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(
|
||||||
|
inta, 2, 1, do_inta,
|
||||||
|
"inta - Assert/Deassert or query INTA# state in non-monarch mode\n",
|
||||||
|
NULL
|
||||||
|
);
|
||||||
|
|
||||||
|
|
||||||
|
/* test-only */
|
||||||
|
int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
ulong pciaddr;
|
||||||
|
|
||||||
|
if (argc > 1) {
|
||||||
|
pciaddr = simple_strtoul(argv[1], NULL, 16);
|
||||||
|
|
||||||
|
pciaddr &= 0xf0000000;
|
||||||
|
|
||||||
|
/* map PCI address at 0xc0000000 in PLB space */
|
||||||
|
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */
|
||||||
|
out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */
|
||||||
|
out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */
|
||||||
|
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */
|
||||||
|
out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */
|
||||||
|
} else {
|
||||||
|
printf("Usage:\npmm %s\n", cmdtp->help);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(
|
||||||
|
pmm, 2, 1, do_pmm,
|
||||||
|
"pmm - Setup pmm[1] registers\n",
|
||||||
|
"<pciaddr> (pciaddr will be aligned to 256MB)\n"
|
||||||
|
);
|
||||||
|
|
||||||
|
#if defined(CFG_EEPROM_WREN)
|
||||||
|
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
int query = argc == 1;
|
||||||
|
int state = 0;
|
||||||
|
|
||||||
|
if (query) {
|
||||||
|
/* Query write access state. */
|
||||||
|
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
|
||||||
|
if (state < 0) {
|
||||||
|
puts("Query of write access state failed.\n");
|
||||||
|
} else {
|
||||||
|
printf("Write access for device 0x%0x is %sabled.\n",
|
||||||
|
CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||||
|
state = 0;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
if ('0' == argv[1][0]) {
|
||||||
|
/* Disable write access. */
|
||||||
|
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
|
||||||
|
} else {
|
||||||
|
/* Enable write access. */
|
||||||
|
state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
|
||||||
|
}
|
||||||
|
if (state < 0) {
|
||||||
|
puts("Setup of write access state failed.\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return state;
|
||||||
|
}
|
||||||
|
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||||
|
"eepwren - Enable / disable / query EEPROM write access\n",
|
||||||
|
NULL);
|
||||||
|
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||||
|
|
||||||
|
#endif /* CONFIG_CMD_BSP */
|
|
@ -20,18 +20,14 @@
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
# MA 02111-1307 USA
|
# MA 02111-1307 USA
|
||||||
#
|
#
|
||||||
|
|
||||||
#
|
#
|
||||||
# esd ADCIOP boards
|
# AMCC 440EPx Reference Platform (Sequoia) board
|
||||||
#
|
#
|
||||||
|
|
||||||
#TEXT_BASE = 0xFFFE0000
|
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||||
|
|
||||||
ifeq ($(ramsym),1)
|
ifndef TEXT_BASE
|
||||||
TEXT_BASE = 0x07FD0000
|
TEXT_BASE = 0xFFFA0000
|
||||||
else
|
|
||||||
TEXT_BASE = 0xFFFC0000
|
|
||||||
#TEXT_BASE = 0x01fc0000
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
461
board/esd/pmc440/fpga.c
Normal file
461
board/esd/pmc440/fpga.c
Normal file
|
@ -0,0 +1,461 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <spartan2.h>
|
||||||
|
#include <spartan3.h>
|
||||||
|
#include <command.h>
|
||||||
|
#include "fpga.h"
|
||||||
|
#include "pmc440.h"
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#if defined(CONFIG_FPGA)
|
||||||
|
|
||||||
|
#define USE_SP_CODE
|
||||||
|
|
||||||
|
#ifdef USE_SP_CODE
|
||||||
|
Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = {
|
||||||
|
fpga_pre_config_fn,
|
||||||
|
fpga_pgm_fn,
|
||||||
|
fpga_init_fn,
|
||||||
|
NULL, /* err */
|
||||||
|
fpga_done_fn,
|
||||||
|
fpga_clk_fn,
|
||||||
|
fpga_cs_fn,
|
||||||
|
fpga_wr_fn,
|
||||||
|
NULL, /* rdata */
|
||||||
|
fpga_wdata_fn,
|
||||||
|
fpga_busy_fn,
|
||||||
|
fpga_abort_fn,
|
||||||
|
fpga_post_config_fn,
|
||||||
|
};
|
||||||
|
#else
|
||||||
|
Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = {
|
||||||
|
fpga_pre_config_fn,
|
||||||
|
fpga_pgm_fn,
|
||||||
|
fpga_clk_fn,
|
||||||
|
fpga_init_fn,
|
||||||
|
fpga_done_fn,
|
||||||
|
fpga_wr_fn,
|
||||||
|
fpga_post_config_fn,
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = {
|
||||||
|
ngcc_fpga_pre_config_fn,
|
||||||
|
ngcc_fpga_pgm_fn,
|
||||||
|
ngcc_fpga_clk_fn,
|
||||||
|
ngcc_fpga_init_fn,
|
||||||
|
ngcc_fpga_done_fn,
|
||||||
|
ngcc_fpga_wr_fn,
|
||||||
|
ngcc_fpga_post_config_fn
|
||||||
|
};
|
||||||
|
|
||||||
|
Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
|
||||||
|
XILINX_XC3S1200E_DESC(
|
||||||
|
#ifdef USE_SP_CODE
|
||||||
|
slave_parallel,
|
||||||
|
#else
|
||||||
|
slave_serial,
|
||||||
|
#endif
|
||||||
|
(void *)&pmc440_fpga_fns,
|
||||||
|
0),
|
||||||
|
XILINX_XC2S200_DESC(
|
||||||
|
slave_serial,
|
||||||
|
(void *)&ngcc_fpga_fns,
|
||||||
|
0)
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set the active-low FPGA reset signal.
|
||||||
|
*/
|
||||||
|
void fpga_reset(int assert)
|
||||||
|
{
|
||||||
|
debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
|
||||||
|
if (assert) {
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
|
||||||
|
debug("asserted\n");
|
||||||
|
} else {
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
|
||||||
|
debug("deasserted\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Initialize the SelectMap interface. We assume that the mode and the
|
||||||
|
* initial state of all of the port pins have already been set!
|
||||||
|
*/
|
||||||
|
void fpga_serialslave_init(void)
|
||||||
|
{
|
||||||
|
debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__,
|
||||||
|
__LINE__);
|
||||||
|
fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set the FPGA's active-low SelectMap program line to the specified level
|
||||||
|
*/
|
||||||
|
int fpga_pgm_fn(int assert, int flush, int cookie)
|
||||||
|
{
|
||||||
|
debug("%s:%d: FPGA PROGRAM ",
|
||||||
|
__FUNCTION__, __LINE__);
|
||||||
|
|
||||||
|
if (assert) {
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_PRG);
|
||||||
|
debug("asserted\n");
|
||||||
|
} else {
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_PRG);
|
||||||
|
debug("deasserted\n");
|
||||||
|
}
|
||||||
|
return assert;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
|
||||||
|
* asserted (low).
|
||||||
|
*/
|
||||||
|
int fpga_init_fn(int cookie)
|
||||||
|
{
|
||||||
|
if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_INIT)
|
||||||
|
return 0;
|
||||||
|
else
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef USE_SP_CODE
|
||||||
|
int fpga_abort_fn(int cookie)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int fpga_cs_fn(int assert_cs, int flush, int cookie)
|
||||||
|
{
|
||||||
|
return assert_cs;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int fpga_busy_fn(int cookie)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Test the state of the active-high FPGA DONE pin
|
||||||
|
*/
|
||||||
|
int fpga_done_fn(int cookie)
|
||||||
|
{
|
||||||
|
if (in_be32((void*)GPIO1_IR) & GPIO1_FPGA_DONE)
|
||||||
|
return 1;
|
||||||
|
else
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA pre-configuration function. Just make sure that
|
||||||
|
* FPGA reset is asserted to keep the FPGA from starting up after
|
||||||
|
* configuration.
|
||||||
|
*/
|
||||||
|
int fpga_pre_config_fn(int cookie)
|
||||||
|
{
|
||||||
|
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
|
||||||
|
fpga_reset(TRUE);
|
||||||
|
|
||||||
|
/* release init# */
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT);
|
||||||
|
/* disable PLD IOs */
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA post configuration function. Blip the FPGA reset line and then see if
|
||||||
|
* the FPGA appears to be running.
|
||||||
|
*/
|
||||||
|
int fpga_post_config_fn(int cookie)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
int rc=0;
|
||||||
|
char *s;
|
||||||
|
|
||||||
|
debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
|
||||||
|
|
||||||
|
/* enable PLD0..7 pins */
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N);
|
||||||
|
|
||||||
|
fpga_reset(TRUE);
|
||||||
|
udelay (100);
|
||||||
|
fpga_reset(FALSE);
|
||||||
|
udelay (100);
|
||||||
|
|
||||||
|
FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK);
|
||||||
|
|
||||||
|
/* NGCC only: enable ledlink */
|
||||||
|
if ((s = getenv("bd_type")) && !strcmp(s, "ngcc"))
|
||||||
|
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
|
||||||
|
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int fpga_clk_fn(int assert_clk, int flush, int cookie)
|
||||||
|
{
|
||||||
|
if (assert_clk)
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_CLK);
|
||||||
|
else
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_CLK);
|
||||||
|
|
||||||
|
return assert_clk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int fpga_wr_fn(int assert_write, int flush, int cookie)
|
||||||
|
{
|
||||||
|
if (assert_write)
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_FPGA_DATA);
|
||||||
|
else
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_FPGA_DATA);
|
||||||
|
|
||||||
|
return assert_write;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef USE_SP_CODE
|
||||||
|
int fpga_wdata_fn(uchar data, int flush, int cookie)
|
||||||
|
{
|
||||||
|
uchar val = data;
|
||||||
|
ulong or = in_be32((void*)GPIO1_OR);
|
||||||
|
int i = 7;
|
||||||
|
do {
|
||||||
|
/* Write data */
|
||||||
|
if (val & 0x80)
|
||||||
|
or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
|
||||||
|
else
|
||||||
|
or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
|
||||||
|
|
||||||
|
out_be32((void*)GPIO1_OR, or);
|
||||||
|
|
||||||
|
/* Assert the clock */
|
||||||
|
or |= GPIO1_FPGA_CLK;
|
||||||
|
out_be32((void*)GPIO1_OR, or);
|
||||||
|
val <<= 1;
|
||||||
|
i --;
|
||||||
|
} while (i > 0);
|
||||||
|
|
||||||
|
/* Write last data bit (the 8th clock comes from the sp_load() code */
|
||||||
|
if (val & 0x80)
|
||||||
|
or = (or & ~GPIO1_FPGA_CLK) | GPIO1_FPGA_DATA;
|
||||||
|
else
|
||||||
|
or = or & ~(GPIO1_FPGA_CLK | GPIO1_FPGA_DATA);
|
||||||
|
|
||||||
|
out_be32((void*)GPIO1_OR, or);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define NGCC_FPGA_PRG CLOCK_EN
|
||||||
|
#define NGCC_FPGA_DATA RESET_OUT
|
||||||
|
#define NGCC_FPGA_DONE CLOCK_IN
|
||||||
|
#define NGCC_FPGA_INIT IRIGB_R_IN
|
||||||
|
#define NGCC_FPGA_CLK CLOCK_OUT
|
||||||
|
|
||||||
|
void ngcc_fpga_serialslave_init(void)
|
||||||
|
{
|
||||||
|
debug("%s:%d: Initialize serial slave interface\n",
|
||||||
|
__FUNCTION__, __LINE__);
|
||||||
|
|
||||||
|
/* make sure program pin is inactive */
|
||||||
|
ngcc_fpga_pgm_fn (FALSE, FALSE, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set the active-low FPGA reset signal.
|
||||||
|
*/
|
||||||
|
void ngcc_fpga_reset(int assert)
|
||||||
|
{
|
||||||
|
debug("%s:%d: RESET ", __FUNCTION__, __LINE__);
|
||||||
|
|
||||||
|
if (assert) {
|
||||||
|
FPGA_CLRBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
|
||||||
|
debug("asserted\n");
|
||||||
|
} else {
|
||||||
|
FPGA_SETBITS(NGCC_CTRL_BASE, NGCC_CTRL_FPGARST_N);
|
||||||
|
debug("deasserted\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set the FPGA's active-low SelectMap program line to the specified level
|
||||||
|
*/
|
||||||
|
int ngcc_fpga_pgm_fn(int assert, int flush, int cookie)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
|
||||||
|
debug("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
|
||||||
|
|
||||||
|
if (assert) {
|
||||||
|
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_PRG);
|
||||||
|
debug("asserted\n");
|
||||||
|
} else {
|
||||||
|
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_PRG);
|
||||||
|
debug("deasserted\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
return assert;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Test the state of the active-low FPGA INIT line. Return 1 on INIT
|
||||||
|
* asserted (low).
|
||||||
|
*/
|
||||||
|
int ngcc_fpga_init_fn(int cookie)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
|
||||||
|
debug("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
|
||||||
|
if (FPGA_IN32(&fpga->status) & NGCC_FPGA_INIT) {
|
||||||
|
debug("high\n");
|
||||||
|
return 0;
|
||||||
|
} else {
|
||||||
|
debug("low\n");
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Test the state of the active-high FPGA DONE pin
|
||||||
|
*/
|
||||||
|
int ngcc_fpga_done_fn(int cookie)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
|
||||||
|
debug("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
|
||||||
|
if (FPGA_IN32(&fpga->status) & NGCC_FPGA_DONE) {
|
||||||
|
debug("DONE high\n");
|
||||||
|
return 1;
|
||||||
|
} else {
|
||||||
|
debug("low\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA pre-configuration function.
|
||||||
|
*/
|
||||||
|
int ngcc_fpga_pre_config_fn(int cookie)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
|
||||||
|
|
||||||
|
ngcc_fpga_reset(TRUE);
|
||||||
|
FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00);
|
||||||
|
|
||||||
|
ngcc_fpga_reset(TRUE);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FPGA post configuration function. Blip the FPGA reset line and then see if
|
||||||
|
* the FPGA appears to be running.
|
||||||
|
*/
|
||||||
|
int ngcc_fpga_post_config_fn(int cookie)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
|
||||||
|
debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__);
|
||||||
|
|
||||||
|
udelay (100);
|
||||||
|
ngcc_fpga_reset(FALSE);
|
||||||
|
|
||||||
|
FPGA_SETBITS(&fpga->ctrla, 0x29f8c000);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
|
||||||
|
if (assert_clk)
|
||||||
|
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_CLK);
|
||||||
|
else
|
||||||
|
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_CLK);
|
||||||
|
|
||||||
|
return assert_clk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie)
|
||||||
|
{
|
||||||
|
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
|
||||||
|
|
||||||
|
if (assert_write)
|
||||||
|
FPGA_SETBITS(&fpga->ctrla, NGCC_FPGA_DATA);
|
||||||
|
else
|
||||||
|
FPGA_CLRBITS(&fpga->ctrla, NGCC_FPGA_DATA);
|
||||||
|
|
||||||
|
return assert_write;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Initialize the fpga. Return 1 on success, 0 on failure.
|
||||||
|
*/
|
||||||
|
int pmc440_init_fpga(void)
|
||||||
|
{
|
||||||
|
char *s;
|
||||||
|
|
||||||
|
debug("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n",
|
||||||
|
__FUNCTION__, __LINE__, gd->reloc_off);
|
||||||
|
fpga_init(gd->reloc_off);
|
||||||
|
|
||||||
|
fpga_serialslave_init ();
|
||||||
|
debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__);
|
||||||
|
fpga_add (fpga_xilinx, &fpga[0]);
|
||||||
|
|
||||||
|
/* NGCC only */
|
||||||
|
if ((s = getenv("bd_type")) && !strcmp(s, "ngcc")) {
|
||||||
|
ngcc_fpga_serialslave_init ();
|
||||||
|
debug("%s:%d: Adding fpga 1\n", __FUNCTION__, __LINE__);
|
||||||
|
fpga_add (fpga_xilinx, &fpga[1]);
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_FPGA */
|
47
board/esd/pmc440/fpga.h
Normal file
47
board/esd/pmc440/fpga.h
Normal file
|
@ -0,0 +1,47 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
extern int pmc440_init_fpga(void);
|
||||||
|
|
||||||
|
extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
|
||||||
|
extern int fpga_init_fn(int cookie);
|
||||||
|
extern int fpga_err_fn(int cookie);
|
||||||
|
extern int fpga_done_fn(int cookie);
|
||||||
|
extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
|
||||||
|
extern int fpga_cs_fn(int assert_cs, int flush, int cookie);
|
||||||
|
extern int fpga_wr_fn(int assert_write, int flush, int cookie);
|
||||||
|
extern int fpga_wdata_fn (uchar data, int flush, int cookie);
|
||||||
|
extern int fpga_read_data_fn(unsigned char *data, int cookie);
|
||||||
|
extern int fpga_write_data_fn(unsigned char data, int flush, int cookie);
|
||||||
|
extern int fpga_busy_fn(int cookie);
|
||||||
|
extern int fpga_abort_fn(int cookie );
|
||||||
|
extern int fpga_pre_config_fn(int cookie );
|
||||||
|
extern int fpga_post_config_fn(int cookie );
|
||||||
|
|
||||||
|
extern int ngcc_fpga_pgm_fn(int assert_pgm, int flush, int cookie);
|
||||||
|
extern int ngcc_fpga_init_fn(int cookie);
|
||||||
|
extern int ngcc_fpga_done_fn(int cookie);
|
||||||
|
extern int ngcc_fpga_clk_fn(int assert_clk, int flush, int cookie);
|
||||||
|
extern int ngcc_fpga_wr_fn(int assert_write, int flush, int cookie);
|
||||||
|
extern int ngcc_fpga_pre_config_fn(int cookie );
|
||||||
|
extern int ngcc_fpga_post_config_fn(int cookie );
|
122
board/esd/pmc440/init.S
Normal file
122
board/esd/pmc440/init.S
Normal file
|
@ -0,0 +1,122 @@
|
||||||
|
/*
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <ppc_asm.tmpl>
|
||||||
|
#include <asm-ppc/mmu.h>
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
* TLB TABLE
|
||||||
|
*
|
||||||
|
* This table is used by the cpu boot code to setup the initial tlb
|
||||||
|
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||||
|
* this table lets each board set things up however they like.
|
||||||
|
*
|
||||||
|
* Pointer to the table is returned in r1
|
||||||
|
*
|
||||||
|
*************************************************************************/
|
||||||
|
.section .bootpg,"ax"
|
||||||
|
.globl tlbtab
|
||||||
|
|
||||||
|
tlbtab:
|
||||||
|
tlbtab_start
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||||
|
* speed up boot process. It is patched after relocation to enable SA_I
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_NAND_SPL
|
||||||
|
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||||
|
#else
|
||||||
|
tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* TLB-entry for DDR SDRAM (Up to 2GB) */
|
||||||
|
#ifdef CONFIG_4xx_DCACHE
|
||||||
|
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
|
||||||
|
#else
|
||||||
|
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CFG_INIT_RAM_DCACHE
|
||||||
|
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||||
|
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* TLB-entry for PCI Memory */
|
||||||
|
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
|
||||||
|
/* TLB-entries for EBC */
|
||||||
|
/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
|
||||||
|
* tlb entry.
|
||||||
|
* This dummy entry is only for convinience in order not to modify the
|
||||||
|
* amount of entries. Currently OS/9 relies on this :-)
|
||||||
|
*/
|
||||||
|
tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||||
|
|
||||||
|
/* TLB-entry for NAND */
|
||||||
|
tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||||
|
|
||||||
|
/* TLB-entry for Internal Registers & OCM */
|
||||||
|
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||||
|
|
||||||
|
/*TLB-entry PCI registers*/
|
||||||
|
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||||
|
|
||||||
|
/* TLB-entry for peripherals */
|
||||||
|
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||||
|
|
||||||
|
/* TLB-entry PCI IO space */
|
||||||
|
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||||
|
|
||||||
|
/* TODO: what about high IO space */
|
||||||
|
tlbtab_end
|
||||||
|
|
||||||
|
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||||
|
/*
|
||||||
|
* For NAND booting the first TLB has to be reconfigured to full size
|
||||||
|
* and with caching disabled after running from RAM!
|
||||||
|
*/
|
||||||
|
#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
|
||||||
|
#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
|
||||||
|
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||||
|
|
||||||
|
.globl reconfig_tlb0
|
||||||
|
reconfig_tlb0:
|
||||||
|
sync
|
||||||
|
isync
|
||||||
|
addi r4,r0,0x0000 /* TLB entry #0 */
|
||||||
|
lis r5,TLB00@h
|
||||||
|
ori r5,r5,TLB00@l
|
||||||
|
tlbwe r5,r4,0x0000 /* Save it out */
|
||||||
|
lis r5,TLB01@h
|
||||||
|
ori r5,r5,TLB01@l
|
||||||
|
tlbwe r5,r4,0x0001 /* Save it out */
|
||||||
|
lis r5,TLB02@h
|
||||||
|
ori r5,r5,TLB02@l
|
||||||
|
tlbwe r5,r4,0x0002 /* Save it out */
|
||||||
|
sync
|
||||||
|
isync
|
||||||
|
blr
|
||||||
|
#endif
|
898
board/esd/pmc440/pmc440.c
Normal file
898
board/esd/pmc440/pmc440.c
Normal file
|
@ -0,0 +1,898 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
|
||||||
|
* Based on board/amcc/sequoia/sequoia.c
|
||||||
|
*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||||
|
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <libfdt.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
|
#include <ppc440.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <command.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#ifdef CONFIG_RESET_PHY_R
|
||||||
|
#include <miiphy.h>
|
||||||
|
#endif
|
||||||
|
#include <serial.h>
|
||||||
|
#include "fpga.h"
|
||||||
|
#include "pmc440.h"
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||||
|
|
||||||
|
ulong flash_get_size(ulong base, int banknum);
|
||||||
|
int pci_is_66mhz(void);
|
||||||
|
int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
|
||||||
|
|
||||||
|
|
||||||
|
struct serial_device *default_serial_console(void)
|
||||||
|
{
|
||||||
|
uchar buf[4];
|
||||||
|
ulong delay;
|
||||||
|
int i;
|
||||||
|
ulong val;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Use default console on P4 when strapping jumper
|
||||||
|
* is installed (bootstrap option != 'H').
|
||||||
|
*/
|
||||||
|
mfsdr(SDR_PINSTP, val);
|
||||||
|
if (((val & 0xf0000000) >> 29) != 7)
|
||||||
|
return &serial1_device;
|
||||||
|
|
||||||
|
ulong scratchreg = in_be32((void*)GPIO0_ISR3L);
|
||||||
|
if (!(scratchreg & 0x80)) {
|
||||||
|
/* mark scratchreg valid */
|
||||||
|
scratchreg = (scratchreg & 0xffffff00) | 0x80;
|
||||||
|
|
||||||
|
i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR, 0x10, buf, 4);
|
||||||
|
if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
|
||||||
|
scratchreg |= buf[2];
|
||||||
|
|
||||||
|
/* bringup delay for console */
|
||||||
|
for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {
|
||||||
|
udelay(1000);
|
||||||
|
}
|
||||||
|
} else
|
||||||
|
scratchreg |= 0x01;
|
||||||
|
out_be32((void*)GPIO0_ISR3L, scratchreg);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (scratchreg & 0x01)
|
||||||
|
return &serial1_device;
|
||||||
|
else
|
||||||
|
return &serial0_device;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
u32 sdr0_cust0;
|
||||||
|
u32 sdr0_pfc1, sdr0_pfc2;
|
||||||
|
u32 reg;
|
||||||
|
|
||||||
|
/* general EBC configuration (disable EBC timeouts) */
|
||||||
|
mtdcr(ebccfga, xbcfg);
|
||||||
|
mtdcr(ebccfgd, 0xf8400000);
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------
|
||||||
|
* Setup the GPIO pins
|
||||||
|
* TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
|
||||||
|
*-------------------------------------------------------------------*/
|
||||||
|
out32(GPIO0_OR, 0x40000002);
|
||||||
|
out32(GPIO0_TCR, 0x4c90011f);
|
||||||
|
out32(GPIO0_OSRL, 0x28011400);
|
||||||
|
out32(GPIO0_OSRH, 0x55005000);
|
||||||
|
out32(GPIO0_TSRL, 0x08011400);
|
||||||
|
out32(GPIO0_TSRH, 0x55005000);
|
||||||
|
out32(GPIO0_ISR1L, 0x54000000);
|
||||||
|
out32(GPIO0_ISR1H, 0x00000000);
|
||||||
|
out32(GPIO0_ISR2L, 0x44000000);
|
||||||
|
out32(GPIO0_ISR2H, 0x00000100);
|
||||||
|
out32(GPIO0_ISR3L, 0x00000000);
|
||||||
|
out32(GPIO0_ISR3H, 0x00000000);
|
||||||
|
|
||||||
|
out32(GPIO1_OR, 0x80002408);
|
||||||
|
out32(GPIO1_TCR, 0xd6003c08);
|
||||||
|
out32(GPIO1_OSRL, 0x0a5a0000);
|
||||||
|
out32(GPIO1_OSRH, 0x00000000);
|
||||||
|
out32(GPIO1_TSRL, 0x00000000);
|
||||||
|
out32(GPIO1_TSRH, 0x00000000);
|
||||||
|
out32(GPIO1_ISR1L, 0x00005555);
|
||||||
|
out32(GPIO1_ISR1H, 0x40000000);
|
||||||
|
out32(GPIO1_ISR2L, 0x04010000);
|
||||||
|
out32(GPIO1_ISR2H, 0x00000000);
|
||||||
|
out32(GPIO1_ISR3L, 0x01400000);
|
||||||
|
out32(GPIO1_ISR3H, 0x00000000);
|
||||||
|
|
||||||
|
/* patch PLB:PCI divider for 66MHz PCI */
|
||||||
|
mfcpr(clk_spcid, reg);
|
||||||
|
if (pci_is_66mhz() && (reg != 0x02000000)) {
|
||||||
|
mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */
|
||||||
|
|
||||||
|
mfcpr(clk_icfg, reg);
|
||||||
|
reg |= CPR0_ICFG_RLI_MASK;
|
||||||
|
mtcpr(clk_icfg, reg);
|
||||||
|
|
||||||
|
mtspr(dbcr0, 0x20000000); /* do chip reset */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------
|
||||||
|
* Setup the interrupt controller polarities, triggers, etc.
|
||||||
|
*-------------------------------------------------------------------*/
|
||||||
|
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||||
|
mtdcr(uic0er, 0x00000000); /* disable all */
|
||||||
|
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
|
||||||
|
mtdcr(uic0pr, 0xfffff7ef);
|
||||||
|
mtdcr(uic0tr, 0x00000000);
|
||||||
|
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||||
|
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||||
|
|
||||||
|
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||||
|
mtdcr(uic1er, 0x00000000); /* disable all */
|
||||||
|
mtdcr(uic1cr, 0x00000000); /* all non-critical */
|
||||||
|
mtdcr(uic1pr, 0xffffc7f5);
|
||||||
|
mtdcr(uic1tr, 0x00000000);
|
||||||
|
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||||
|
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||||
|
|
||||||
|
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||||
|
mtdcr(uic2er, 0x00000000); /* disable all */
|
||||||
|
mtdcr(uic2cr, 0x00000000); /* all non-critical */
|
||||||
|
mtdcr(uic2pr, 0x27ffffff);
|
||||||
|
mtdcr(uic2tr, 0x00000000);
|
||||||
|
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||||
|
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||||
|
|
||||||
|
/* select Ethernet pins */
|
||||||
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;
|
||||||
|
mfsdr(SDR0_PFC2, sdr0_pfc2);
|
||||||
|
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;
|
||||||
|
|
||||||
|
/* enable 2nd IIC */
|
||||||
|
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
|
||||||
|
|
||||||
|
mtsdr(SDR0_PFC2, sdr0_pfc2);
|
||||||
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
||||||
|
/* setup NAND FLASH */
|
||||||
|
mfsdr(SDR0_CUST0, sdr0_cust0);
|
||||||
|
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
|
||||||
|
SDR0_CUST0_NDFC_ENABLE |
|
||||||
|
SDR0_CUST0_NDFC_BW_8_BIT |
|
||||||
|
SDR0_CUST0_NDFC_ARE_MASK |
|
||||||
|
(0x80000000 >> (28 + CFG_NAND_CS));
|
||||||
|
mtsdr(SDR0_CUST0, sdr0_cust0);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------+
|
||||||
|
| misc_init_r.
|
||||||
|
+---------------------------------------------------------------------------*/
|
||||||
|
int misc_init_r(void)
|
||||||
|
{
|
||||||
|
uint pbcr;
|
||||||
|
int size_val = 0;
|
||||||
|
u32 reg;
|
||||||
|
unsigned long usb2d0cr = 0;
|
||||||
|
unsigned long usb2phy0cr, usb2h0cr = 0;
|
||||||
|
unsigned long sdr0_pfc1;
|
||||||
|
char *act = getenv("usbact");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FLASH stuff...
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Re-do sizing to get full correct info */
|
||||||
|
|
||||||
|
/* adjust flash start and offset */
|
||||||
|
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||||
|
gd->bd->bi_flashoffset = 0;
|
||||||
|
|
||||||
|
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||||
|
mtdcr(ebccfga, pb2cr);
|
||||||
|
#else
|
||||||
|
mtdcr(ebccfga, pb0cr);
|
||||||
|
#endif
|
||||||
|
pbcr = mfdcr(ebccfgd);
|
||||||
|
switch (gd->bd->bi_flashsize) {
|
||||||
|
case 1 << 20:
|
||||||
|
size_val = 0;
|
||||||
|
break;
|
||||||
|
case 2 << 20:
|
||||||
|
size_val = 1;
|
||||||
|
break;
|
||||||
|
case 4 << 20:
|
||||||
|
size_val = 2;
|
||||||
|
break;
|
||||||
|
case 8 << 20:
|
||||||
|
size_val = 3;
|
||||||
|
break;
|
||||||
|
case 16 << 20:
|
||||||
|
size_val = 4;
|
||||||
|
break;
|
||||||
|
case 32 << 20:
|
||||||
|
size_val = 5;
|
||||||
|
break;
|
||||||
|
case 64 << 20:
|
||||||
|
size_val = 6;
|
||||||
|
break;
|
||||||
|
case 128 << 20:
|
||||||
|
size_val = 7;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
|
||||||
|
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||||
|
mtdcr(ebccfga, pb2cr);
|
||||||
|
#else
|
||||||
|
mtdcr(ebccfga, pb0cr);
|
||||||
|
#endif
|
||||||
|
mtdcr(ebccfgd, pbcr);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Re-check to get correct base address
|
||||||
|
*/
|
||||||
|
flash_get_size(gd->bd->bi_flashstart, 0);
|
||||||
|
|
||||||
|
#ifdef CFG_ENV_IS_IN_FLASH
|
||||||
|
/* Monitor protection ON by default */
|
||||||
|
(void)flash_protect(FLAG_PROTECT_SET,
|
||||||
|
-CFG_MONITOR_LEN,
|
||||||
|
0xffffffff,
|
||||||
|
&flash_info[0]);
|
||||||
|
|
||||||
|
/* Env protection ON by default */
|
||||||
|
(void)flash_protect(FLAG_PROTECT_SET,
|
||||||
|
CFG_ENV_ADDR_REDUND,
|
||||||
|
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||||
|
&flash_info[0]);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* USB suff...
|
||||||
|
*/
|
||||||
|
if ((act == NULL || strcmp(act, "hostdev") == 0) &&
|
||||||
|
!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){
|
||||||
|
/* SDR Setting */
|
||||||
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
|
||||||
|
|
||||||
|
/* An 8-bit/60MHz interface is the only possible alternative
|
||||||
|
when connecting the Device to the PHY */
|
||||||
|
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
|
||||||
|
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
|
||||||
|
|
||||||
|
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
||||||
|
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
|
||||||
|
|
||||||
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
|
||||||
|
/*clear resets*/
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x00000000);
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST0, 0x00000000);
|
||||||
|
|
||||||
|
printf("USB: Host\n");
|
||||||
|
|
||||||
|
} else if ((strcmp(act, "dev") == 0) || (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {
|
||||||
|
/*-------------------PATCH-------------------------------*/
|
||||||
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
|
||||||
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
|
||||||
|
udelay (1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x672c6000);
|
||||||
|
|
||||||
|
udelay (1000);
|
||||||
|
mtsdr(SDR0_SRST0, 0x00000080);
|
||||||
|
|
||||||
|
udelay (1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x60206000);
|
||||||
|
|
||||||
|
*(unsigned int *)(0xe0000350) = 0x00000001;
|
||||||
|
|
||||||
|
udelay (1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x60306000);
|
||||||
|
/*-------------------PATCH-------------------------------*/
|
||||||
|
|
||||||
|
/* SDR Setting */
|
||||||
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
|
||||||
|
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
|
||||||
|
|
||||||
|
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
|
||||||
|
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
|
||||||
|
|
||||||
|
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
||||||
|
|
||||||
|
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
|
||||||
|
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
|
||||||
|
|
||||||
|
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
||||||
|
/*clear resets*/
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x00000000);
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST0, 0x00000000);
|
||||||
|
|
||||||
|
printf("USB: Device\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clear PLB4A0_ACR[WRP]
|
||||||
|
* This fix will make the MAL burst disabling patch for the Linux
|
||||||
|
* EMAC driver obsolete.
|
||||||
|
*/
|
||||||
|
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
|
||||||
|
mtdcr(plb4_acr, reg);
|
||||||
|
|
||||||
|
#ifdef CONFIG_FPGA
|
||||||
|
pmc440_init_fpga();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* turn off POST LED */
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);
|
||||||
|
/* turn on RUN LED */
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int is_monarch(void)
|
||||||
|
{
|
||||||
|
if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int pci_is_66mhz(void)
|
||||||
|
{
|
||||||
|
if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)
|
||||||
|
return 1;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_revision(void)
|
||||||
|
{
|
||||||
|
return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
puts("Board: esd GmbH - PMC440");
|
||||||
|
|
||||||
|
gd->board_type = board_revision();
|
||||||
|
printf(", Rev 1.%ld, ", gd->board_type);
|
||||||
|
|
||||||
|
if (!is_monarch()) {
|
||||||
|
puts("non-");
|
||||||
|
}
|
||||||
|
|
||||||
|
printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");
|
||||||
|
return (0);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
|
||||||
|
/*
|
||||||
|
* Assign interrupts to PCI devices. Some OSs rely on this.
|
||||||
|
*/
|
||||||
|
void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
||||||
|
{
|
||||||
|
unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};
|
||||||
|
|
||||||
|
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
|
||||||
|
int_line[PCI_DEV(dev) & 0x03]);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* pci_pre_init
|
||||||
|
*
|
||||||
|
* This routine is called just prior to registering the hose and gives
|
||||||
|
* the board the opportunity to check things. Returning a value of zero
|
||||||
|
* indicates that things are bad & PCI initialization should be aborted.
|
||||||
|
*
|
||||||
|
* Different boards may wish to customize the pci controller structure
|
||||||
|
* (add regions, override default access routines, etc) or perform
|
||||||
|
* certain pre-initialization actions.
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
#if defined(CONFIG_PCI)
|
||||||
|
int pci_pre_init(struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
unsigned long addr;
|
||||||
|
|
||||||
|
/*-------------------------------------------------------------------------+
|
||||||
|
| Set priority for all PLB3 devices to 0.
|
||||||
|
| Set PLB3 arbiter to fair mode.
|
||||||
|
+-------------------------------------------------------------------------*/
|
||||||
|
mfsdr(sdr_amp1, addr);
|
||||||
|
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
|
||||||
|
addr = mfdcr(plb3_acr);
|
||||||
|
mtdcr(plb3_acr, addr | 0x80000000);
|
||||||
|
|
||||||
|
/*-------------------------------------------------------------------------+
|
||||||
|
| Set priority for all PLB4 devices to 0.
|
||||||
|
+-------------------------------------------------------------------------*/
|
||||||
|
mfsdr(sdr_amp0, addr);
|
||||||
|
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
|
||||||
|
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
|
||||||
|
mtdcr(plb4_acr, addr);
|
||||||
|
|
||||||
|
/*-------------------------------------------------------------------------+
|
||||||
|
| Set Nebula PLB4 arbiter to fair mode.
|
||||||
|
+-------------------------------------------------------------------------*/
|
||||||
|
/* Segment0 */
|
||||||
|
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
||||||
|
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
||||||
|
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
||||||
|
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
|
||||||
|
mtdcr(plb0_acr, addr);
|
||||||
|
|
||||||
|
/* Segment1 */
|
||||||
|
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
||||||
|
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
||||||
|
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
||||||
|
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
|
||||||
|
mtdcr(plb1_acr, addr);
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCI_PNP
|
||||||
|
hose->fixup_irq = pmc440_pci_fixup_irq;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_PCI) */
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* pci_target_init
|
||||||
|
*
|
||||||
|
* The bootstrap configuration provides default settings for the pci
|
||||||
|
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||||
|
* may not be sufficient for a given board.
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||||
|
void pci_target_init(struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
* Set up Direct MMIO registers
|
||||||
|
*--------------------------------------------------------------------------*/
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
| PowerPC440EPX PCI Master configuration.
|
||||||
|
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||||
|
| PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
|
||||||
|
| Use byte reversed out routines to handle endianess.
|
||||||
|
| Make this region non-prefetchable.
|
||||||
|
+--------------------------------------------------------------------------*/
|
||||||
|
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
||||||
|
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
||||||
|
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
|
||||||
|
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||||
|
out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, and enable region */
|
||||||
|
|
||||||
|
if (!is_monarch()) {
|
||||||
|
/* BAR1: top 64MB of RAM */
|
||||||
|
out32r(PCIX0_PTM1MS, 0xfc000001); /* Memory Size/Attribute */
|
||||||
|
out32r(PCIX0_PTM1LA, 0x0c000000); /* Local Addr. Reg */
|
||||||
|
} else {
|
||||||
|
/* BAR1: complete 256MB RAM (TODO: make dynamic) */
|
||||||
|
out32r(PCIX0_PTM1MS, 0xf0000001); /* Memory Size/Attribute */
|
||||||
|
out32r(PCIX0_PTM1LA, 0x00000000); /* Local Addr. Reg */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* BAR2: 16 MB FPGA registers */
|
||||||
|
out32r(PCIX0_PTM2MS, 0xff000001); /* Memory Size/Attribute */
|
||||||
|
out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */
|
||||||
|
|
||||||
|
if (is_monarch()) {
|
||||||
|
/* BAR2: map FPGA registers behind system memory at 1GB */
|
||||||
|
pci_write_config_dword(0, PCI_BASE_ADDRESS_2, 0x40000008);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
* Set up Configuration registers
|
||||||
|
*--------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Program the board's vendor id */
|
||||||
|
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
||||||
|
CFG_PCI_SUBSYS_VENDORID);
|
||||||
|
|
||||||
|
#if 0 /* disabled for PMC405 backward compatibility */
|
||||||
|
/* Configure command register as bus master */
|
||||||
|
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* 240nS PCI clock */
|
||||||
|
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
||||||
|
|
||||||
|
/* No error reporting */
|
||||||
|
pci_write_config_word(0, PCI_ERREN, 0);
|
||||||
|
|
||||||
|
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||||
|
|
||||||
|
if (!is_monarch()) {
|
||||||
|
/* Program the board's subsystem id/classcode */
|
||||||
|
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
|
||||||
|
CFG_PCI_SUBSYS_ID_NONMONARCH);
|
||||||
|
pci_write_config_word(0, PCI_CLASS_SUB_CODE,
|
||||||
|
CFG_PCI_CLASSCODE_NONMONARCH);
|
||||||
|
|
||||||
|
/* PCI configuration done: release ERREADY */
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_PPC_EREADY);
|
||||||
|
out_be32((void*)GPIO1_TCR, in_be32((void*)GPIO1_TCR) | GPIO1_PPC_EREADY);
|
||||||
|
} else {
|
||||||
|
/* Program the board's subsystem id/classcode */
|
||||||
|
pci_write_config_word(0, PCI_SUBSYSTEM_ID,
|
||||||
|
CFG_PCI_SUBSYS_ID_MONARCH);
|
||||||
|
pci_write_config_word(0, PCI_CLASS_SUB_CODE,
|
||||||
|
CFG_PCI_CLASSCODE_MONARCH);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* pci_master_init
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
|
||||||
|
void pci_master_init(struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
unsigned short temp_short;
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
| Write the PowerPC440 EP PCI Configuration regs.
|
||||||
|
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||||
|
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||||
|
+--------------------------------------------------------------------------*/
|
||||||
|
if (is_monarch()) {
|
||||||
|
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
||||||
|
pci_write_config_word(0, PCI_COMMAND,
|
||||||
|
temp_short | PCI_COMMAND_MASTER |
|
||||||
|
PCI_COMMAND_MEMORY);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
|
||||||
|
|
||||||
|
|
||||||
|
static void wait_for_pci_ready(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
char *s = getenv("pcidelay");
|
||||||
|
if (s) {
|
||||||
|
int ms = simple_strtoul(s, NULL, 10);
|
||||||
|
printf("PCI: Waiting for %d ms\n", ms);
|
||||||
|
for (i=0; i<ms; i++)
|
||||||
|
udelay(1000);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!(in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY)) {
|
||||||
|
printf("PCI: Waiting for EREADY (CTRL-C to skip) ... ");
|
||||||
|
while (1) {
|
||||||
|
if (ctrlc()) {
|
||||||
|
puts("abort\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
if (in_be32((void*)GPIO1_IR) & GPIO1_PPC_EREADY) {
|
||||||
|
printf("done\n");
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* is_pci_host
|
||||||
|
*
|
||||||
|
* This routine is called to determine if a pci scan should be
|
||||||
|
* performed. With various hardware environments (especially cPCI and
|
||||||
|
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||||
|
* bit in the strap register, or generic host/adapter assumptions.
|
||||||
|
*
|
||||||
|
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||||
|
* 440 pci code requires the board to decide at runtime.
|
||||||
|
*
|
||||||
|
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
#if defined(CONFIG_PCI)
|
||||||
|
int is_pci_host(struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
char *s = getenv("pciscan");
|
||||||
|
if (s == NULL)
|
||||||
|
if (is_monarch()) {
|
||||||
|
wait_for_pci_ready();
|
||||||
|
return 1;
|
||||||
|
} else
|
||||||
|
return 0;
|
||||||
|
else if (!strcmp(s, "yes"))
|
||||||
|
return 1;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_PCI) */
|
||||||
|
#if defined(CONFIG_POST)
|
||||||
|
/*
|
||||||
|
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||||
|
* Called from board_init_f().
|
||||||
|
*/
|
||||||
|
int post_hotkeys_pressed(void)
|
||||||
|
{
|
||||||
|
return 0; /* No hotkeys supported */
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_POST */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef CONFIG_RESET_PHY_R
|
||||||
|
void reset_phy(void)
|
||||||
|
{
|
||||||
|
if (miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0001) == 0) {
|
||||||
|
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0010);
|
||||||
|
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x11, 0x0df0);
|
||||||
|
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x10, 0x0e10);
|
||||||
|
miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, 0x1f, 0x0000);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0001) == 0) {
|
||||||
|
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0010);
|
||||||
|
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x11, 0x0df0);
|
||||||
|
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x10, 0x0e10);
|
||||||
|
miiphy_write("ppc_4xx_eth1", CONFIG_PHY1_ADDR, 0x1f, 0x0000);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CFG_EEPROM_WREN)
|
||||||
|
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||||
|
* <state> -1: deliver current state
|
||||||
|
* 0: disable write
|
||||||
|
* 1: enable write
|
||||||
|
* Returns: -1: wrong device address
|
||||||
|
* 0: dis-/en- able done
|
||||||
|
* 0/1: current state if <state> was -1.
|
||||||
|
*/
|
||||||
|
int eeprom_write_enable(unsigned dev_addr, int state)
|
||||||
|
{
|
||||||
|
if ((CFG_I2C_EEPROM_ADDR != dev_addr) && (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
|
||||||
|
return -1;
|
||||||
|
} else {
|
||||||
|
switch (state) {
|
||||||
|
case 1:
|
||||||
|
/* Enable write access, clear bit GPIO_SINT2. */
|
||||||
|
out32(GPIO0_OR, in32(GPIO0_OR) & ~GPIO0_EP_EEP);
|
||||||
|
state = 0;
|
||||||
|
break;
|
||||||
|
case 0:
|
||||||
|
/* Disable write access, set bit GPIO_SINT2. */
|
||||||
|
out32(GPIO0_OR, in32(GPIO0_OR) | GPIO0_EP_EEP);
|
||||||
|
state = 0;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
/* Read current status back. */
|
||||||
|
state = (0 == (in32(GPIO0_OR) & GPIO0_EP_EEP));
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return state;
|
||||||
|
}
|
||||||
|
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||||
|
|
||||||
|
|
||||||
|
#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
|
||||||
|
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
|
||||||
|
{
|
||||||
|
unsigned end = offset + cnt;
|
||||||
|
unsigned blk_off;
|
||||||
|
int rcode = 0;
|
||||||
|
|
||||||
|
#if defined(CFG_EEPROM_WREN)
|
||||||
|
eeprom_write_enable(dev_addr, 1);
|
||||||
|
#endif
|
||||||
|
/* Write data until done or would cross a write page boundary.
|
||||||
|
* We must write the address again when changing pages
|
||||||
|
* because the address counter only increments within a page.
|
||||||
|
*/
|
||||||
|
|
||||||
|
while (offset < end) {
|
||||||
|
unsigned alen, len;
|
||||||
|
unsigned maxlen;
|
||||||
|
uchar addr[2];
|
||||||
|
|
||||||
|
blk_off = offset & 0xFF; /* block offset */
|
||||||
|
|
||||||
|
addr[0] = offset >> 8; /* block number */
|
||||||
|
addr[1] = blk_off; /* block offset */
|
||||||
|
alen = 2;
|
||||||
|
addr[0] |= dev_addr; /* insert device address */
|
||||||
|
|
||||||
|
len = end - offset;
|
||||||
|
|
||||||
|
#define BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
|
||||||
|
#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
|
||||||
|
|
||||||
|
maxlen = BOOT_EEPROM_PAGE_SIZE - BOOT_EEPROM_PAGE_OFFSET(blk_off);
|
||||||
|
if (maxlen > I2C_RXTX_LEN)
|
||||||
|
maxlen = I2C_RXTX_LEN;
|
||||||
|
|
||||||
|
if (len > maxlen)
|
||||||
|
len = maxlen;
|
||||||
|
|
||||||
|
if (i2c_write (addr[0], offset, alen-1, buffer, len) != 0)
|
||||||
|
rcode = 1;
|
||||||
|
|
||||||
|
buffer += len;
|
||||||
|
offset += len;
|
||||||
|
|
||||||
|
#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
|
||||||
|
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#if defined(CFG_EEPROM_WREN)
|
||||||
|
eeprom_write_enable(dev_addr, 0);
|
||||||
|
#endif
|
||||||
|
return rcode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int bootstrap_eeprom_read (unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt)
|
||||||
|
{
|
||||||
|
unsigned end = offset + cnt;
|
||||||
|
unsigned blk_off;
|
||||||
|
int rcode = 0;
|
||||||
|
|
||||||
|
/* Read data until done or would cross a page boundary.
|
||||||
|
* We must write the address again when changing pages
|
||||||
|
* because the next page may be in a different device.
|
||||||
|
*/
|
||||||
|
while (offset < end) {
|
||||||
|
unsigned alen, len;
|
||||||
|
unsigned maxlen;
|
||||||
|
uchar addr[2];
|
||||||
|
|
||||||
|
blk_off = offset & 0xFF; /* block offset */
|
||||||
|
|
||||||
|
addr[0] = offset >> 8; /* block number */
|
||||||
|
addr[1] = blk_off; /* block offset */
|
||||||
|
alen = 2;
|
||||||
|
|
||||||
|
addr[0] |= dev_addr; /* insert device address */
|
||||||
|
|
||||||
|
len = end - offset;
|
||||||
|
|
||||||
|
maxlen = 0x100 - blk_off;
|
||||||
|
if (maxlen > I2C_RXTX_LEN)
|
||||||
|
maxlen = I2C_RXTX_LEN;
|
||||||
|
if (len > maxlen)
|
||||||
|
len = maxlen;
|
||||||
|
|
||||||
|
if (i2c_read (addr[0], offset, alen-1, buffer, len) != 0)
|
||||||
|
rcode = 1;
|
||||||
|
buffer += len;
|
||||||
|
offset += len;
|
||||||
|
}
|
||||||
|
|
||||||
|
return rcode;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
|
||||||
|
int usb_board_init(void)
|
||||||
|
{
|
||||||
|
char *act = getenv("usbact");
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if ((act == NULL || strcmp(act, "hostdev") == 0) &&
|
||||||
|
!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT))
|
||||||
|
/* enable power on USB socket */
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);
|
||||||
|
|
||||||
|
for (i=0; i<1000; i++)
|
||||||
|
udelay(1000);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int usb_board_stop(void)
|
||||||
|
{
|
||||||
|
/* disable power on USB socket */
|
||||||
|
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_USB_PWR_N);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int usb_board_init_fail(void)
|
||||||
|
{
|
||||||
|
usb_board_stop();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
|
||||||
|
|
||||||
|
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
|
||||||
|
void ft_board_setup(void *blob, bd_t *bd)
|
||||||
|
{
|
||||||
|
u32 val[4];
|
||||||
|
int rc;
|
||||||
|
|
||||||
|
ft_cpu_setup(blob, bd);
|
||||||
|
|
||||||
|
/* Fixup NOR mapping */
|
||||||
|
val[0] = 0; /* chip select number */
|
||||||
|
val[1] = 0; /* always 0 */
|
||||||
|
val[2] = gd->bd->bi_flashstart;
|
||||||
|
val[3] = gd->bd->bi_flashsize;
|
||||||
|
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
|
||||||
|
val, sizeof(val), 1);
|
||||||
|
if (rc)
|
||||||
|
printf("Unable to update property NOR mapping, err=%s\n",
|
||||||
|
fdt_strerror(rc));
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
|
154
board/esd/pmc440/pmc440.h
Normal file
154
board/esd/pmc440/pmc440.h
Normal file
|
@ -0,0 +1,154 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __PMC440_H__
|
||||||
|
#define __PMC440_H__
|
||||||
|
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* GPIOs
|
||||||
|
*/
|
||||||
|
#define GPIO1_INTA_FAKE (0x80000000 >> (45-32)) /* GPIO45 OD */
|
||||||
|
#define GPIO1_NONMONARCH (0x80000000 >> (63-32)) /* GPIO63 I */
|
||||||
|
#define GPIO1_PPC_EREADY (0x80000000 >> (62-32)) /* GPIO62 I/O */
|
||||||
|
#define GPIO1_M66EN (0x80000000 >> (61-32)) /* GPIO61 I */
|
||||||
|
#define GPIO1_POST_N (0x80000000 >> (60-32)) /* GPIO60 O */
|
||||||
|
#define GPIO1_IOEN_N (0x80000000 >> (50-32)) /* GPIO50 O */
|
||||||
|
#define GPIO1_HWID_MASK (0xf0000000 >> (56-32)) /* GPIO56..59 I */
|
||||||
|
|
||||||
|
#define GPIO1_USB_PWR_N (0x80000000 >> (32-32)) /* GPIO32 I */
|
||||||
|
#define GPIO0_LED_RUN_N (0x80000000 >> 30) /* GPIO30 O */
|
||||||
|
#define GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO23 O */
|
||||||
|
#define GPIO0_USB_ID (0x80000000 >> 21) /* GPIO21 I */
|
||||||
|
#define GPIO0_USB_PRSNT (0x80000000 >> 20) /* GPIO20 I */
|
||||||
|
#define GPIO0_SELF_RST (0x80000000 >> 6) /* GPIO6 OD */
|
||||||
|
|
||||||
|
/* FPGA programming pin configuration */
|
||||||
|
#define GPIO1_FPGA_PRG (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
|
||||||
|
#define GPIO1_FPGA_CLK (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output) */
|
||||||
|
#define GPIO1_FPGA_DATA (0x80000000 >> (52-32)) /* FPGA data pin (ppc output) */
|
||||||
|
#define GPIO1_FPGA_DONE (0x80000000 >> (55-32)) /* FPGA done pin (ppc input) */
|
||||||
|
#define GPIO1_FPGA_INIT (0x80000000 >> (54-32)) /* FPGA init pin (ppc input) */
|
||||||
|
#define GPIO0_FPGA_FORCEINIT (0x80000000 >> 27) /* low: force INIT# low */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* FPGA interface
|
||||||
|
*/
|
||||||
|
#define FPGA_BA CFG_FPGA_BASE0
|
||||||
|
#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
|
||||||
|
#define FPGA_IN32(p) in_be32((void*)(p))
|
||||||
|
#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
|
||||||
|
#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
|
||||||
|
|
||||||
|
struct pmc440_fifo_s {
|
||||||
|
u32 data;
|
||||||
|
u32 ctrl;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* fifo ctrl register */
|
||||||
|
#define FIFO_IE (1 << 15)
|
||||||
|
#define FIFO_OVERFLOW (1 << 10)
|
||||||
|
#define FIFO_EMPTY (1 << 9)
|
||||||
|
#define FIFO_FULL (1 << 8)
|
||||||
|
#define FIFO_LEVEL_MASK 0x000000ff
|
||||||
|
|
||||||
|
#define FIFO_COUNT 4
|
||||||
|
|
||||||
|
struct pmc440_fpga_s {
|
||||||
|
u32 ctrla;
|
||||||
|
u32 status;
|
||||||
|
u32 ctrlb;
|
||||||
|
u32 pad1[0x40 / sizeof(u32) - 3];
|
||||||
|
u32 irig_time; /* offset: 0x0040 */
|
||||||
|
u32 irig_tod;
|
||||||
|
u32 irig_cf;
|
||||||
|
u32 pad2;
|
||||||
|
u32 irig_rx_time; /* offset: 0x0050 */
|
||||||
|
u32 pad3[3];
|
||||||
|
u32 hostctrl; /* offset: 0x0060 */
|
||||||
|
u32 pad4[0x20 / sizeof(u32) - 1];
|
||||||
|
struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef struct pmc440_fpga_s pmc440_fpga_t;
|
||||||
|
|
||||||
|
/* ctrl register */
|
||||||
|
#define CTRL_HOST_IE (1 << 8)
|
||||||
|
|
||||||
|
/* outputs */
|
||||||
|
#define RESET_EN (1 << 31)
|
||||||
|
#define CLOCK_EN (1 << 30)
|
||||||
|
#define RESET_OUT (1 << 19)
|
||||||
|
#define CLOCK_OUT (1 << 22)
|
||||||
|
#define RESET_OUT (1 << 19)
|
||||||
|
#define IRIGB_R_OUT (1 << 14)
|
||||||
|
|
||||||
|
|
||||||
|
/* status register */
|
||||||
|
#define STATUS_VERSION_SHIFT 24
|
||||||
|
#define STATUS_VERSION_MASK 0xff000000
|
||||||
|
#define STATUS_HWREV_SHIFT 20
|
||||||
|
#define STATUS_HWREV_MASK 0x00f00000
|
||||||
|
|
||||||
|
#define STATUS_CAN_ISF (1 << 11)
|
||||||
|
#define STATUS_CSTM_ISF (1 << 10)
|
||||||
|
#define STATUS_FIFO_ISF (1 << 9)
|
||||||
|
#define STATUS_HOST_ISF (1 << 8)
|
||||||
|
|
||||||
|
|
||||||
|
/* inputs */
|
||||||
|
#define RESET_IN (1 << 0)
|
||||||
|
#define CLOCK_IN (1 << 1)
|
||||||
|
#define IRIGB_R_IN (1 << 5)
|
||||||
|
|
||||||
|
|
||||||
|
/* hostctrl register */
|
||||||
|
#define HOSTCTRL_PMCRSTOUT_GATE (1 << 17)
|
||||||
|
#define HOSTCTRL_PMCRSTOUT_FLAG (1 << 16)
|
||||||
|
#define HOSTCTRL_CSTM1IE_GATE (1 << 7)
|
||||||
|
#define HOSTCTRL_CSTM1IW_FLAG (1 << 6)
|
||||||
|
#define HOSTCTRL_CSTM0IE_GATE (1 << 5)
|
||||||
|
#define HOSTCTRL_CSTM0IW_FLAG (1 << 4)
|
||||||
|
#define HOSTCTRL_FIFOIE_GATE (1 << 3)
|
||||||
|
#define HOSTCTRL_FIFOIE_FLAG (1 << 2)
|
||||||
|
#define HOSTCTRL_HCINT_GATE (1 << 1)
|
||||||
|
#define HOSTCTRL_HCINT_FLAG (1 << 0)
|
||||||
|
|
||||||
|
#define NGCC_CTRL_BASE (CFG_FPGA_BASE0 + 0x80000)
|
||||||
|
#define NGCC_CTRL_FPGARST_N (1 << 2)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* FPGA to PPC interrupt
|
||||||
|
*/
|
||||||
|
#define IRQ0_FPGA (32+28) /* UIC1 - FPGA internal */
|
||||||
|
#define IRQ1_FPGA (32+30) /* UIC1 - custom module */
|
||||||
|
#define IRQ2_FPGA (64+ 3) /* UIC2 - custom module / CAN */
|
||||||
|
#define IRQ_ETH0 (64+ 4) /* UIC2 */
|
||||||
|
#define IRQ_ETH1 ( 27) /* UIC0 */
|
||||||
|
#define IRQ_RTC (64+ 0) /* UIC2 */
|
||||||
|
#define IRQ_PCIA (64+ 1) /* UIC2 */
|
||||||
|
#define IRQ_PCIB (32+18) /* UIC1 */
|
||||||
|
#define IRQ_PCIC (32+19) /* UIC1 */
|
||||||
|
#define IRQ_PCID (32+20) /* UIC1 */
|
||||||
|
|
||||||
|
#endif /* __PMC440_H__ */
|
442
board/esd/pmc440/sdram.c
Normal file
442
board/esd/pmc440/sdram.c
Normal file
|
@ -0,0 +1,442 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||||
|
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||||
|
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||||
|
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||||
|
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||||
|
*
|
||||||
|
* (C) Copyright 2006-2007
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* define DEBUG for debug output */
|
||||||
|
#undef DEBUG
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <ppc440.h>
|
||||||
|
|
||||||
|
#include "sdram.h"
|
||||||
|
|
||||||
|
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
|
||||||
|
defined(CONFIG_DDR_DATA_EYE)
|
||||||
|
/*-----------------------------------------------------------------------------+
|
||||||
|
* wait_for_dlllock.
|
||||||
|
+----------------------------------------------------------------------------*/
|
||||||
|
static int wait_for_dlllock(void)
|
||||||
|
{
|
||||||
|
unsigned long val;
|
||||||
|
int wait = 0;
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Wait for the DCC master delay line to finish calibration
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_17);
|
||||||
|
val = DDR0_17_DLLLOCKREG_UNLOCKED;
|
||||||
|
|
||||||
|
while (wait != 0xffff) {
|
||||||
|
val = mfdcr(ddrcfgd);
|
||||||
|
if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
|
||||||
|
/* dlllockreg bit on */
|
||||||
|
return 0;
|
||||||
|
else
|
||||||
|
wait++;
|
||||||
|
}
|
||||||
|
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
|
||||||
|
debug("Waiting for dlllockreg bit to raise\n");
|
||||||
|
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_DDR_DATA_EYE)
|
||||||
|
/*-----------------------------------------------------------------------------+
|
||||||
|
* wait_for_dram_init_complete.
|
||||||
|
+----------------------------------------------------------------------------*/
|
||||||
|
int wait_for_dram_init_complete(void)
|
||||||
|
{
|
||||||
|
unsigned long val;
|
||||||
|
int wait = 0;
|
||||||
|
|
||||||
|
/* --------------------------------------------------------------+
|
||||||
|
* Wait for 'DRAM initialization complete' bit in status register
|
||||||
|
* -------------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_00);
|
||||||
|
|
||||||
|
while (wait != 0xffff) {
|
||||||
|
val = mfdcr(ddrcfgd);
|
||||||
|
if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
|
||||||
|
/* 'DRAM initialization complete' bit */
|
||||||
|
return 0;
|
||||||
|
else
|
||||||
|
wait++;
|
||||||
|
}
|
||||||
|
|
||||||
|
debug("DRAM initialization complete bit in status register did not rise\n");
|
||||||
|
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define NUM_TRIES 64
|
||||||
|
#define NUM_READS 10
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------+
|
||||||
|
* denali_core_search_data_eye.
|
||||||
|
+----------------------------------------------------------------------------*/
|
||||||
|
void denali_core_search_data_eye(unsigned long memory_size)
|
||||||
|
{
|
||||||
|
int k, j;
|
||||||
|
u32 val;
|
||||||
|
u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
|
||||||
|
u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
|
||||||
|
u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
|
||||||
|
u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
|
||||||
|
volatile u32 *ram_pointer;
|
||||||
|
u32 test[NUM_TRIES] = {
|
||||||
|
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
|
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
|
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||||
|
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||||
|
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||||
|
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||||
|
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||||
|
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||||
|
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||||
|
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||||
|
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||||
|
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||||
|
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||||
|
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||||
|
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
|
||||||
|
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
|
||||||
|
|
||||||
|
ram_pointer = (volatile u32 *)(CFG_SDRAM_BASE);
|
||||||
|
|
||||||
|
for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
|
||||||
|
/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* De-assert 'start' parameter.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_02);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Set 'wr_dqs_shift'
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_09);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||||
|
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
dqs_out_shift = wr_dqs_shift + 32;
|
||||||
|
mtdcr(ddrcfga, DDR0_22);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||||
|
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
|
||||||
|
passing_cases = 0;
|
||||||
|
|
||||||
|
for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
|
||||||
|
/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Set 'dll_dqs_delay_X'.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
/* dll_dqs_delay_0 */
|
||||||
|
mtdcr(ddrcfga, DDR0_17);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||||
|
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||||
|
mtdcr(ddrcfga, DDR0_18);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||||
|
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||||
|
mtdcr(ddrcfga, DDR0_19);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||||
|
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
|
||||||
|
ppcMsync();
|
||||||
|
ppcMbar();
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Assert 'start' parameter.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_02);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
|
||||||
|
ppcMsync();
|
||||||
|
ppcMbar();
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Wait for the DCC master delay line to finish calibration
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
if (wait_for_dlllock() != 0) {
|
||||||
|
printf("dlllock did not occur !!!\n");
|
||||||
|
printf("denali_core_search_data_eye!!!\n");
|
||||||
|
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||||
|
wr_dqs_shift, dll_dqs_delay_X);
|
||||||
|
hang();
|
||||||
|
}
|
||||||
|
ppcMsync();
|
||||||
|
ppcMbar();
|
||||||
|
|
||||||
|
if (wait_for_dram_init_complete() != 0) {
|
||||||
|
printf("dram init complete did not occur !!!\n");
|
||||||
|
printf("denali_core_search_data_eye!!!\n");
|
||||||
|
printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
|
||||||
|
wr_dqs_shift, dll_dqs_delay_X);
|
||||||
|
hang();
|
||||||
|
}
|
||||||
|
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||||
|
|
||||||
|
/* write values */
|
||||||
|
for (j=0; j<NUM_TRIES; j++) {
|
||||||
|
ram_pointer[j] = test[j];
|
||||||
|
|
||||||
|
/* clear any cache at ram location */
|
||||||
|
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||||
|
}
|
||||||
|
|
||||||
|
/* read values back */
|
||||||
|
for (j=0; j<NUM_TRIES; j++) {
|
||||||
|
for (k=0; k<NUM_READS; k++) {
|
||||||
|
/* clear any cache at ram location */
|
||||||
|
__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
|
||||||
|
|
||||||
|
if (ram_pointer[j] != test[j])
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* read error */
|
||||||
|
if (k != NUM_READS)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* See if the dll_dqs_delay_X value passed.*/
|
||||||
|
if (j < NUM_TRIES) {
|
||||||
|
/* Failed */
|
||||||
|
passing_cases = 0;
|
||||||
|
/* break; */
|
||||||
|
} else {
|
||||||
|
/* Passed */
|
||||||
|
if (passing_cases == 0)
|
||||||
|
dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
|
||||||
|
passing_cases++;
|
||||||
|
if (passing_cases >= max_passing_cases) {
|
||||||
|
max_passing_cases = passing_cases;
|
||||||
|
wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
|
||||||
|
dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
|
||||||
|
dll_dqs_delay_X_end_window = dll_dqs_delay_X;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* De-assert 'start' parameter.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_02);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
|
||||||
|
} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
|
||||||
|
|
||||||
|
} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Largest passing window is now detected.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Compute dll_dqs_delay_X value */
|
||||||
|
dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
|
||||||
|
wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
|
||||||
|
|
||||||
|
debug("DQS calibration - Window detected:\n");
|
||||||
|
debug("max_passing_cases = %d\n", max_passing_cases);
|
||||||
|
debug("wr_dqs_shift = %d\n", wr_dqs_shift);
|
||||||
|
debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
|
||||||
|
debug("dll_dqs_delay_X window = %d - %d\n",
|
||||||
|
dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* De-assert 'start' parameter.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_02);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Set 'wr_dqs_shift'
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_09);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
|
||||||
|
| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
debug("DDR0_09=0x%08lx\n", val);
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Set 'dqs_out_shift' = wr_dqs_shift + 32
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
dqs_out_shift = wr_dqs_shift + 32;
|
||||||
|
mtdcr(ddrcfga, DDR0_22);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
|
||||||
|
| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
debug("DDR0_22=0x%08lx\n", val);
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Set 'dll_dqs_delay_X'.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
/* dll_dqs_delay_0 */
|
||||||
|
mtdcr(ddrcfga, DDR0_17);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
|
||||||
|
| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
debug("DDR0_17=0x%08lx\n", val);
|
||||||
|
|
||||||
|
/* dll_dqs_delay_1 to dll_dqs_delay_4 */
|
||||||
|
mtdcr(ddrcfga, DDR0_18);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
|
||||||
|
| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
debug("DDR0_18=0x%08lx\n", val);
|
||||||
|
|
||||||
|
/* dll_dqs_delay_5 to dll_dqs_delay_8 */
|
||||||
|
mtdcr(ddrcfga, DDR0_19);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
|
||||||
|
| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
|
||||||
|
| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
debug("DDR0_19=0x%08lx\n", val);
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Assert 'start' parameter.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
mtdcr(ddrcfga, DDR0_02);
|
||||||
|
val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
|
||||||
|
mtdcr(ddrcfgd, val);
|
||||||
|
|
||||||
|
ppcMsync();
|
||||||
|
ppcMbar();
|
||||||
|
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Wait for the DCC master delay line to finish calibration
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
if (wait_for_dlllock() != 0) {
|
||||||
|
printf("dlllock did not occur !!!\n");
|
||||||
|
hang();
|
||||||
|
}
|
||||||
|
ppcMsync();
|
||||||
|
ppcMbar();
|
||||||
|
|
||||||
|
if (wait_for_dram_init_complete() != 0) {
|
||||||
|
printf("dram init complete did not occur !!!\n");
|
||||||
|
hang();
|
||||||
|
}
|
||||||
|
udelay(100); /* wait 100us to ensure init is really completed !!! */
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_DDR_DATA_EYE */
|
||||||
|
|
||||||
|
#if defined(CONFIG_NAND_SPL)
|
||||||
|
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
|
||||||
|
* for the 4k NAND boot image so define bus_frequency to 133MHz here
|
||||||
|
* which is save for the refresh counter setup.
|
||||||
|
*/
|
||||||
|
#define get_bus_freq(val) 133000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
*
|
||||||
|
* initdram -- 440EPx's DDR controller is a DENALI Core
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
long int initdram (int board_type)
|
||||||
|
{
|
||||||
|
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||||
|
#if !defined(CONFIG_NAND_SPL)
|
||||||
|
ulong speed = get_bus_freq(0);
|
||||||
|
#else
|
||||||
|
ulong speed = 133333333; /* 133MHz is on the safe side */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
mtsdram(DDR0_02, 0x00000000);
|
||||||
|
|
||||||
|
mtsdram(DDR0_00, 0x0000190A);
|
||||||
|
mtsdram(DDR0_01, 0x01000000);
|
||||||
|
mtsdram(DDR0_03, 0x02030602);
|
||||||
|
mtsdram(DDR0_04, 0x0A020200);
|
||||||
|
mtsdram(DDR0_05, 0x02020308);
|
||||||
|
mtsdram(DDR0_06, 0x0102C812);
|
||||||
|
mtsdram(DDR0_07, 0x000D0100);
|
||||||
|
mtsdram(DDR0_08, 0x02430001);
|
||||||
|
mtsdram(DDR0_09, 0x00011D5F);
|
||||||
|
mtsdram(DDR0_10, 0x00000300);
|
||||||
|
mtsdram(DDR0_11, 0x0027C800);
|
||||||
|
mtsdram(DDR0_12, 0x00000003);
|
||||||
|
mtsdram(DDR0_14, 0x00000000);
|
||||||
|
mtsdram(DDR0_17, 0x19000000);
|
||||||
|
mtsdram(DDR0_18, 0x19191919);
|
||||||
|
mtsdram(DDR0_19, 0x19191919);
|
||||||
|
mtsdram(DDR0_20, 0x0B0B0B0B);
|
||||||
|
mtsdram(DDR0_21, 0x0B0B0B0B);
|
||||||
|
mtsdram(DDR0_22, 0x00267F0B);
|
||||||
|
mtsdram(DDR0_23, 0x00000000);
|
||||||
|
mtsdram(DDR0_24, 0x01010002);
|
||||||
|
if (speed > 133333334)
|
||||||
|
mtsdram(DDR0_26, 0x5B26050C);
|
||||||
|
else
|
||||||
|
mtsdram(DDR0_26, 0x5B260408);
|
||||||
|
mtsdram(DDR0_27, 0x0000682B);
|
||||||
|
mtsdram(DDR0_28, 0x00000000);
|
||||||
|
mtsdram(DDR0_31, 0x00000000);
|
||||||
|
mtsdram(DDR0_42, 0x01000006);
|
||||||
|
mtsdram(DDR0_43, 0x030A0200);
|
||||||
|
mtsdram(DDR0_44, 0x00000003);
|
||||||
|
mtsdram(DDR0_02, 0x00000001);
|
||||||
|
|
||||||
|
wait_for_dlllock();
|
||||||
|
#endif /* #ifndef CONFIG_NAND_U_BOOT */
|
||||||
|
|
||||||
|
#ifdef CONFIG_DDR_DATA_EYE
|
||||||
|
/* -----------------------------------------------------------+
|
||||||
|
* Perform data eye search if requested.
|
||||||
|
* ----------------------------------------------------------*/
|
||||||
|
denali_core_search_data_eye(CFG_MBYTES_SDRAM << 20);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return (CFG_MBYTES_SDRAM << 20);
|
||||||
|
}
|
505
board/esd/pmc440/sdram.h
Normal file
505
board/esd/pmc440/sdram.h
Normal file
|
@ -0,0 +1,505 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||||
|
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||||
|
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||||
|
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||||
|
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _SPD_SDRAM_DENALI_H_
|
||||||
|
#define _SPD_SDRAM_DENALI_H_
|
||||||
|
|
||||||
|
#define ppcMsync sync
|
||||||
|
#define ppcMbar eieio
|
||||||
|
|
||||||
|
/* General definitions */
|
||||||
|
#define MAX_SPD_BYTE 128 /* highest SPD byte # to read */
|
||||||
|
#define DENALI_REG_NUMBER 45 /* 45 Regs in PPC440EPx Denali Core */
|
||||||
|
#define SUPPORTED_DIMMS_NB 7 /* Number of supported DIMM modules types */
|
||||||
|
#define SDRAM_NONE 0 /* No DIMM detected in Slot */
|
||||||
|
#define MAXRANKS 2 /* 2 ranks maximum */
|
||||||
|
|
||||||
|
/* Supported PLB Frequencies */
|
||||||
|
#define PLB_FREQ_133MHZ 133333333
|
||||||
|
#define PLB_FREQ_152MHZ 152000000
|
||||||
|
#define PLB_FREQ_160MHZ 160000000
|
||||||
|
#define PLB_FREQ_166MHZ 166666666
|
||||||
|
|
||||||
|
/* Denali Core Registers */
|
||||||
|
#define SDRAM_DCR_BASE 0x10
|
||||||
|
|
||||||
|
#define DDR_DCR_BASE 0x10
|
||||||
|
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||||
|
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------+
|
||||||
|
| Values for ddrcfga register - indirect addressing of these regs
|
||||||
|
+-----------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define DDR0_00 0x00
|
||||||
|
#define DDR0_00_INT_ACK_MASK 0x7F000000 /* Write only */
|
||||||
|
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||||
|
#define DDR0_00_INT_ACK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||||
|
#define DDR0_00_INT_ACK_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||||
|
/* Status */
|
||||||
|
#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */
|
||||||
|
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
|
||||||
|
#define DDR0_00_INT_STATUS_BIT0 0x00010000
|
||||||
|
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
|
||||||
|
#define DDR0_00_INT_STATUS_BIT1 0x00020000
|
||||||
|
/* Bit2. Single correctable ECC event detected */
|
||||||
|
#define DDR0_00_INT_STATUS_BIT2 0x00040000
|
||||||
|
/* Bit3. Multiple correctable ECC events detected. */
|
||||||
|
#define DDR0_00_INT_STATUS_BIT3 0x00080000
|
||||||
|
/* Bit4. Single uncorrectable ECC event detected. */
|
||||||
|
#define DDR0_00_INT_STATUS_BIT4 0x00100000
|
||||||
|
/* Bit5. Multiple uncorrectable ECC events detected. */
|
||||||
|
#define DDR0_00_INT_STATUS_BIT5 0x00200000
|
||||||
|
/* Bit6. DRAM initialization complete. */
|
||||||
|
#define DDR0_00_INT_STATUS_BIT6 0x00400000
|
||||||
|
/* Bit7. Logical OR of all lower bits. */
|
||||||
|
#define DDR0_00_INT_STATUS_BIT7 0x00800000
|
||||||
|
|
||||||
|
#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||||
|
#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||||
|
#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00
|
||||||
|
#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||||
|
#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||||
|
#define DDR0_00_DLL_START_POINT_MASK 0x0000007F
|
||||||
|
#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||||
|
#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||||
|
|
||||||
|
|
||||||
|
#define DDR0_01 0x01
|
||||||
|
#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000
|
||||||
|
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||||
|
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||||
|
#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000
|
||||||
|
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||||
|
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||||
|
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */
|
||||||
|
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||||
|
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||||
|
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||||
|
#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||||
|
#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||||
|
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||||
|
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||||
|
|
||||||
|
#define DDR0_02 0x02
|
||||||
|
#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */
|
||||||
|
#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24)
|
||||||
|
#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2)
|
||||||
|
#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */
|
||||||
|
#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||||
|
#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||||
|
#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */
|
||||||
|
#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||||
|
#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||||
|
#define DDR0_02_START_MASK 0x00000001
|
||||||
|
#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||||
|
#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||||
|
#define DDR0_02_START_OFF 0x00000000
|
||||||
|
#define DDR0_02_START_ON 0x00000001
|
||||||
|
|
||||||
|
#define DDR0_03 0x03
|
||||||
|
#define DDR0_03_BSTLEN_MASK 0x07000000
|
||||||
|
#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||||
|
#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||||
|
#define DDR0_03_CASLAT_MASK 0x00070000
|
||||||
|
#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||||
|
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||||
|
#define DDR0_03_CASLAT_LIN_MASK 0x00000F00
|
||||||
|
#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||||
|
#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||||
|
#define DDR0_03_INITAREF_MASK 0x0000000F
|
||||||
|
#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||||
|
#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||||
|
|
||||||
|
#define DDR0_04 0x04
|
||||||
|
#define DDR0_04_TRC_MASK 0x1F000000
|
||||||
|
#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||||
|
#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||||
|
#define DDR0_04_TRRD_MASK 0x00070000
|
||||||
|
#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||||
|
#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||||
|
#define DDR0_04_TRTP_MASK 0x00000700
|
||||||
|
#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||||
|
#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||||
|
|
||||||
|
#define DDR0_05 0x05
|
||||||
|
#define DDR0_05_TMRD_MASK 0x1F000000
|
||||||
|
#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||||
|
#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||||
|
#define DDR0_05_TEMRS_MASK 0x00070000
|
||||||
|
#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||||
|
#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||||
|
#define DDR0_05_TRP_MASK 0x00000F00
|
||||||
|
#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8)
|
||||||
|
#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF)
|
||||||
|
#define DDR0_05_TRAS_MIN_MASK 0x000000FF
|
||||||
|
#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||||
|
#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||||
|
|
||||||
|
#define DDR0_06 0x06
|
||||||
|
#define DDR0_06_WRITEINTERP_MASK 0x01000000
|
||||||
|
#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||||
|
#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||||
|
#define DDR0_06_TWTR_MASK 0x00070000
|
||||||
|
#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16)
|
||||||
|
#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||||
|
#define DDR0_06_TDLL_MASK 0x0000FF00
|
||||||
|
#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||||
|
#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||||
|
#define DDR0_06_TRFC_MASK 0x0000007F
|
||||||
|
#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||||
|
#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||||
|
|
||||||
|
#define DDR0_07 0x07
|
||||||
|
#define DDR0_07_NO_CMD_INIT_MASK 0x01000000
|
||||||
|
#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||||
|
#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||||
|
#define DDR0_07_TFAW_MASK 0x001F0000
|
||||||
|
#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
|
||||||
|
#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F)
|
||||||
|
#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100
|
||||||
|
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||||
|
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||||
|
#define DDR0_07_AREFRESH_MASK 0x00000001
|
||||||
|
#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||||
|
#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||||
|
|
||||||
|
#define DDR0_08 0x08
|
||||||
|
#define DDR0_08_WRLAT_MASK 0x07000000
|
||||||
|
#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||||
|
#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||||
|
#define DDR0_08_TCPD_MASK 0x00FF0000
|
||||||
|
#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||||
|
#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||||
|
#define DDR0_08_DQS_N_EN_MASK 0x00000100
|
||||||
|
#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||||
|
#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||||
|
#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001
|
||||||
|
#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||||
|
#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||||
|
|
||||||
|
#define DDR0_09 0x09
|
||||||
|
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000
|
||||||
|
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
|
||||||
|
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||||
|
#define DDR0_09_RTT_0_MASK 0x00030000
|
||||||
|
#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||||
|
#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||||
|
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00
|
||||||
|
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||||
|
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||||
|
#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F
|
||||||
|
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||||
|
#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||||
|
|
||||||
|
#define DDR0_10 0x0A
|
||||||
|
#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */
|
||||||
|
#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||||
|
#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||||
|
#define DDR0_10_CS_MAP_MASK 0x00000300
|
||||||
|
#define DDR0_10_CS_MAP_NO_MEM 0x00000000
|
||||||
|
#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100
|
||||||
|
#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200
|
||||||
|
#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||||
|
#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||||
|
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F
|
||||||
|
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
|
||||||
|
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)
|
||||||
|
|
||||||
|
#define DDR0_11 0x0B
|
||||||
|
#define DDR0_11_SREFRESH_MASK 0x01000000
|
||||||
|
#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||||
|
#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
|
||||||
|
#define DDR0_11_TXSNR_MASK 0x00FF0000
|
||||||
|
#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||||
|
#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||||
|
#define DDR0_11_TXSR_MASK 0x0000FF00
|
||||||
|
#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||||
|
#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||||
|
|
||||||
|
#define DDR0_12 0x0C
|
||||||
|
#define DDR0_12_TCKE_MASK 0x0000007
|
||||||
|
#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
|
||||||
|
#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7)
|
||||||
|
|
||||||
|
#define DDR0_13 0x0D
|
||||||
|
|
||||||
|
#define DDR0_14 0x0E
|
||||||
|
#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000
|
||||||
|
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24)
|
||||||
|
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1)
|
||||||
|
#define DDR0_14_REDUC_MASK 0x00010000
|
||||||
|
#define DDR0_14_REDUC_64BITS 0x00000000
|
||||||
|
#define DDR0_14_REDUC_32BITS 0x00010000
|
||||||
|
#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||||
|
#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||||
|
#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100
|
||||||
|
#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
|
||||||
|
#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
|
||||||
|
|
||||||
|
#define DDR0_15 0x0F
|
||||||
|
|
||||||
|
#define DDR0_16 0x10
|
||||||
|
|
||||||
|
#define DDR0_17 0x11
|
||||||
|
#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000
|
||||||
|
#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||||
|
#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||||
|
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||||
|
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||||
|
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||||
|
#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16)
|
||||||
|
#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1)
|
||||||
|
#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */
|
||||||
|
#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||||
|
#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||||
|
|
||||||
|
#define DDR0_18 0x12
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||||
|
#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||||
|
|
||||||
|
#define DDR0_19 0x13
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||||
|
#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||||
|
|
||||||
|
#define DDR0_20 0x14
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||||
|
#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||||
|
|
||||||
|
#define DDR0_21 0x15
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24)
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F)
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||||
|
#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||||
|
|
||||||
|
#define DDR0_22 0x16
|
||||||
|
/* ECC */
|
||||||
|
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||||
|
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */
|
||||||
|
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/
|
||||||
|
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */
|
||||||
|
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */
|
||||||
|
#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||||
|
#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||||
|
|
||||||
|
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000
|
||||||
|
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
|
||||||
|
#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F)
|
||||||
|
#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00
|
||||||
|
#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
|
||||||
|
#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
|
||||||
|
#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F
|
||||||
|
#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0)
|
||||||
|
#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F)
|
||||||
|
|
||||||
|
|
||||||
|
#define DDR0_23 0x17
|
||||||
|
#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000
|
||||||
|
#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||||
|
#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||||
|
#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */
|
||||||
|
#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16)
|
||||||
|
#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF)
|
||||||
|
#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */
|
||||||
|
#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8)
|
||||||
|
#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF)
|
||||||
|
#define DDR0_23_FWC_MASK 0x00000001 /* Write only */
|
||||||
|
#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||||
|
#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||||
|
|
||||||
|
#define DDR0_24 0x18
|
||||||
|
#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000
|
||||||
|
#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
|
||||||
|
#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3)
|
||||||
|
#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000
|
||||||
|
#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
|
||||||
|
#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3)
|
||||||
|
#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300
|
||||||
|
#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8)
|
||||||
|
#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3)
|
||||||
|
#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003
|
||||||
|
#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0)
|
||||||
|
#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3)
|
||||||
|
|
||||||
|
#define DDR0_25 0x19
|
||||||
|
#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */
|
||||||
|
#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||||
|
#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||||
|
#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */
|
||||||
|
#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||||
|
#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||||
|
|
||||||
|
#define DDR0_26 0x1A
|
||||||
|
#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000
|
||||||
|
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||||
|
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||||
|
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||||
|
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
||||||
|
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
||||||
|
|
||||||
|
#define DDR0_27 0x1B
|
||||||
|
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||||
|
#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||||
|
#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||||
|
#define DDR0_27_TINIT_MASK 0x0000FFFF
|
||||||
|
#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||||
|
#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||||
|
|
||||||
|
#define DDR0_28 0x1C
|
||||||
|
#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000
|
||||||
|
#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16)
|
||||||
|
#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF)
|
||||||
|
#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF
|
||||||
|
#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||||
|
#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||||
|
|
||||||
|
#define DDR0_29 0x1D
|
||||||
|
|
||||||
|
#define DDR0_30 0x1E
|
||||||
|
|
||||||
|
#define DDR0_31 0x1F
|
||||||
|
#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF
|
||||||
|
#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0)
|
||||||
|
#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF)
|
||||||
|
|
||||||
|
#define DDR0_32 0x20
|
||||||
|
#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||||
|
#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||||
|
#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||||
|
|
||||||
|
#define DDR0_33 0x21
|
||||||
|
#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */
|
||||||
|
#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||||
|
#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||||
|
|
||||||
|
#define DDR0_34 0x22
|
||||||
|
#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||||
|
#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||||
|
#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||||
|
|
||||||
|
#define DDR0_35 0x23
|
||||||
|
#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */
|
||||||
|
#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||||
|
#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||||
|
|
||||||
|
#define DDR0_36 0x24
|
||||||
|
#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||||
|
#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||||
|
#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||||
|
|
||||||
|
#define DDR0_37 0x25
|
||||||
|
#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||||
|
#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||||
|
#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||||
|
|
||||||
|
#define DDR0_38 0x26
|
||||||
|
#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */
|
||||||
|
#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||||
|
#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||||
|
|
||||||
|
#define DDR0_39 0x27
|
||||||
|
#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */
|
||||||
|
#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||||
|
#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||||
|
|
||||||
|
#define DDR0_40 0x28
|
||||||
|
#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||||
|
#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||||
|
#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||||
|
|
||||||
|
#define DDR0_41 0x29
|
||||||
|
#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */
|
||||||
|
#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0)
|
||||||
|
#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF)
|
||||||
|
|
||||||
|
#define DDR0_42 0x2A
|
||||||
|
#define DDR0_42_ADDR_PINS_MASK 0x07000000
|
||||||
|
#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||||
|
#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||||
|
#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F
|
||||||
|
#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0)
|
||||||
|
#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF)
|
||||||
|
|
||||||
|
#define DDR0_43 0x2B
|
||||||
|
#define DDR0_43_TWR_MASK 0x07000000
|
||||||
|
#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24)
|
||||||
|
#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7)
|
||||||
|
#define DDR0_43_APREBIT_MASK 0x000F0000
|
||||||
|
#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16)
|
||||||
|
#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF)
|
||||||
|
#define DDR0_43_COLUMN_SIZE_MASK 0x00000700
|
||||||
|
#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8)
|
||||||
|
#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7)
|
||||||
|
#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001
|
||||||
|
#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001
|
||||||
|
#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000
|
||||||
|
#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0)
|
||||||
|
#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1)
|
||||||
|
|
||||||
|
#define DDR0_44 0x2C
|
||||||
|
#define DDR0_44_TRCD_MASK 0x000000FF
|
||||||
|
#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
|
||||||
|
#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF)
|
||||||
|
|
||||||
|
#endif /* _SPD_SDRAM_DENALI_H_ */
|
137
board/esd/pmc440/u-boot-nand.lds
Normal file
137
board/esd/pmc440/u-boot-nand.lds
Normal file
|
@ -0,0 +1,137 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
OUTPUT_ARCH(powerpc)
|
||||||
|
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* Read-only sections, merged into text segment: */
|
||||||
|
. = + SIZEOF_HEADERS;
|
||||||
|
.interp : { *(.interp) }
|
||||||
|
.hash : { *(.hash) }
|
||||||
|
.dynsym : { *(.dynsym) }
|
||||||
|
.dynstr : { *(.dynstr) }
|
||||||
|
.rel.text : { *(.rel.text) }
|
||||||
|
.rela.text : { *(.rela.text) }
|
||||||
|
.rel.data : { *(.rel.data) }
|
||||||
|
.rela.data : { *(.rela.data) }
|
||||||
|
.rel.rodata : { *(.rel.rodata) }
|
||||||
|
.rela.rodata : { *(.rela.rodata) }
|
||||||
|
.rel.got : { *(.rel.got) }
|
||||||
|
.rela.got : { *(.rela.got) }
|
||||||
|
.rel.ctors : { *(.rel.ctors) }
|
||||||
|
.rela.ctors : { *(.rela.ctors) }
|
||||||
|
.rel.dtors : { *(.rel.dtors) }
|
||||||
|
.rela.dtors : { *(.rela.dtors) }
|
||||||
|
.rel.bss : { *(.rel.bss) }
|
||||||
|
.rela.bss : { *(.rela.bss) }
|
||||||
|
.rel.plt : { *(.rel.plt) }
|
||||||
|
.rela.plt : { *(.rela.plt) }
|
||||||
|
.init : { *(.init) }
|
||||||
|
.plt : { *(.plt) }
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
/* WARNING - the following is hand-optimized to fit within */
|
||||||
|
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||||
|
|
||||||
|
cpu/ppc4xx/start.o (.text)
|
||||||
|
|
||||||
|
/* Align to next NAND block */
|
||||||
|
. = ALIGN(0x4000);
|
||||||
|
common/environment.o (.ppcenv)
|
||||||
|
/* Keep some space here for redundant env and potential bad env blocks */
|
||||||
|
. = ALIGN(0x10000);
|
||||||
|
|
||||||
|
*(.text)
|
||||||
|
*(.fixup)
|
||||||
|
*(.got1)
|
||||||
|
}
|
||||||
|
_etext = .;
|
||||||
|
PROVIDE (etext = .);
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata1)
|
||||||
|
*(.rodata.str1.4)
|
||||||
|
}
|
||||||
|
.fini : { *(.fini) } =0
|
||||||
|
.ctors : { *(.ctors) }
|
||||||
|
.dtors : { *(.dtors) }
|
||||||
|
|
||||||
|
/* Read-write section, merged into data segment: */
|
||||||
|
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||||
|
_erotext = .;
|
||||||
|
PROVIDE (erotext = .);
|
||||||
|
.reloc :
|
||||||
|
{
|
||||||
|
*(.got)
|
||||||
|
_GOT2_TABLE_ = .;
|
||||||
|
*(.got2)
|
||||||
|
_FIXUP_TABLE_ = .;
|
||||||
|
*(.fixup)
|
||||||
|
}
|
||||||
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||||
|
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.data)
|
||||||
|
*(.data1)
|
||||||
|
*(.sdata)
|
||||||
|
*(.sdata2)
|
||||||
|
*(.dynamic)
|
||||||
|
CONSTRUCTORS
|
||||||
|
}
|
||||||
|
_edata = .;
|
||||||
|
PROVIDE (edata = .);
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
__u_boot_cmd_start = .;
|
||||||
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
__u_boot_cmd_end = .;
|
||||||
|
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
__start___ex_table = .;
|
||||||
|
__ex_table : { *(__ex_table) }
|
||||||
|
__stop___ex_table = .;
|
||||||
|
|
||||||
|
. = ALIGN(256);
|
||||||
|
__init_begin = .;
|
||||||
|
.text.init : { *(.text.init) }
|
||||||
|
.data.init : { *(.data.init) }
|
||||||
|
. = ALIGN(256);
|
||||||
|
__init_end = .;
|
||||||
|
|
||||||
|
__bss_start = .;
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
*(.sbss) *(.scommon)
|
||||||
|
*(.dynbss)
|
||||||
|
*(.bss)
|
||||||
|
*(COMMON)
|
||||||
|
}
|
||||||
|
|
||||||
|
_end = . ;
|
||||||
|
PROVIDE (end = .);
|
||||||
|
}
|
|
@ -28,13 +28,11 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/
|
||||||
SECTIONS
|
SECTIONS
|
||||||
{
|
{
|
||||||
.resetvec 0xFFFFFFFC :
|
.resetvec 0xFFFFFFFC :
|
||||||
/* .resetvec 0x01FFFFFC :*/
|
|
||||||
{
|
{
|
||||||
*(.resetvec)
|
*(.resetvec)
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
|
||||||
.bootpg 0xFFFFF000 :
|
.bootpg 0xFFFFF000 :
|
||||||
/* .bootpg 0x01FFF000 :*/
|
|
||||||
{
|
{
|
||||||
cpu/ppc4xx/start.o (.bootpg)
|
cpu/ppc4xx/start.o (.bootpg)
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
@ -69,20 +67,6 @@ SECTIONS
|
||||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||||
|
|
||||||
cpu/ppc4xx/start.o (.text)
|
cpu/ppc4xx/start.o (.text)
|
||||||
board/esd/cpci440/init.o (.text)
|
|
||||||
cpu/ppc4xx/kgdb.o (.text)
|
|
||||||
cpu/ppc4xx/traps.o (.text)
|
|
||||||
cpu/ppc4xx/interrupts.o (.text)
|
|
||||||
cpu/ppc4xx/4xx_uart.o (.text)
|
|
||||||
cpu/ppc4xx/cpu_init.o (.text)
|
|
||||||
cpu/ppc4xx/speed.o (.text)
|
|
||||||
common/dlmalloc.o (.text)
|
|
||||||
lib_generic/crc32.o (.text)
|
|
||||||
lib_ppc/extable.o (.text)
|
|
||||||
lib_generic/zlib.o (.text)
|
|
||||||
|
|
||||||
/* . = env_offset;*/
|
|
||||||
/* common/environment.o(.text)*/
|
|
||||||
|
|
||||||
*(.text)
|
*(.text)
|
||||||
*(.fixup)
|
*(.fixup)
|
||||||
|
@ -95,7 +79,6 @@ SECTIONS
|
||||||
*(.rodata)
|
*(.rodata)
|
||||||
*(.rodata1)
|
*(.rodata1)
|
||||||
*(.rodata.str1.4)
|
*(.rodata.str1.4)
|
||||||
*(.eh_frame)
|
|
||||||
}
|
}
|
||||||
.fini : { *(.fini) } =0
|
.fini : { *(.fini) } =0
|
||||||
.ctors : { *(.ctors) }
|
.ctors : { *(.ctors) }
|
||||||
|
@ -154,6 +137,9 @@ SECTIONS
|
||||||
*(.bss)
|
*(.bss)
|
||||||
*(COMMON)
|
*(COMMON)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
|
||||||
|
|
||||||
_end = . ;
|
_end = . ;
|
||||||
PROVIDE (end = .);
|
PROVIDE (end = .);
|
||||||
}
|
}
|
|
@ -22,6 +22,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
#include <asm/io.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
#include <malloc.h>
|
#include <malloc.h>
|
||||||
|
@ -112,11 +113,11 @@ int misc_init_f (void)
|
||||||
|
|
||||||
int misc_init_r (void)
|
int misc_init_r (void)
|
||||||
{
|
{
|
||||||
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
|
||||||
volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
|
||||||
volatile unsigned short *lcd_contrast =
|
unsigned short *lcd_contrast =
|
||||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
|
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
|
||||||
volatile unsigned short *lcd_backlight =
|
unsigned short *lcd_backlight =
|
||||||
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
|
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
|
||||||
unsigned char *dst;
|
unsigned char *dst;
|
||||||
ulong len = sizeof(fpgadata);
|
ulong len = sizeof(fpgadata);
|
||||||
|
@ -180,25 +181,37 @@ int misc_init_r (void)
|
||||||
/*
|
/*
|
||||||
* Reset FPGA via FPGA_INIT pin
|
* Reset FPGA via FPGA_INIT pin
|
||||||
*/
|
*/
|
||||||
out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
|
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
|
||||||
udelay(1000); /* wait 1ms */
|
udelay(1000); /* wait 1ms */
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
|
||||||
udelay(1000); /* wait 1ms */
|
udelay(1000); /* wait 1ms */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Reset external DUARTs
|
* Reset external DUARTs
|
||||||
*/
|
*/
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
|
||||||
udelay(10); /* wait 10us */
|
udelay(10); /* wait 10us */
|
||||||
out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
|
||||||
udelay(1000); /* wait 1ms */
|
udelay(1000); /* wait 1ms */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Set NAND-FLASH GPIO signals to default
|
||||||
|
*/
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup EEPROM write protection
|
||||||
|
*/
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||||
|
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Enable interrupts in exar duart mcr[3]
|
* Enable interrupts in exar duart mcr[3]
|
||||||
*/
|
*/
|
||||||
*duart0_mcr = 0x08;
|
out_8(duart0_mcr, 0x08);
|
||||||
*duart1_mcr = 0x08;
|
out_8(duart1_mcr, 0x08);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Init lcd interface and display logo
|
* Init lcd interface and display logo
|
||||||
|
@ -240,17 +253,23 @@ int misc_init_r (void)
|
||||||
/*
|
/*
|
||||||
* Set invert bit in small lcd controller
|
* Set invert bit in small lcd controller
|
||||||
*/
|
*/
|
||||||
*(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01;
|
out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
|
||||||
|
in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Set default contrast voltage on epson vga controller
|
* Set default contrast voltage on epson vga controller
|
||||||
*/
|
*/
|
||||||
*lcd_contrast = 0x4646;
|
out_be16(lcd_contrast, 0x4646);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Enable backlight
|
* Enable backlight
|
||||||
*/
|
*/
|
||||||
*lcd_backlight = 0xffff;
|
out_be16(lcd_backlight, 0xffff);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Enable external I2C bus
|
||||||
|
*/
|
||||||
|
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
|
||||||
|
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
@ -281,11 +300,6 @@ int checkboard (void)
|
||||||
|
|
||||||
putc ('\n');
|
putc ('\n');
|
||||||
|
|
||||||
/*
|
|
||||||
* Disable sleep mode in LXT971
|
|
||||||
*/
|
|
||||||
lxt971_no_sleep();
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -334,3 +348,86 @@ void ide_set_reset(int on)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_IDE_RESET */
|
#endif /* CONFIG_IDE_RESET */
|
||||||
|
|
||||||
|
#if defined(CONFIG_RESET_PHY_R)
|
||||||
|
void reset_phy(void)
|
||||||
|
{
|
||||||
|
#ifdef CONFIG_LXT971_NO_SLEEP
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Disable sleep mode in LXT971
|
||||||
|
*/
|
||||||
|
lxt971_no_sleep();
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CFG_EEPROM_WREN)
|
||||||
|
/* Input: <dev_addr> I2C address of EEPROM device to enable.
|
||||||
|
* <state> -1: deliver current state
|
||||||
|
* 0: disable write
|
||||||
|
* 1: enable write
|
||||||
|
* Returns: -1: wrong device address
|
||||||
|
* 0: dis-/en- able done
|
||||||
|
* 0/1: current state if <state> was -1.
|
||||||
|
*/
|
||||||
|
int eeprom_write_enable (unsigned dev_addr, int state)
|
||||||
|
{
|
||||||
|
if (CFG_I2C_EEPROM_ADDR != dev_addr) {
|
||||||
|
return -1;
|
||||||
|
} else {
|
||||||
|
switch (state) {
|
||||||
|
case 1:
|
||||||
|
/* Enable write access, clear bit GPIO0. */
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
|
||||||
|
state = 0;
|
||||||
|
break;
|
||||||
|
case 0:
|
||||||
|
/* Disable write access, set bit GPIO0. */
|
||||||
|
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
|
||||||
|
state = 0;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
/* Read current status back. */
|
||||||
|
state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return state;
|
||||||
|
}
|
||||||
|
|
||||||
|
int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
|
{
|
||||||
|
int query = argc == 1;
|
||||||
|
int state = 0;
|
||||||
|
|
||||||
|
if (query) {
|
||||||
|
/* Query write access state. */
|
||||||
|
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
|
||||||
|
if (state < 0) {
|
||||||
|
puts ("Query of write access state failed.\n");
|
||||||
|
} else {
|
||||||
|
printf ("Write access for device 0x%0x is %sabled.\n",
|
||||||
|
CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
|
||||||
|
state = 0;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
if ('0' == argv[1][0]) {
|
||||||
|
/* Disable write access. */
|
||||||
|
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
|
||||||
|
} else {
|
||||||
|
/* Enable write access. */
|
||||||
|
state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
|
||||||
|
}
|
||||||
|
if (state < 0) {
|
||||||
|
puts ("Setup of write access state failed.\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return state;
|
||||||
|
}
|
||||||
|
|
||||||
|
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
|
||||||
|
"eepwren - Enable / disable / query EEPROM write access\n",
|
||||||
|
NULL);
|
||||||
|
#endif /* #if defined(CFG_EEPROM_WREN) */
|
||||||
|
|
|
@ -21,24 +21,29 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
#include <libfdt.h>
|
||||||
#if defined(CONFIG_OF_FLAT_TREE)
|
#include <fdt_support.h>
|
||||||
#include <ft_build.h>
|
|
||||||
#include "cadmus.h"
|
#include "cadmus.h"
|
||||||
|
|
||||||
extern void ft_cpu_setup(void *blob, bd_t *bd);
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||||
|
|
||||||
static void cds_pci_fixup(void *blob)
|
static void cds_pci_fixup(void *blob)
|
||||||
{
|
{
|
||||||
int len;
|
int node, tmp[2];
|
||||||
u32 *map;
|
const char *path;
|
||||||
int slot;
|
int len, slot, i;
|
||||||
int i;
|
u32 *map = NULL;
|
||||||
|
|
||||||
map = ft_get_prop(blob, "/" OF_SOC "/pci@8000/interrupt-map", &len);
|
node = fdt_path_offset(blob, "/aliases");
|
||||||
|
tmp[0] = 0;
|
||||||
if (!map)
|
if (node >= 0) {
|
||||||
map = ft_get_prop(blob, "/" OF_PCI "/interrupt-map", &len);
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||||
|
if (path) {
|
||||||
|
node = fdt_path_offset(blob, path);
|
||||||
|
if (node >= 0) {
|
||||||
|
map = fdt_getprop_w(blob, node, "interrupt-map", &len);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
if (map) {
|
if (map) {
|
||||||
len /= sizeof(u32);
|
len /= sizeof(u32);
|
||||||
|
@ -50,33 +55,18 @@ static void cds_pci_fixup(void *blob)
|
||||||
* changes depending on the slot the carrier card is in.
|
* changes depending on the slot the carrier card is in.
|
||||||
*/
|
*/
|
||||||
map[3] = ((map[3] + slot - 2) % 4) + 1;
|
map[3] = ((map[3] + slot - 2) % 4) + 1;
|
||||||
|
|
||||||
map+=7;
|
map+=7;
|
||||||
}
|
}
|
||||||
} else {
|
|
||||||
printf("*** Warning - No PCI node found\n");
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
|
||||||
void
|
void
|
||||||
ft_board_setup(void *blob, bd_t *bd)
|
ft_board_setup(void *blob, bd_t *bd)
|
||||||
{
|
{
|
||||||
u32 *p;
|
ft_cpu_setup(blob, bd);
|
||||||
int len;
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
#ifdef CONFIG_PCI
|
||||||
ft_pci_setup(blob, bd);
|
ft_pci_setup(blob, bd);
|
||||||
#endif
|
|
||||||
ft_cpu_setup(blob, bd);
|
|
||||||
|
|
||||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
|
||||||
if (p != NULL) {
|
|
||||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
|
||||||
*p = cpu_to_be32(bd->bi_memsize);
|
|
||||||
}
|
|
||||||
|
|
||||||
cds_pci_fixup(blob);
|
cds_pci_fixup(blob);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
|
@ -30,11 +30,8 @@
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/immap_85xx.h>
|
#include <asm/immap_85xx.h>
|
||||||
#include <spd.h>
|
#include <spd.h>
|
||||||
|
#include <libfdt.h>
|
||||||
#if defined(CONFIG_OF_FLAT_TREE)
|
#include <fdt_support.h>
|
||||||
#include <ft_build.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||||
|
@ -77,13 +74,12 @@ initdram(int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
extern long spd_sdram (void);
|
extern long spd_sdram (void);
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
puts("Initializing\n");
|
puts("Initializing\n");
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_DLL)
|
#if defined(CONFIG_DDR_DLL)
|
||||||
{
|
{
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
uint temp_ddrdll = 0;
|
uint temp_ddrdll = 0;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -125,9 +121,8 @@ initdram(int board_type)
|
||||||
void
|
void
|
||||||
local_bus_init(void)
|
local_bus_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
@ -186,8 +181,7 @@ local_bus_init(void)
|
||||||
void
|
void
|
||||||
sdram_init(void)
|
sdram_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
|
|
||||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
||||||
|
|
||||||
puts(" SDRAM: ");
|
puts(" SDRAM: ");
|
||||||
|
@ -282,8 +276,7 @@ int testdram (void)
|
||||||
long int fixed_sdram (void)
|
long int fixed_sdram (void)
|
||||||
{
|
{
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
|
||||||
|
|
||||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||||||
|
@ -331,22 +324,25 @@ pci_init_board(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||||
void
|
void
|
||||||
ft_board_setup(void *blob, bd_t *bd)
|
ft_board_setup(void *blob, bd_t *bd)
|
||||||
{
|
{
|
||||||
u32 *p;
|
int node, tmp[2];
|
||||||
int len;
|
const char *path;
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
ft_pci_setup(blob, bd);
|
|
||||||
#endif
|
|
||||||
ft_cpu_setup(blob, bd);
|
ft_cpu_setup(blob, bd);
|
||||||
|
|
||||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
node = fdt_path_offset(blob, "/aliases");
|
||||||
if (p != NULL) {
|
tmp[0] = 0;
|
||||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
if (node >= 0) {
|
||||||
*p = cpu_to_be32(bd->bi_memsize);
|
#ifdef CONFIG_PCI
|
||||||
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = hose.last_busno - hose.first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
|
@ -35,7 +35,7 @@ SECTIONS
|
||||||
.bootpg 0xFFFFF000 :
|
.bootpg 0xFFFFF000 :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.bootpg)
|
cpu/mpc85xx/start.o (.bootpg)
|
||||||
board/mpc8540ads/init.o (.bootpg)
|
board/freescale/mpc8540ads/init.o (.bootpg)
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
|
||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
|
@ -65,7 +65,7 @@ SECTIONS
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.text)
|
cpu/mpc85xx/start.o (.text)
|
||||||
board/mpc8540ads/init.o (.text)
|
board/freescale/mpc8540ads/init.o (.text)
|
||||||
cpu/mpc85xx/traps.o (.text)
|
cpu/mpc85xx/traps.o (.text)
|
||||||
cpu/mpc85xx/interrupts.o (.text)
|
cpu/mpc85xx/interrupts.o (.text)
|
||||||
cpu/mpc85xx/cpu_init.o (.text)
|
cpu/mpc85xx/cpu_init.o (.text)
|
|
@ -28,6 +28,8 @@
|
||||||
#include <asm/immap_85xx.h>
|
#include <asm/immap_85xx.h>
|
||||||
#include <ioports.h>
|
#include <ioports.h>
|
||||||
#include <spd.h>
|
#include <spd.h>
|
||||||
|
#include <libfdt.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
|
|
||||||
#include "../common/cadmus.h"
|
#include "../common/cadmus.h"
|
||||||
#include "../common/eeprom.h"
|
#include "../common/eeprom.h"
|
||||||
|
@ -203,8 +205,7 @@ int board_early_init_f (void)
|
||||||
|
|
||||||
int checkboard (void)
|
int checkboard (void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
|
|
||||||
/* PCI slot in USER bits CSR[6:7] by convention. */
|
/* PCI slot in USER bits CSR[6:7] by convention. */
|
||||||
uint pci_slot = get_pci_slot ();
|
uint pci_slot = get_pci_slot ();
|
||||||
|
@ -250,7 +251,6 @@ long int
|
||||||
initdram(int board_type)
|
initdram(int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
puts("Initializing\n");
|
puts("Initializing\n");
|
||||||
|
|
||||||
|
@ -263,7 +263,7 @@ initdram(int board_type)
|
||||||
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
||||||
*/
|
*/
|
||||||
|
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
|
|
||||||
gur->ddrdllcr = 0x81000000;
|
gur->ddrdllcr = 0x81000000;
|
||||||
asm("sync;isync;msync");
|
asm("sync;isync;msync");
|
||||||
|
@ -293,9 +293,8 @@ initdram(int board_type)
|
||||||
void
|
void
|
||||||
local_bus_init(void)
|
local_bus_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
@ -344,8 +343,7 @@ sdram_init(void)
|
||||||
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
||||||
|
|
||||||
uint idx;
|
uint idx;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
||||||
uint cpu_board_rev;
|
uint cpu_board_rev;
|
||||||
uint lsdmr_common;
|
uint lsdmr_common;
|
||||||
|
@ -506,3 +504,31 @@ pci_init_board(void)
|
||||||
pci_mpc85xx_init(hose);
|
pci_mpc85xx_init(hose);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||||
|
void
|
||||||
|
ft_pci_setup(void *blob, bd_t *bd)
|
||||||
|
{
|
||||||
|
int node, tmp[2];
|
||||||
|
const char *path;
|
||||||
|
|
||||||
|
node = fdt_path_offset(blob, "/aliases");
|
||||||
|
tmp[0] = 0;
|
||||||
|
if (node >= 0) {
|
||||||
|
#ifdef CONFIG_PCI1
|
||||||
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = hose[0].last_busno - hose[0].first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_MPC85XX_PCI2
|
||||||
|
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = hose[1].last_busno - hose[1].first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
|
@ -34,7 +34,7 @@ SECTIONS
|
||||||
.bootpg 0xFFFFF000 :
|
.bootpg 0xFFFFF000 :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.bootpg)
|
cpu/mpc85xx/start.o (.bootpg)
|
||||||
board/cds/mpc8541cds/init.o (.bootpg)
|
board/freescale/mpc8541cds/init.o (.bootpg)
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
|
||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
|
@ -64,7 +64,7 @@ SECTIONS
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.text)
|
cpu/mpc85xx/start.o (.text)
|
||||||
board/cds/mpc8541cds/init.o (.text)
|
board/freescale/mpc8541cds/init.o (.text)
|
||||||
cpu/mpc85xx/traps.o (.text)
|
cpu/mpc85xx/traps.o (.text)
|
||||||
cpu/mpc85xx/interrupts.o (.text)
|
cpu/mpc85xx/interrupts.o (.text)
|
||||||
cpu/mpc85xx/cpu_init.o (.text)
|
cpu/mpc85xx/cpu_init.o (.text)
|
|
@ -27,13 +27,6 @@
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <mpc85xx.h>
|
#include <mpc85xx.h>
|
||||||
|
|
||||||
#define LAWAR_TRGT_PCI1 0x00000000
|
|
||||||
#define LAWAR_TRGT_PCIE1 0x00200000
|
|
||||||
#define LAWAR_TRGT_PCIE2 0x00100000
|
|
||||||
#define LAWAR_TRGT_PCIE3 0x00300000
|
|
||||||
#define LAWAR_TRGT_LBC 0x00400000
|
|
||||||
#define LAWAR_TRGT_DDR 0x00f00000
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TLB0 and TLB1 Entries
|
* TLB0 and TLB1 Entries
|
||||||
*
|
*
|
||||||
|
@ -212,31 +205,31 @@ law_entry:
|
||||||
.long (4f-3f)/8
|
.long (4f-3f)/8
|
||||||
3:
|
3:
|
||||||
.long 0
|
.long 0
|
||||||
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
|
.long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
|
||||||
|
|
||||||
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
|
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||||
|
|
||||||
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
|
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
|
||||||
|
|
||||||
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
|
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
|
||||||
|
|
||||||
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
|
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M)
|
||||||
|
|
||||||
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
|
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_64K)
|
||||||
|
|
||||||
.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
|
.long (CFG_PCIE2_MEM_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||||
|
|
||||||
.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
|
.long (CFG_PCIE2_IO_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_64K)
|
||||||
|
|
||||||
/* contains both PCIE3 MEM & IO space */
|
/* contains both PCIE3 MEM & IO space */
|
||||||
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
|
.long (CFG_PCIE3_MEM_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE3 | (LAWAR_SIZE & LAWAR_SIZE_4M)
|
||||||
4:
|
4:
|
||||||
entry_end
|
entry_end
|
||||||
|
|
|
@ -29,14 +29,11 @@
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <spd.h>
|
#include <spd.h>
|
||||||
#include <miiphy.h>
|
#include <miiphy.h>
|
||||||
|
#include <libfdt.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
|
|
||||||
#include "../common/pixis.h"
|
#include "../common/pixis.h"
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE)
|
|
||||||
#include <ft_build.h>
|
|
||||||
extern void ft_cpu_setup(void *blob, bd_t *bd);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||||
#endif
|
#endif
|
||||||
|
@ -52,10 +49,9 @@ int board_early_init_f (void)
|
||||||
|
|
||||||
int checkboard (void)
|
int checkboard (void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
|
||||||
volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
|
|
||||||
|
|
||||||
if ((uint)&gur->porpllsr != 0xe00e0000) {
|
if ((uint)&gur->porpllsr != 0xe00e0000) {
|
||||||
printf("immap size error %x\n",&gur->porpllsr);
|
printf("immap size error %x\n",&gur->porpllsr);
|
||||||
|
@ -149,8 +145,7 @@ int first_free_busno=0;
|
||||||
void
|
void
|
||||||
pci_init_board(void)
|
pci_init_board(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
uint devdisr = gur->devdisr;
|
uint devdisr = gur->devdisr;
|
||||||
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
||||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
||||||
|
@ -508,51 +503,47 @@ get_board_sys_clk(ulong dummy)
|
||||||
return val;
|
return val;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||||
|
|
||||||
void
|
void
|
||||||
ft_board_setup(void *blob, bd_t *bd)
|
ft_board_setup(void *blob, bd_t *bd)
|
||||||
{
|
{
|
||||||
u32 *p;
|
int node, tmp[2];
|
||||||
int len;
|
const char *path;
|
||||||
|
|
||||||
ft_cpu_setup(blob, bd);
|
ft_cpu_setup(blob, bd);
|
||||||
|
|
||||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
node = fdt_path_offset(blob, "/aliases");
|
||||||
if (p != NULL) {
|
tmp[0] = 0;
|
||||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
if (node >= 0) {
|
||||||
*p = cpu_to_be32(bd->bi_memsize);
|
|
||||||
}
|
|
||||||
#ifdef CONFIG_PCI1
|
#ifdef CONFIG_PCI1
|
||||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||||
if (p != NULL) {
|
if (path) {
|
||||||
p[0] = 0;
|
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||||
p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
}
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_PCIE1
|
|
||||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
|
|
||||||
if (p != NULL) {
|
|
||||||
p[0] = 0;
|
|
||||||
p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
|
||||||
debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_PCIE2
|
#ifdef CONFIG_PCIE2
|
||||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
|
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||||
if (p != NULL) {
|
if (path) {
|
||||||
p[0] = 0;
|
tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
|
||||||
p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
}
|
||||||
}
|
#endif
|
||||||
|
#ifdef CONFIG_PCIE1
|
||||||
|
path = fdt_getprop(blob, node, "pci2", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_PCIE3
|
#ifdef CONFIG_PCIE3
|
||||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@b000/bus-range", &len);
|
path = fdt_getprop(blob, node, "pci3", NULL);
|
||||||
if (p != NULL) {
|
if (path) {
|
||||||
p[0] = 0;
|
tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
|
||||||
p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
}
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -28,13 +28,6 @@
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <mpc85xx.h>
|
#include <mpc85xx.h>
|
||||||
|
|
||||||
#define LAWAR_TRGT_PCI1 0x00000000
|
|
||||||
#define LAWAR_TRGT_PCI2 0x00100000
|
|
||||||
#define LAWAR_TRGT_PCIE 0x00200000
|
|
||||||
#define LAWAR_TRGT_RIO 0x00c00000
|
|
||||||
#define LAWAR_TRGT_LBC 0x00400000
|
|
||||||
#define LAWAR_TRGT_DDR 0x00f00000
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TLB0 and TLB1 Entries
|
* TLB0 and TLB1 Entries
|
||||||
*
|
*
|
||||||
|
@ -232,39 +225,39 @@ law_entry:
|
||||||
.long (4f-3f)/8
|
.long (4f-3f)/8
|
||||||
3:
|
3:
|
||||||
.long 0
|
.long 0
|
||||||
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
|
.long (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
|
||||||
|
|
||||||
#ifdef CFG_PCI1_MEM_PHYS
|
#ifdef CFG_PCI1_MEM_PHYS
|
||||||
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
|
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||||
|
|
||||||
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
|
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CFG_PCI2_MEM_PHYS
|
#ifdef CFG_PCI2_MEM_PHYS
|
||||||
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
|
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||||
|
|
||||||
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
|
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CFG_PCIE1_MEM_PHYS
|
#ifdef CFG_PCIE1_MEM_PHYS
|
||||||
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
|
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||||
|
|
||||||
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
|
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||||
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
|
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
|
||||||
|
|
||||||
#ifdef CFG_RIO_MEM_PHYS
|
#ifdef CFG_RIO_MEM_PHYS
|
||||||
.long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
|
.long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
|
||||||
.long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
.long LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||||
#endif
|
#endif
|
||||||
4:
|
4:
|
||||||
entry_end
|
entry_end
|
|
@ -29,14 +29,13 @@
|
||||||
#include <asm/immap_fsl_pci.h>
|
#include <asm/immap_fsl_pci.h>
|
||||||
#include <spd.h>
|
#include <spd.h>
|
||||||
#include <miiphy.h>
|
#include <miiphy.h>
|
||||||
|
#include <libfdt.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
|
|
||||||
#include "../common/cadmus.h"
|
#include "../common/cadmus.h"
|
||||||
#include "../common/eeprom.h"
|
#include "../common/eeprom.h"
|
||||||
#include "../common/via.h"
|
#include "../common/via.h"
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE)
|
|
||||||
#include <ft_build.h>
|
|
||||||
#endif
|
|
||||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||||
#endif
|
#endif
|
||||||
|
@ -55,9 +54,8 @@ int board_early_init_f (void)
|
||||||
|
|
||||||
int checkboard (void)
|
int checkboard (void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
|
||||||
volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
|
|
||||||
|
|
||||||
/* PCI slot in USER bits CSR[6:7] by convention. */
|
/* PCI slot in USER bits CSR[6:7] by convention. */
|
||||||
uint pci_slot = get_pci_slot ();
|
uint pci_slot = get_pci_slot ();
|
||||||
|
@ -96,7 +94,6 @@ long int
|
||||||
initdram(int board_type)
|
initdram(int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
puts("Initializing\n");
|
puts("Initializing\n");
|
||||||
|
|
||||||
|
@ -109,7 +106,7 @@ initdram(int board_type)
|
||||||
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
||||||
*/
|
*/
|
||||||
|
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
|
|
||||||
gur->ddrdllcr = 0x81000000;
|
gur->ddrdllcr = 0x81000000;
|
||||||
asm("sync;isync;msync");
|
asm("sync;isync;msync");
|
||||||
|
@ -139,9 +136,8 @@ initdram(int board_type)
|
||||||
void
|
void
|
||||||
local_bus_init(void)
|
local_bus_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
@ -177,8 +173,7 @@ sdram_init(void)
|
||||||
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
||||||
|
|
||||||
uint idx;
|
uint idx;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
||||||
uint cpu_board_rev;
|
uint cpu_board_rev;
|
||||||
uint lsdmr_common;
|
uint lsdmr_common;
|
||||||
|
@ -330,8 +325,7 @@ int first_free_busno=0;
|
||||||
void
|
void
|
||||||
pci_init_board(void)
|
pci_init_board(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
||||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
||||||
|
|
||||||
|
@ -524,30 +518,30 @@ int last_stage_init(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||||
void
|
void
|
||||||
ft_pci_setup(void *blob, bd_t *bd)
|
ft_pci_setup(void *blob, bd_t *bd)
|
||||||
{
|
{
|
||||||
u32 *p;
|
int node, tmp[2];
|
||||||
int len;
|
const char *path;
|
||||||
|
|
||||||
|
|
||||||
|
node = fdt_path_offset(blob, "/aliases");
|
||||||
|
tmp[0] = 0;
|
||||||
|
if (node >= 0) {
|
||||||
#ifdef CONFIG_PCI1
|
#ifdef CONFIG_PCI1
|
||||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||||
if (p != NULL) {
|
if (path) {
|
||||||
p[0] = 0;
|
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||||
p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
}
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_PCIE1
|
#ifdef CONFIG_PCIE1
|
||||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
|
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||||
if (p != NULL) {
|
if (path) {
|
||||||
p[0] = 0;
|
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||||
p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
}
|
||||||
}
|
|
||||||
#endif
|
#endif
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
|
@ -34,7 +34,7 @@ SECTIONS
|
||||||
.bootpg 0xFFFFF000 :
|
.bootpg 0xFFFFF000 :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.bootpg)
|
cpu/mpc85xx/start.o (.bootpg)
|
||||||
board/cds/mpc8548cds/init.o (.bootpg)
|
board/freescale/mpc8548cds/init.o (.bootpg)
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
|
||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
|
@ -64,7 +64,7 @@ SECTIONS
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.text)
|
cpu/mpc85xx/start.o (.text)
|
||||||
board/cds/mpc8548cds/init.o (.text)
|
board/freescale/mpc8548cds/init.o (.text)
|
||||||
cpu/mpc85xx/traps.o (.text)
|
cpu/mpc85xx/traps.o (.text)
|
||||||
cpu/mpc85xx/interrupts.o (.text)
|
cpu/mpc85xx/interrupts.o (.text)
|
||||||
cpu/mpc85xx/cpu_init.o (.text)
|
cpu/mpc85xx/cpu_init.o (.text)
|
|
@ -26,6 +26,8 @@
|
||||||
#include <asm/immap_85xx.h>
|
#include <asm/immap_85xx.h>
|
||||||
#include <ioports.h>
|
#include <ioports.h>
|
||||||
#include <spd.h>
|
#include <spd.h>
|
||||||
|
#include <libfdt.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
|
|
||||||
#include "../common/cadmus.h"
|
#include "../common/cadmus.h"
|
||||||
#include "../common/eeprom.h"
|
#include "../common/eeprom.h"
|
||||||
|
@ -201,8 +203,7 @@ int board_early_init_f (void)
|
||||||
|
|
||||||
int checkboard (void)
|
int checkboard (void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
|
||||||
|
|
||||||
/* PCI slot in USER bits CSR[6:7] by convention. */
|
/* PCI slot in USER bits CSR[6:7] by convention. */
|
||||||
uint pci_slot = get_pci_slot ();
|
uint pci_slot = get_pci_slot ();
|
||||||
|
@ -248,7 +249,6 @@ long int
|
||||||
initdram(int board_type)
|
initdram(int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
puts("Initializing\n");
|
puts("Initializing\n");
|
||||||
|
|
||||||
|
@ -261,7 +261,7 @@ initdram(int board_type)
|
||||||
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
||||||
*/
|
*/
|
||||||
|
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
|
|
||||||
gur->ddrdllcr = 0x81000000;
|
gur->ddrdllcr = 0x81000000;
|
||||||
asm("sync;isync;msync");
|
asm("sync;isync;msync");
|
||||||
|
@ -291,9 +291,8 @@ initdram(int board_type)
|
||||||
void
|
void
|
||||||
local_bus_init(void)
|
local_bus_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
@ -342,8 +341,7 @@ sdram_init(void)
|
||||||
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
||||||
|
|
||||||
uint idx;
|
uint idx;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
||||||
uint cpu_board_rev;
|
uint cpu_board_rev;
|
||||||
uint lsdmr_common;
|
uint lsdmr_common;
|
||||||
|
@ -506,3 +504,31 @@ pci_init_board(void)
|
||||||
pci_mpc85xx_init(hose);
|
pci_mpc85xx_init(hose);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||||
|
void
|
||||||
|
ft_pci_setup(void *blob, bd_t *bd)
|
||||||
|
{
|
||||||
|
int node, tmp[2];
|
||||||
|
const char *path;
|
||||||
|
|
||||||
|
node = fdt_path_offset(blob, "/aliases");
|
||||||
|
tmp[0] = 0;
|
||||||
|
if (node >= 0) {
|
||||||
|
#ifdef CONFIG_PCI1
|
||||||
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = hose[0].last_busno - hose[0].first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_MPC85XX_PCI2
|
||||||
|
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = hose[1].last_busno - hose[1].first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
|
@ -34,7 +34,7 @@ SECTIONS
|
||||||
.bootpg 0xFFFFF000 :
|
.bootpg 0xFFFFF000 :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.bootpg)
|
cpu/mpc85xx/start.o (.bootpg)
|
||||||
board/cds/mpc8555cds/init.o (.bootpg)
|
board/freescale/mpc8555cds/init.o (.bootpg)
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
|
||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
|
@ -64,7 +64,7 @@ SECTIONS
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.text)
|
cpu/mpc85xx/start.o (.text)
|
||||||
board/cds/mpc8555cds/init.o (.text)
|
board/freescale/mpc8555cds/init.o (.text)
|
||||||
cpu/mpc85xx/traps.o (.text)
|
cpu/mpc85xx/traps.o (.text)
|
||||||
cpu/mpc85xx/interrupts.o (.text)
|
cpu/mpc85xx/interrupts.o (.text)
|
||||||
cpu/mpc85xx/cpu_init.o (.text)
|
cpu/mpc85xx/cpu_init.o (.text)
|
|
@ -32,10 +32,8 @@
|
||||||
#include <ioports.h>
|
#include <ioports.h>
|
||||||
#include <spd.h>
|
#include <spd.h>
|
||||||
#include <miiphy.h>
|
#include <miiphy.h>
|
||||||
|
#include <libfdt.h>
|
||||||
#if defined(CONFIG_OF_FLAT_TREE)
|
#include <fdt_support.h>
|
||||||
#include <ft_build.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||||
|
@ -278,13 +276,12 @@ initdram(int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
extern long spd_sdram (void);
|
extern long spd_sdram (void);
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
puts("Initializing\n");
|
puts("Initializing\n");
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_DLL)
|
#if defined(CONFIG_DDR_DLL)
|
||||||
{
|
{
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
uint temp_ddrdll = 0;
|
uint temp_ddrdll = 0;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -326,9 +323,8 @@ initdram(int board_type)
|
||||||
void
|
void
|
||||||
local_bus_init(void)
|
local_bus_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
@ -387,8 +383,7 @@ local_bus_init(void)
|
||||||
void
|
void
|
||||||
sdram_init(void)
|
sdram_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
|
|
||||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
||||||
|
|
||||||
puts(" SDRAM: ");
|
puts(" SDRAM: ");
|
||||||
|
@ -483,8 +478,7 @@ int testdram (void)
|
||||||
long int fixed_sdram (void)
|
long int fixed_sdram (void)
|
||||||
{
|
{
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
|
||||||
|
|
||||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||||||
|
@ -548,35 +542,25 @@ pci_init_board(void)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||||
void
|
|
||||||
ft_soc_setup(void *blob, bd_t *bd)
|
|
||||||
{
|
|
||||||
u32 *p;
|
|
||||||
int len;
|
|
||||||
|
|
||||||
p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
|
|
||||||
|
|
||||||
if (p != NULL)
|
|
||||||
*p = cpu_to_be32(bd->bi_brgfreq);
|
|
||||||
|
|
||||||
p = ft_get_prop(blob,
|
|
||||||
"/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed",
|
|
||||||
&len);
|
|
||||||
if (p != NULL)
|
|
||||||
*p = cpu_to_be32(bd->bi_baudrate);
|
|
||||||
|
|
||||||
p = ft_get_prop(blob,
|
|
||||||
"/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed",
|
|
||||||
&len);
|
|
||||||
if (p != NULL)
|
|
||||||
*p = cpu_to_be32(bd->bi_baudrate);
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
void
|
||||||
ft_board_setup(void *blob, bd_t *bd)
|
ft_board_setup(void *blob, bd_t *bd)
|
||||||
{
|
{
|
||||||
|
int node, tmp[2];
|
||||||
|
const char *path;
|
||||||
|
|
||||||
ft_cpu_setup(blob, bd);
|
ft_cpu_setup(blob, bd);
|
||||||
ft_soc_setup(blob, bd);
|
|
||||||
|
node = fdt_path_offset(blob, "/aliases");
|
||||||
|
tmp[0] = 0;
|
||||||
|
if (node >= 0) {
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = hose.last_busno - hose.first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
|
@ -35,7 +35,7 @@ SECTIONS
|
||||||
.bootpg 0xFFFFF000 :
|
.bootpg 0xFFFFF000 :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.bootpg)
|
cpu/mpc85xx/start.o (.bootpg)
|
||||||
board/mpc8560ads/init.o (.bootpg)
|
board/freescale/mpc8560ads/init.o (.bootpg)
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
|
||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
|
@ -65,7 +65,7 @@ SECTIONS
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.text)
|
cpu/mpc85xx/start.o (.text)
|
||||||
board/mpc8560ads/init.o (.text)
|
board/freescale/mpc8560ads/init.o (.text)
|
||||||
cpu/mpc85xx/commproc.o (.text)
|
cpu/mpc85xx/commproc.o (.text)
|
||||||
cpu/mpc85xx/traps.o (.text)
|
cpu/mpc85xx/traps.o (.text)
|
||||||
cpu/mpc85xx/interrupts.o (.text)
|
cpu/mpc85xx/interrupts.o (.text)
|
|
@ -29,9 +29,7 @@ endif
|
||||||
|
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS := $(BOARD).o \
|
COBJS := $(BOARD).o bcsr.o
|
||||||
bcsr.o \
|
|
||||||
ft_board.o
|
|
||||||
|
|
||||||
SOBJS := init.o
|
SOBJS := init.o
|
||||||
|
|
|
@ -28,7 +28,6 @@
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <mpc85xx.h>
|
#include <mpc85xx.h>
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* TLB0 and TLB1 Entries
|
* TLB0 and TLB1 Entries
|
||||||
*
|
*
|
||||||
|
@ -216,15 +215,14 @@ tlb1_entry:
|
||||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
|
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
|
||||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||||
|
|
||||||
#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
|
#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xfffff)
|
||||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||||
|
|
||||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
|
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
|
||||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
|
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
|
||||||
|
|
||||||
#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
|
#define LAWBAR4 ((CFG_PCIE1_IO_PHYS>>12) & 0xfffff)
|
||||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
|
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
|
||||||
|
|
||||||
|
|
||||||
#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
|
#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
|
||||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
|
@ -26,9 +26,12 @@
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/immap_85xx.h>
|
#include <asm/immap_85xx.h>
|
||||||
|
#include <asm/immap_fsl_pci.h>
|
||||||
#include <spd.h>
|
#include <spd.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
#include <ioports.h>
|
#include <ioports.h>
|
||||||
|
#include <libfdt.h>
|
||||||
|
#include <fdt_support.h>
|
||||||
|
|
||||||
#include "bcsr.h"
|
#include "bcsr.h"
|
||||||
|
|
||||||
|
@ -133,7 +136,6 @@ long int
|
||||||
initdram(int board_type)
|
initdram(int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
puts("Initializing\n");
|
puts("Initializing\n");
|
||||||
|
|
||||||
|
@ -146,7 +148,7 @@ initdram(int board_type)
|
||||||
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
* Override DLL = 1, Course Adj = 1, Tap Select = 0
|
||||||
*/
|
*/
|
||||||
|
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
|
|
||||||
gur->ddrdllcr = 0x81000000;
|
gur->ddrdllcr = 0x81000000;
|
||||||
asm("sync;isync;msync");
|
asm("sync;isync;msync");
|
||||||
|
@ -176,9 +178,8 @@ initdram(int board_type)
|
||||||
void
|
void
|
||||||
local_bus_init(void)
|
local_bus_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
@ -211,8 +212,7 @@ sdram_init(void)
|
||||||
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
|
||||||
|
|
||||||
uint idx;
|
uint idx;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
|
||||||
uint lsdmr_common;
|
uint lsdmr_common;
|
||||||
|
|
||||||
|
@ -337,16 +337,19 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static struct pci_controller hose[] = {
|
static struct pci_controller pci1_hose = {
|
||||||
{
|
|
||||||
#ifndef CONFIG_PCI_PNP
|
#ifndef CONFIG_PCI_PNP
|
||||||
config_table: pci_mpc8568mds_config_table,
|
config_table: pci_mpc8568mds_config_table,
|
||||||
#endif
|
#endif
|
||||||
}
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#endif /* CONFIG_PCI */
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCIE1
|
||||||
|
static struct pci_controller pcie1_hose;
|
||||||
|
#endif /* CONFIG_PCIE1 */
|
||||||
|
|
||||||
|
int first_free_busno = 0;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
|
* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
|
||||||
*/
|
*/
|
||||||
|
@ -389,11 +392,164 @@ pib_init(void)
|
||||||
asm("eieio");
|
asm("eieio");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCI
|
||||||
void
|
void
|
||||||
pci_init_board(void)
|
pci_init_board(void)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_PCI
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
|
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
||||||
|
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCI1
|
||||||
|
{
|
||||||
pib_init();
|
pib_init();
|
||||||
pci_mpc85xx_init(hose);
|
|
||||||
|
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
|
||||||
|
extern void fsl_pci_init(struct pci_controller *hose);
|
||||||
|
struct pci_controller *hose = &pci1_hose;
|
||||||
|
|
||||||
|
uint pci_32 = 1; /* PORDEVSR[15] */
|
||||||
|
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
|
||||||
|
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
|
||||||
|
|
||||||
|
uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
|
||||||
|
|
||||||
|
uint pci_speed = 66666000;
|
||||||
|
|
||||||
|
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||||
|
printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
|
||||||
|
(pci_32) ? 32 : 64,
|
||||||
|
(pci_speed == 33333000) ? "33" :
|
||||||
|
(pci_speed == 66666000) ? "66" : "unknown",
|
||||||
|
pci_clk_sel ? "sync" : "async",
|
||||||
|
pci_agent ? "agent" : "host",
|
||||||
|
pci_arb ? "arbiter" : "external-arbiter"
|
||||||
|
);
|
||||||
|
|
||||||
|
/* inbound */
|
||||||
|
pci_set_region(hose->regions + 0,
|
||||||
|
CFG_PCI_MEMORY_BUS,
|
||||||
|
CFG_PCI_MEMORY_PHYS,
|
||||||
|
CFG_PCI_MEMORY_SIZE,
|
||||||
|
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||||
|
|
||||||
|
/* outbound memory */
|
||||||
|
pci_set_region(hose->regions + 1,
|
||||||
|
CFG_PCI1_MEM_BASE,
|
||||||
|
CFG_PCI1_MEM_PHYS,
|
||||||
|
CFG_PCI1_MEM_SIZE,
|
||||||
|
PCI_REGION_MEM);
|
||||||
|
|
||||||
|
/* outbound io */
|
||||||
|
pci_set_region(hose->regions + 2,
|
||||||
|
CFG_PCI1_IO_BASE,
|
||||||
|
CFG_PCI1_IO_PHYS,
|
||||||
|
CFG_PCI1_IO_SIZE,
|
||||||
|
PCI_REGION_IO);
|
||||||
|
|
||||||
|
hose->region_count = 3;
|
||||||
|
|
||||||
|
hose->first_busno = first_free_busno;
|
||||||
|
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||||
|
|
||||||
|
fsl_pci_init(hose);
|
||||||
|
first_free_busno = hose->last_busno+1;
|
||||||
|
printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
|
||||||
|
} else {
|
||||||
|
printf (" PCI: disabled\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_PCIE1
|
||||||
|
{
|
||||||
|
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
|
||||||
|
extern void fsl_pci_init(struct pci_controller *hose);
|
||||||
|
struct pci_controller *hose = &pcie1_hose;
|
||||||
|
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
|
||||||
|
|
||||||
|
int pcie_configured = io_sel >= 1;
|
||||||
|
|
||||||
|
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||||
|
printf ("\n PCIE connected to slot as %s (base address %x)",
|
||||||
|
pcie_ep ? "End Point" : "Root Complex",
|
||||||
|
(uint)pci);
|
||||||
|
|
||||||
|
if (pci->pme_msg_det) {
|
||||||
|
pci->pme_msg_det = 0xffffffff;
|
||||||
|
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
|
||||||
|
}
|
||||||
|
printf ("\n");
|
||||||
|
|
||||||
|
/* inbound */
|
||||||
|
pci_set_region(hose->regions + 0,
|
||||||
|
CFG_PCI_MEMORY_BUS,
|
||||||
|
CFG_PCI_MEMORY_PHYS,
|
||||||
|
CFG_PCI_MEMORY_SIZE,
|
||||||
|
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||||
|
|
||||||
|
/* outbound memory */
|
||||||
|
pci_set_region(hose->regions + 1,
|
||||||
|
CFG_PCIE1_MEM_BASE,
|
||||||
|
CFG_PCIE1_MEM_PHYS,
|
||||||
|
CFG_PCIE1_MEM_SIZE,
|
||||||
|
PCI_REGION_MEM);
|
||||||
|
|
||||||
|
/* outbound io */
|
||||||
|
pci_set_region(hose->regions + 2,
|
||||||
|
CFG_PCIE1_IO_BASE,
|
||||||
|
CFG_PCIE1_IO_PHYS,
|
||||||
|
CFG_PCIE1_IO_SIZE,
|
||||||
|
PCI_REGION_IO);
|
||||||
|
|
||||||
|
hose->region_count = 3;
|
||||||
|
|
||||||
|
hose->first_busno=first_free_busno;
|
||||||
|
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||||
|
|
||||||
|
fsl_pci_init(hose);
|
||||||
|
printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
|
||||||
|
|
||||||
|
first_free_busno=hose->last_busno+1;
|
||||||
|
|
||||||
|
} else {
|
||||||
|
printf (" PCIE: disabled\n");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
#endif /* CONFIG_PCI */
|
||||||
|
|
||||||
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||||
|
void
|
||||||
|
ft_board_setup(void *blob, bd_t *bd)
|
||||||
|
{
|
||||||
|
int node, tmp[2];
|
||||||
|
const char *path;
|
||||||
|
|
||||||
|
ft_cpu_setup(blob, bd);
|
||||||
|
|
||||||
|
node = fdt_path_offset(blob, "/aliases");
|
||||||
|
tmp[0] = 0;
|
||||||
|
if (node >= 0) {
|
||||||
|
#ifdef CONFIG_PCI1
|
||||||
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_PCIE1
|
||||||
|
path = fdt_getprop(blob, node, "pci1", NULL);
|
||||||
|
if (path) {
|
||||||
|
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||||
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
|
@ -37,7 +37,7 @@ SECTIONS
|
||||||
.bootpg 0xFFFFF000:
|
.bootpg 0xFFFFF000:
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.bootpg)
|
cpu/mpc85xx/start.o (.bootpg)
|
||||||
board/mpc8568mds/init.o (.bootpg)
|
board/freescale/mpc8568mds/init.o (.bootpg)
|
||||||
} = 0xffff
|
} = 0xffff
|
||||||
|
|
||||||
/* Read-only sections, merged into text segment: */
|
/* Read-only sections, merged into text segment: */
|
||||||
|
@ -67,7 +67,7 @@ SECTIONS
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
cpu/mpc85xx/start.o (.text)
|
cpu/mpc85xx/start.o (.text)
|
||||||
board/mpc8568mds/init.o (.text)
|
board/freescale/mpc8568mds/init.o (.text)
|
||||||
cpu/mpc85xx/traps.o (.text)
|
cpu/mpc85xx/traps.o (.text)
|
||||||
cpu/mpc85xx/interrupts.o (.text)
|
cpu/mpc85xx/interrupts.o (.text)
|
||||||
cpu/mpc85xx/cpu_init.o (.text)
|
cpu/mpc85xx/cpu_init.o (.text)
|
51
board/korat/Makefile
Normal file
51
board/korat/Makefile
Normal file
|
@ -0,0 +1,51 @@
|
||||||
|
#
|
||||||
|
# (C) Copyright 2002-2007
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
|
COBJS = $(BOARD).o
|
||||||
|
SOBJS = init.o
|
||||||
|
|
||||||
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
|
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||||
|
|
||||||
|
$(LIB): $(OBJS) $(SOBJS)
|
||||||
|
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(SOBJS) $(OBJS)
|
||||||
|
|
||||||
|
distclean: clean
|
||||||
|
rm -f $(LIB) core *.bak .depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
# defines $(obj).depend target
|
||||||
|
include $(SRCTREE)/rules.mk
|
||||||
|
|
||||||
|
sinclude $(obj).depend
|
||||||
|
|
||||||
|
#########################################################################
|
37
board/korat/config.mk
Normal file
37
board/korat/config.mk
Normal file
|
@ -0,0 +1,37 @@
|
||||||
|
#
|
||||||
|
# (C) Copyright 2002
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
#
|
||||||
|
# Korat (PPC440EPx) board
|
||||||
|
#
|
||||||
|
|
||||||
|
TEXT_BASE = 0xFFFA0000
|
||||||
|
|
||||||
|
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||||
|
|
||||||
|
ifeq ($(debug),1)
|
||||||
|
PLATFORM_CPPFLAGS += -DDEBUG
|
||||||
|
endif
|
||||||
|
|
||||||
|
ifeq ($(dbcr),1)
|
||||||
|
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||||
|
endif
|
80
board/korat/init.S
Normal file
80
board/korat/init.S
Normal file
|
@ -0,0 +1,80 @@
|
||||||
|
/*
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <ppc_asm.tmpl>
|
||||||
|
#include <asm-ppc/mmu.h>
|
||||||
|
#include <config.h>
|
||||||
|
|
||||||
|
/**************************************************************************
|
||||||
|
* TLB TABLE
|
||||||
|
*
|
||||||
|
* This table is used by the cpu boot code to setup the initial tlb
|
||||||
|
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||||
|
* this table lets each board set things up however they like.
|
||||||
|
*
|
||||||
|
* Pointer to the table is returned in r1
|
||||||
|
*
|
||||||
|
*************************************************************************/
|
||||||
|
.section .bootpg,"ax"
|
||||||
|
.globl tlbtab
|
||||||
|
|
||||||
|
tlbtab:
|
||||||
|
tlbtab_start
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||||
|
* speed up boot process. It is patched after relocation to enable SA_I
|
||||||
|
*/
|
||||||
|
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TLB entries for SDRAM are not needed on this platform. They are
|
||||||
|
* generated dynamically in the SPD DDR2 detection routine.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef CFG_INIT_RAM_DCACHE
|
||||||
|
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||||
|
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* TLB-entry for PCI Memory */
|
||||||
|
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
|
||||||
|
/* TLB-entry for EBC */
|
||||||
|
tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
|
||||||
|
/* TLB-entry for Internal Registers & OCM */
|
||||||
|
/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
|
||||||
|
tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||||
|
|
||||||
|
/*TLB-entry PCI registers*/
|
||||||
|
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
|
||||||
|
|
||||||
|
/* TLB-entry for peripherals */
|
||||||
|
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||||
|
|
||||||
|
/* TLB-entry PCI IO Space - from sr@denx.de */
|
||||||
|
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||||
|
|
||||||
|
tlbtab_end
|
761
board/korat/korat.c
Normal file
761
board/korat/korat.c
Normal file
|
@ -0,0 +1,761 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2007
|
||||||
|
* Larry Johnson, lrj@acm.org
|
||||||
|
*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||||
|
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
#include <asm-ppc/io.h>
|
||||||
|
#include <i2c.h>
|
||||||
|
#include <ppc440.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||||
|
|
||||||
|
ulong flash_get_size(ulong base, int banknum);
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
u32 sdr0_pfc1, sdr0_pfc2;
|
||||||
|
u32 gpio0_ir;
|
||||||
|
u32 reg;
|
||||||
|
int eth;
|
||||||
|
|
||||||
|
mtdcr(ebccfga, xbcfg);
|
||||||
|
mtdcr(ebccfgd, 0xb8400000);
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------
|
||||||
|
* Setup the GPIO pins
|
||||||
|
*
|
||||||
|
* Korat GPIO usage:
|
||||||
|
*
|
||||||
|
* Init.
|
||||||
|
* Pin Source I/O value Function
|
||||||
|
* ------ ------ --- ----- ---------------------------------
|
||||||
|
* GPIO00 Alt1 I/O x PerAddr07
|
||||||
|
* GPIO01 Alt1 I/O x PerAddr06
|
||||||
|
* GPIO02 Alt1 I/O x PerAddr05
|
||||||
|
* GPIO03 GPIO x x GPIO03 to expansion bus connector
|
||||||
|
* GPIO04 GPIO x x GPIO04 to expansion bus connector
|
||||||
|
* GPIO05 GPIO x x GPIO05 to expansion bus connector
|
||||||
|
* GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
|
||||||
|
* GPIO07 Alt1 O x PerCS2 (CPLD)
|
||||||
|
* GPIO08 Alt1 O x PerCS3 to expansion bus connector
|
||||||
|
* GPIO09 Alt1 O x PerCS4 to expansion bus connector
|
||||||
|
* GPIO10 Alt1 O x PerCS5 to expansion bus connector
|
||||||
|
* GPIO11 Alt1 I x PerErr
|
||||||
|
* GPIO12 GPIO O 0 ATMega !Reset
|
||||||
|
* GPIO13 GPIO O 1 SPI Atmega !SS
|
||||||
|
* GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
|
||||||
|
* GPIO15 GPIO O 0 CPU Run LED !On
|
||||||
|
* GPIO16 Alt1 O x GMC1TxD0
|
||||||
|
* GPIO17 Alt1 O x GMC1TxD1
|
||||||
|
* GPIO18 Alt1 O x GMC1TxD2
|
||||||
|
* GPIO19 Alt1 O x GMC1TxD3
|
||||||
|
* GPIO20 Alt1 O x RejectPkt0
|
||||||
|
* GPIO21 Alt1 O x RejectPkt1
|
||||||
|
* GPIO22 GPIO I x PGOOD_DDR
|
||||||
|
* GPIO23 Alt1 O x SCPD0
|
||||||
|
* GPIO24 Alt1 O x GMC0TxD2
|
||||||
|
* GPIO25 Alt1 O x GMC0TxD3
|
||||||
|
* GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
|
||||||
|
* GPIO27 GPIO O 0 PHY #0 1000BASE-X
|
||||||
|
* GPIO28 GPIO O 0 PHY #1 1000BASE-X
|
||||||
|
* GPIO29 GPIO I x Test jumper !Present
|
||||||
|
* GPIO30 GPIO I x SFP module #0 !Present
|
||||||
|
* GPIO31 GPIO I x SFP module #1 !Present
|
||||||
|
*
|
||||||
|
* GPIO32 GPIO O 1 SFP module #0 Tx !Enable
|
||||||
|
* GPIO33 GPIO O 1 SFP module #1 Tx !Enable
|
||||||
|
* GPIO34 Alt2 I x !UART1_CTS
|
||||||
|
* GPIO35 Alt2 O x !UART1_RTS
|
||||||
|
* GPIO36 Alt1 I x !UART0_CTS
|
||||||
|
* GPIO37 Alt1 O x !UART0_RTS
|
||||||
|
* GPIO38 Alt2 O x UART1_Tx
|
||||||
|
* GPIO39 Alt2 I x UART1_Rx
|
||||||
|
* GPIO40 Alt1 I x IRQ0 (Ethernet 0)
|
||||||
|
* GPIO41 Alt1 I x IRQ1 (Ethernet 1)
|
||||||
|
* GPIO42 Alt1 I x IRQ2 (PCI interrupt)
|
||||||
|
* GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
|
||||||
|
* GPIO44 xxxx x x (grounded through pulldown)
|
||||||
|
* GPIO45 GPIO O 0 PHY #0 Enable
|
||||||
|
* GPIO46 GPIO O 0 PHY #1 Enable
|
||||||
|
* GPIO47 GPIO I x Reset switch !Pressed
|
||||||
|
* GPIO48 GPIO I x Shutdown switch !Pressed
|
||||||
|
* GPIO49 xxxx x x (reserved for trace port)
|
||||||
|
* . . . . .
|
||||||
|
* . . . . .
|
||||||
|
* . . . . .
|
||||||
|
* GPIO63 xxxx x x (reserved for trace port)
|
||||||
|
*-------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
out_be32((u32 *) GPIO0_OR, 0x00060000);
|
||||||
|
out_be32((u32 *) GPIO1_OR, 0xC0000000);
|
||||||
|
|
||||||
|
out_be32((u32 *) GPIO0_OSRL, 0x54055400);
|
||||||
|
out_be32((u32 *) GPIO0_OSRH, 0x55015000);
|
||||||
|
out_be32((u32 *) GPIO1_OSRL, 0x02180000);
|
||||||
|
out_be32((u32 *) GPIO1_OSRH, 0x00000000);
|
||||||
|
|
||||||
|
out_be32((u32 *) GPIO0_TSRL, 0x54055500);
|
||||||
|
out_be32((u32 *) GPIO0_TSRH, 0x00015000);
|
||||||
|
out_be32((u32 *) GPIO1_TSRL, 0x00000000);
|
||||||
|
out_be32((u32 *) GPIO1_TSRH, 0x00000000);
|
||||||
|
|
||||||
|
out_be32((u32 *) GPIO0_TCR, 0x000FF0D8);
|
||||||
|
out_be32((u32 *) GPIO1_TCR, 0xD6060000);
|
||||||
|
|
||||||
|
out_be32((u32 *) GPIO0_ISR1L, 0x54000100);
|
||||||
|
out_be32((u32 *) GPIO0_ISR1H, 0x00500000);
|
||||||
|
out_be32((u32 *) GPIO1_ISR1L, 0x00405500);
|
||||||
|
out_be32((u32 *) GPIO1_ISR1H, 0x00000000);
|
||||||
|
|
||||||
|
out_be32((u32 *) GPIO0_ISR2L, 0x00000000);
|
||||||
|
out_be32((u32 *) GPIO0_ISR2H, 0x00000000);
|
||||||
|
out_be32((u32 *) GPIO1_ISR2L, 0x04010000);
|
||||||
|
out_be32((u32 *) GPIO1_ISR2H, 0x00000000);
|
||||||
|
|
||||||
|
out_be32((u32 *) GPIO0_ISR3L, 0x00000000);
|
||||||
|
out_be32((u32 *) GPIO0_ISR3H, 0x00000000);
|
||||||
|
out_be32((u32 *) GPIO1_ISR3L, 0x00000000);
|
||||||
|
out_be32((u32 *) GPIO1_ISR3H, 0x00000000);
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------
|
||||||
|
* Setup the interrupt controller polarities, triggers, etc.
|
||||||
|
*-------------------------------------------------------------------*/
|
||||||
|
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||||
|
mtdcr(uic0er, 0x00000000); /* disable all */
|
||||||
|
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
|
||||||
|
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
|
||||||
|
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
|
||||||
|
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||||
|
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||||
|
|
||||||
|
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||||
|
mtdcr(uic1er, 0x00000000); /* disable all */
|
||||||
|
mtdcr(uic1cr, 0x00000000); /* all non-critical */
|
||||||
|
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
|
||||||
|
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
|
||||||
|
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||||
|
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||||
|
|
||||||
|
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||||
|
mtdcr(uic2er, 0x00000000); /* disable all */
|
||||||
|
mtdcr(uic2cr, 0x00000000); /* all non-critical */
|
||||||
|
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
|
||||||
|
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
|
||||||
|
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||||
|
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||||
|
|
||||||
|
/* take sim card reader and CF controller out of reset */
|
||||||
|
out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80);
|
||||||
|
|
||||||
|
/* Configure the two Ethernet PHYs. For each PHY, configure for fiber
|
||||||
|
* if the SFP module is present, and for copper if it is not present.
|
||||||
|
*/
|
||||||
|
gpio0_ir = in_be32((u32 *) GPIO0_IR);
|
||||||
|
for (eth = 0; eth < 2; ++eth) {
|
||||||
|
if (gpio0_ir & (0x00000001 << (1 - eth))) {
|
||||||
|
/* SFP module not present: configure PHY for copper. */
|
||||||
|
/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
|
||||||
|
out_8((u8 *) CFG_CPLD_BASE + 0x06,
|
||||||
|
in_8((u8 *) CFG_CPLD_BASE + 0x06) |
|
||||||
|
0x06 << (4 * eth));
|
||||||
|
} else {
|
||||||
|
/* SFP module present: configure PHY for fiber and
|
||||||
|
enable output */
|
||||||
|
out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) |
|
||||||
|
(0x00000001 << (4 - eth)));
|
||||||
|
out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) &
|
||||||
|
~(0x00000001 << (31 - eth)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* enable Ethernet: set GPIO45 and GPIO46 to 1 */
|
||||||
|
out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000);
|
||||||
|
|
||||||
|
/* select Ethernet pins */
|
||||||
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
|
||||||
|
SDR0_PFC1_SELECT_CONFIG_4;
|
||||||
|
mfsdr(SDR0_PFC2, sdr0_pfc2);
|
||||||
|
sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
|
||||||
|
SDR0_PFC2_SELECT_CONFIG_4;
|
||||||
|
mtsdr(SDR0_PFC2, sdr0_pfc2);
|
||||||
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
||||||
|
/* PCI arbiter enabled */
|
||||||
|
mfsdr(sdr_pci0, reg);
|
||||||
|
mtsdr(sdr_pci0, 0x80000000 | reg);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int man_data_read(unsigned int addr)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Read an octet of data from address "addr" in the manufacturer's
|
||||||
|
* information serial EEPROM, or -1 on error.
|
||||||
|
*/
|
||||||
|
u8 data[2];
|
||||||
|
|
||||||
|
if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
|
||||||
|
0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
|
||||||
|
debug("man_data_read(0x%02X) failed\n", addr);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
|
||||||
|
return data[0];
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned int man_data_field_addr(unsigned int const field)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* The manufacturer's information serial EEPROM contains a sequence of
|
||||||
|
* zero-delimited fields. Return the starting address of field "field",
|
||||||
|
* or 0 on error.
|
||||||
|
*/
|
||||||
|
unsigned addr, i;
|
||||||
|
|
||||||
|
if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
|
||||||
|
/* Only format "A" is currently supported */
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
|
||||||
|
if ('\0' == man_data_read(addr))
|
||||||
|
++i;
|
||||||
|
}
|
||||||
|
return (addr < 256) ? addr : 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static char *man_data_read_field(char s[], unsigned const field,
|
||||||
|
unsigned const length)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* Place the null-terminated contents of field "field" of length
|
||||||
|
* "length" from the manufacturer's information serial EEPROM into
|
||||||
|
* string "s[length + 1]" and return a pointer to s, or return 0 on
|
||||||
|
* error. In either case the original contents of s[] is not preserved.
|
||||||
|
*/
|
||||||
|
unsigned addr, i;
|
||||||
|
|
||||||
|
addr = man_data_field_addr(field);
|
||||||
|
if (0 == addr || addr + length >= 255)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
for (i = 0; i < length; ++i) {
|
||||||
|
int const c = man_data_read(addr++);
|
||||||
|
|
||||||
|
if (c <= 0)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
s[i] = (char)c;
|
||||||
|
}
|
||||||
|
if (0 != man_data_read(addr))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
s[i] = '\0';
|
||||||
|
return s;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_serial_number(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* If the environmental variable "serial#" is not set, try to set it
|
||||||
|
* from the manufacturer's information serial EEPROM.
|
||||||
|
*/
|
||||||
|
char s[MAN_SERIAL_NO_LENGTH + 1];
|
||||||
|
|
||||||
|
if (0 == getenv("serial#") &&
|
||||||
|
0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD,
|
||||||
|
MAN_SERIAL_NO_LENGTH))
|
||||||
|
setenv("serial#", s);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void set_mac_addresses(void)
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
* If the environmental variables "ethaddr" and/or "eth1addr" are not
|
||||||
|
* set, try to set them from the manufacturer's information serial
|
||||||
|
* EEPROM.
|
||||||
|
*/
|
||||||
|
char s[MAN_MAC_ADDR_LENGTH + 1];
|
||||||
|
|
||||||
|
if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD,
|
||||||
|
MAN_MAC_ADDR_LENGTH))
|
||||||
|
return;
|
||||||
|
|
||||||
|
if (0 == getenv("ethaddr"))
|
||||||
|
setenv("ethaddr", s);
|
||||||
|
|
||||||
|
if (0 == getenv("eth1addr")) {
|
||||||
|
++s[MAN_MAC_ADDR_LENGTH - 1];
|
||||||
|
setenv("eth1addr", s);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------+
|
||||||
|
| misc_init_r.
|
||||||
|
+---------------------------------------------------------------------------*/
|
||||||
|
int misc_init_r(void)
|
||||||
|
{
|
||||||
|
uint pbcr;
|
||||||
|
int size_val = 0;
|
||||||
|
u32 reg;
|
||||||
|
unsigned long usb2d0cr = 0;
|
||||||
|
unsigned long usb2phy0cr, usb2h0cr = 0;
|
||||||
|
unsigned long sdr0_pfc1;
|
||||||
|
char *act = getenv("usbact");
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FLASH stuff...
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Re-do sizing to get full correct info */
|
||||||
|
|
||||||
|
/* adjust flash start and offset */
|
||||||
|
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||||
|
gd->bd->bi_flashoffset = 0;
|
||||||
|
|
||||||
|
mtdcr(ebccfga, pb0cr);
|
||||||
|
pbcr = mfdcr(ebccfgd);
|
||||||
|
switch (gd->bd->bi_flashsize) {
|
||||||
|
case 1 << 20:
|
||||||
|
size_val = 0;
|
||||||
|
break;
|
||||||
|
case 2 << 20:
|
||||||
|
size_val = 1;
|
||||||
|
break;
|
||||||
|
case 4 << 20:
|
||||||
|
size_val = 2;
|
||||||
|
break;
|
||||||
|
case 8 << 20:
|
||||||
|
size_val = 3;
|
||||||
|
break;
|
||||||
|
case 16 << 20:
|
||||||
|
size_val = 4;
|
||||||
|
break;
|
||||||
|
case 32 << 20:
|
||||||
|
size_val = 5;
|
||||||
|
break;
|
||||||
|
case 64 << 20:
|
||||||
|
size_val = 6;
|
||||||
|
break;
|
||||||
|
case 128 << 20:
|
||||||
|
size_val = 7;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
|
||||||
|
mtdcr(ebccfga, pb0cr);
|
||||||
|
mtdcr(ebccfgd, pbcr);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Re-check to get correct base address
|
||||||
|
*/
|
||||||
|
flash_get_size(gd->bd->bi_flashstart, 0);
|
||||||
|
|
||||||
|
/* Monitor protection ON by default */
|
||||||
|
(void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff,
|
||||||
|
&flash_info[0]);
|
||||||
|
|
||||||
|
/* Env protection ON by default */
|
||||||
|
(void)flash_protect(FLAG_PROTECT_SET,
|
||||||
|
CFG_ENV_ADDR_REDUND,
|
||||||
|
CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1,
|
||||||
|
&flash_info[0]);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* USB suff...
|
||||||
|
*/
|
||||||
|
if (act == NULL || strcmp(act, "hostdev") == 0) {
|
||||||
|
/* SDR Setting */
|
||||||
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
|
||||||
|
|
||||||
|
/* An 8-bit/60MHz interface is the only possible alternative
|
||||||
|
when connecting the Device to the PHY */
|
||||||
|
usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
|
||||||
|
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */
|
||||||
|
|
||||||
|
/* To enable the USB 2.0 Device function through the UTMI interface */
|
||||||
|
usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
||||||
|
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */
|
||||||
|
|
||||||
|
sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
|
||||||
|
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */
|
||||||
|
|
||||||
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
|
||||||
|
/*clear resets */
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x00000000);
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST0, 0x00000000);
|
||||||
|
|
||||||
|
printf("USB: Host(int phy) Device(ext phy)\n");
|
||||||
|
|
||||||
|
} else if (strcmp(act, "dev") == 0) {
|
||||||
|
/*-------------------PATCH-------------------------------*/
|
||||||
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */
|
||||||
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x672c6000);
|
||||||
|
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST0, 0x00000080);
|
||||||
|
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x60206000);
|
||||||
|
|
||||||
|
*(unsigned int *)(0xe0000350) = 0x00000001;
|
||||||
|
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x60306000);
|
||||||
|
/*-------------------PATCH-------------------------------*/
|
||||||
|
|
||||||
|
/* SDR Setting */
|
||||||
|
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
|
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0 */
|
||||||
|
usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||||
|
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0 */
|
||||||
|
|
||||||
|
usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
|
||||||
|
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0 */
|
||||||
|
|
||||||
|
usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
||||||
|
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0 */
|
||||||
|
|
||||||
|
sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK;
|
||||||
|
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1 */
|
||||||
|
|
||||||
|
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||||
|
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||||
|
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||||
|
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||||
|
|
||||||
|
/*clear resets */
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST1, 0x00000000);
|
||||||
|
udelay(1000);
|
||||||
|
mtsdr(SDR0_SRST0, 0x00000000);
|
||||||
|
|
||||||
|
printf("USB: Device(int phy)\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
|
||||||
|
reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
|
||||||
|
mtsdr(SDR0_SRST1, reg);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clear PLB4A0_ACR[WRP]
|
||||||
|
* This fix will make the MAL burst disabling patch for the Linux
|
||||||
|
* EMAC driver obsolete.
|
||||||
|
*/
|
||||||
|
reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
|
||||||
|
mtdcr(plb4_acr, reg);
|
||||||
|
|
||||||
|
set_serial_number();
|
||||||
|
set_mac_addresses();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
char const *const s = getenv("serial#");
|
||||||
|
u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
|
||||||
|
u32 const gpio0_or = in_be32((u32 *) GPIO0_OR);
|
||||||
|
|
||||||
|
printf("Board: Korat, Rev. %X", rev);
|
||||||
|
if (s != NULL)
|
||||||
|
printf(", serial# %s", s);
|
||||||
|
|
||||||
|
printf(", Ethernet PHY 0: ");
|
||||||
|
if (gpio0_or & 0x00000010)
|
||||||
|
printf("fiber");
|
||||||
|
else
|
||||||
|
printf("copper");
|
||||||
|
|
||||||
|
printf(", PHY 1: ");
|
||||||
|
if (gpio0_or & 0x00000008)
|
||||||
|
printf("fiber");
|
||||||
|
else
|
||||||
|
printf("copper");
|
||||||
|
|
||||||
|
printf(".\n");
|
||||||
|
return (0);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined(CFG_DRAM_TEST)
|
||||||
|
int testdram(void)
|
||||||
|
{
|
||||||
|
unsigned long *mem = (unsigned long *)0;
|
||||||
|
const unsigned long kend = (1024 / sizeof(unsigned long));
|
||||||
|
unsigned long k, n;
|
||||||
|
|
||||||
|
mtmsr(0);
|
||||||
|
|
||||||
|
/* TODO: find correct size of SDRAM */
|
||||||
|
for (k = 0; k < CFG_MBYTES_SDRAM;
|
||||||
|
++k, mem += (1024 / sizeof(unsigned long))) {
|
||||||
|
if ((k & 1023) == 0)
|
||||||
|
printf("%3d MB\r", k / 1024);
|
||||||
|
|
||||||
|
memset(mem, 0xaaaaaaaa, 1024);
|
||||||
|
for (n = 0; n < kend; ++n) {
|
||||||
|
if (mem[n] != 0xaaaaaaaa) {
|
||||||
|
printf("SDRAM test fails at: %08x\n",
|
||||||
|
(uint) & mem[n]);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
memset(mem, 0x55555555, 1024);
|
||||||
|
for (n = 0; n < kend; ++n) {
|
||||||
|
if (mem[n] != 0x55555555) {
|
||||||
|
printf("SDRAM test fails at: %08x\n",
|
||||||
|
(uint) & mem[n]);
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
printf("SDRAM test passes\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
#endif /* defined(CFG_DRAM_TEST) */
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* pci_pre_init
|
||||||
|
*
|
||||||
|
* This routine is called just prior to registering the hose and gives
|
||||||
|
* the board the opportunity to check things. Returning a value of zero
|
||||||
|
* indicates that things are bad & PCI initialization should be aborted.
|
||||||
|
*
|
||||||
|
* Different boards may wish to customize the pci controller structure
|
||||||
|
* (add regions, override default access routines, etc) or perform
|
||||||
|
* certain pre-initialization actions.
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
#if defined(CONFIG_PCI)
|
||||||
|
int pci_pre_init(struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
unsigned long addr;
|
||||||
|
|
||||||
|
/*-------------------------------------------------------------------------+
|
||||||
|
| Set priority for all PLB3 devices to 0.
|
||||||
|
| Set PLB3 arbiter to fair mode.
|
||||||
|
+-------------------------------------------------------------------------*/
|
||||||
|
mfsdr(sdr_amp1, addr);
|
||||||
|
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
|
||||||
|
addr = mfdcr(plb3_acr);
|
||||||
|
mtdcr(plb3_acr, addr | 0x80000000);
|
||||||
|
|
||||||
|
/*-------------------------------------------------------------------------+
|
||||||
|
| Set priority for all PLB4 devices to 0.
|
||||||
|
+-------------------------------------------------------------------------*/
|
||||||
|
mfsdr(sdr_amp0, addr);
|
||||||
|
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
|
||||||
|
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
|
||||||
|
mtdcr(plb4_acr, addr);
|
||||||
|
|
||||||
|
/*-------------------------------------------------------------------------+
|
||||||
|
| Set Nebula PLB4 arbiter to fair mode.
|
||||||
|
+-------------------------------------------------------------------------*/
|
||||||
|
/* Segment0 */
|
||||||
|
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
||||||
|
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
||||||
|
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
||||||
|
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
|
||||||
|
mtdcr(plb0_acr, addr);
|
||||||
|
|
||||||
|
/* Segment1 */
|
||||||
|
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
||||||
|
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
||||||
|
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
||||||
|
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
|
||||||
|
mtdcr(plb1_acr, addr);
|
||||||
|
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_PCI) */
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* pci_target_init
|
||||||
|
*
|
||||||
|
* The bootstrap configuration provides default settings for the pci
|
||||||
|
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||||
|
* may not be sufficient for a given board.
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||||
|
void pci_target_init(struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
* Set up Direct MMIO registers
|
||||||
|
*--------------------------------------------------------------------------*/
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
| PowerPC440EPX PCI Master configuration.
|
||||||
|
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||||
|
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
|
||||||
|
| Use byte reversed out routines to handle endianess.
|
||||||
|
| Make this region non-prefetchable.
|
||||||
|
+--------------------------------------------------------------------------*/
|
||||||
|
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
||||||
|
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
||||||
|
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
|
||||||
|
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||||
|
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
|
||||||
|
|
||||||
|
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
|
||||||
|
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
|
||||||
|
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
|
||||||
|
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||||
|
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
|
||||||
|
|
||||||
|
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
||||||
|
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
|
||||||
|
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
|
||||||
|
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
* Set up Configuration registers
|
||||||
|
*--------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Program the board's subsystem id/vendor id */
|
||||||
|
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
||||||
|
CFG_PCI_SUBSYS_VENDORID);
|
||||||
|
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
|
||||||
|
|
||||||
|
/* Configure command register as bus master */
|
||||||
|
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||||
|
|
||||||
|
/* 240nS PCI clock */
|
||||||
|
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
||||||
|
|
||||||
|
/* No error reporting */
|
||||||
|
pci_write_config_word(0, PCI_ERREN, 0);
|
||||||
|
|
||||||
|
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
* Set up Configuration registers for on-board NEC uPD720101 USB controller
|
||||||
|
*--------------------------------------------------------------------------*/
|
||||||
|
pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
|
||||||
|
}
|
||||||
|
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* pci_master_init
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
|
||||||
|
void pci_master_init(struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
unsigned short temp_short;
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------------+
|
||||||
|
| Write the PowerPC440 EP PCI Configuration regs.
|
||||||
|
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||||
|
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||||
|
+--------------------------------------------------------------------------*/
|
||||||
|
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
||||||
|
pci_write_config_word(0, PCI_COMMAND,
|
||||||
|
temp_short | PCI_COMMAND_MASTER |
|
||||||
|
PCI_COMMAND_MEMORY);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*************************************************************************
|
||||||
|
* is_pci_host
|
||||||
|
*
|
||||||
|
* This routine is called to determine if a pci scan should be
|
||||||
|
* performed. With various hardware environments (especially cPCI and
|
||||||
|
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||||
|
* bit in the strap register, or generic host/adapter assumptions.
|
||||||
|
*
|
||||||
|
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||||
|
* 440 pci code requires the board to decide at runtime.
|
||||||
|
*
|
||||||
|
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
************************************************************************/
|
||||||
|
#if defined(CONFIG_PCI)
|
||||||
|
int is_pci_host(struct pci_controller *hose)
|
||||||
|
{
|
||||||
|
/* Korat is always configured as host. */
|
||||||
|
return (1);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_POST)
|
||||||
|
/*
|
||||||
|
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||||
|
* Called from board_init_f().
|
||||||
|
*/
|
||||||
|
int post_hotkeys_pressed(void)
|
||||||
|
{
|
||||||
|
return 0; /* No hotkeys supported */
|
||||||
|
}
|
||||||
|
#endif
|
145
board/korat/u-boot.lds
Normal file
145
board/korat/u-boot.lds
Normal file
|
@ -0,0 +1,145 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2002
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
OUTPUT_ARCH(powerpc)
|
||||||
|
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||||
|
/* Do we need any of these for elf?
|
||||||
|
__DYNAMIC = 0; */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.resetvec 0xFFFFFFFC :
|
||||||
|
{
|
||||||
|
*(.resetvec)
|
||||||
|
} = 0xffff
|
||||||
|
|
||||||
|
.bootpg 0xFFFFF000 :
|
||||||
|
{
|
||||||
|
cpu/ppc4xx/start.o (.bootpg)
|
||||||
|
} = 0xffff
|
||||||
|
|
||||||
|
/* Read-only sections, merged into text segment: */
|
||||||
|
. = + SIZEOF_HEADERS;
|
||||||
|
.interp : { *(.interp) }
|
||||||
|
.hash : { *(.hash) }
|
||||||
|
.dynsym : { *(.dynsym) }
|
||||||
|
.dynstr : { *(.dynstr) }
|
||||||
|
.rel.text : { *(.rel.text) }
|
||||||
|
.rela.text : { *(.rela.text) }
|
||||||
|
.rel.data : { *(.rel.data) }
|
||||||
|
.rela.data : { *(.rela.data) }
|
||||||
|
.rel.rodata : { *(.rel.rodata) }
|
||||||
|
.rela.rodata : { *(.rela.rodata) }
|
||||||
|
.rel.got : { *(.rel.got) }
|
||||||
|
.rela.got : { *(.rela.got) }
|
||||||
|
.rel.ctors : { *(.rel.ctors) }
|
||||||
|
.rela.ctors : { *(.rela.ctors) }
|
||||||
|
.rel.dtors : { *(.rel.dtors) }
|
||||||
|
.rela.dtors : { *(.rela.dtors) }
|
||||||
|
.rel.bss : { *(.rel.bss) }
|
||||||
|
.rela.bss : { *(.rela.bss) }
|
||||||
|
.rel.plt : { *(.rel.plt) }
|
||||||
|
.rela.plt : { *(.rela.plt) }
|
||||||
|
.init : { *(.init) }
|
||||||
|
.plt : { *(.plt) }
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
/* WARNING - the following is hand-optimized to fit within */
|
||||||
|
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||||
|
|
||||||
|
cpu/ppc4xx/start.o (.text)
|
||||||
|
|
||||||
|
*(.text)
|
||||||
|
*(.fixup)
|
||||||
|
*(.got1)
|
||||||
|
}
|
||||||
|
_etext = .;
|
||||||
|
PROVIDE (etext = .);
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata1)
|
||||||
|
*(.rodata.str1.4)
|
||||||
|
}
|
||||||
|
.fini : { *(.fini) } =0
|
||||||
|
.ctors : { *(.ctors) }
|
||||||
|
.dtors : { *(.dtors) }
|
||||||
|
|
||||||
|
/* Read-write section, merged into data segment: */
|
||||||
|
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||||
|
_erotext = .;
|
||||||
|
PROVIDE (erotext = .);
|
||||||
|
.reloc :
|
||||||
|
{
|
||||||
|
*(.got)
|
||||||
|
_GOT2_TABLE_ = .;
|
||||||
|
*(.got2)
|
||||||
|
_FIXUP_TABLE_ = .;
|
||||||
|
*(.fixup)
|
||||||
|
}
|
||||||
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||||
|
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.data)
|
||||||
|
*(.data1)
|
||||||
|
*(.sdata)
|
||||||
|
*(.sdata2)
|
||||||
|
*(.dynamic)
|
||||||
|
CONSTRUCTORS
|
||||||
|
}
|
||||||
|
_edata = .;
|
||||||
|
PROVIDE (edata = .);
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
__u_boot_cmd_start = .;
|
||||||
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
__u_boot_cmd_end = .;
|
||||||
|
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
__start___ex_table = .;
|
||||||
|
__ex_table : { *(__ex_table) }
|
||||||
|
__stop___ex_table = .;
|
||||||
|
|
||||||
|
. = ALIGN(256);
|
||||||
|
__init_begin = .;
|
||||||
|
.text.init : { *(.text.init) }
|
||||||
|
.data.init : { *(.data.init) }
|
||||||
|
. = ALIGN(256);
|
||||||
|
__init_end = .;
|
||||||
|
|
||||||
|
__bss_start = .;
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
*(.sbss) *(.scommon)
|
||||||
|
*(.dynbss)
|
||||||
|
*(.bss)
|
||||||
|
*(COMMON)
|
||||||
|
}
|
||||||
|
|
||||||
|
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
|
||||||
|
|
||||||
|
_end = . ;
|
||||||
|
PROVIDE (end = .);
|
||||||
|
}
|
|
@ -395,8 +395,8 @@
|
||||||
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
|
||||||
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
|
||||||
#define DDR0_26_TREF_MASK 0x00003FFF
|
#define DDR0_26_TREF_MASK 0x00003FFF
|
||||||
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
|
#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0)
|
||||||
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
|
#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF)
|
||||||
|
|
||||||
#define DDR0_27 0x1B
|
#define DDR0_27 0x1B
|
||||||
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000
|
||||||
|
|
|
@ -35,8 +35,7 @@ long int fixed_sdram (void);
|
||||||
int board_pre_init (void)
|
int board_pre_init (void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
|
||||||
volatile ccsr_pcix_t *pci = &immr->im_pcix;
|
|
||||||
|
|
||||||
pci->peer &= 0xffffffdf; /* disable master abort */
|
pci->peer &= 0xffffffdf; /* disable master abort */
|
||||||
#endif
|
#endif
|
||||||
|
@ -68,14 +67,13 @@ long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
extern long spd_sdram (void);
|
extern long spd_sdram (void);
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
#if !defined(CONFIG_RAM_AS_FLASH)
|
#if !defined(CONFIG_RAM_AS_FLASH)
|
||||||
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
sys_info_t sysinfo;
|
sys_info_t sysinfo;
|
||||||
uint temp_lbcdll = 0;
|
uint temp_lbcdll = 0;
|
||||||
#endif
|
#endif
|
||||||
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
|
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_DLL)
|
#if defined(CONFIG_DDR_DLL)
|
||||||
|
@ -138,8 +136,7 @@ long int initdram (int board_type)
|
||||||
* enable errors */
|
* enable errors */
|
||||||
uint *p = 0;
|
uint *p = 0;
|
||||||
uint i = 0;
|
uint i = 0;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
|
||||||
dma_init();
|
dma_init();
|
||||||
for (*p = 0; p < (uint *)(8 * 1024); p++) {
|
for (*p = 0; p < (uint *)(8 * 1024); p++) {
|
||||||
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
|
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
|
||||||
|
@ -222,8 +219,7 @@ int testdram (void)
|
||||||
long int fixed_sdram (void)
|
long int fixed_sdram (void)
|
||||||
{
|
{
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
|
||||||
|
|
||||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||||||
|
|
48
board/ms7722se/Makefile
Normal file
48
board/ms7722se/Makefile
Normal file
|
@ -0,0 +1,48 @@
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007
|
||||||
|
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007
|
||||||
|
# Kenati Technologies, Inc.
|
||||||
|
#
|
||||||
|
# board/ms7722se/Makefile
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
|
||||||
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
|
LIB = lib$(BOARD).a
|
||||||
|
|
||||||
|
OBJS := ms7722se.o
|
||||||
|
SOBJS := lowlevel_init.o
|
||||||
|
|
||||||
|
$(LIB): $(OBJS) $(SOBJS)
|
||||||
|
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(SOBJS) $(OBJS)
|
||||||
|
|
||||||
|
distclean: clean
|
||||||
|
rm -f $(LIB) core *.bak .depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||||
|
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||||
|
|
||||||
|
-include .depend
|
||||||
|
|
||||||
|
#########################################################################
|
31
board/ms7722se/config.mk
Normal file
31
board/ms7722se/config.mk
Normal file
|
@ -0,0 +1,31 @@
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007
|
||||||
|
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007
|
||||||
|
# Kenati Technologies, Inc.
|
||||||
|
#
|
||||||
|
# board/ms7722se/config.mk
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
|
||||||
|
#
|
||||||
|
# TEXT_BASE refers to image _after_ relocation.
|
||||||
|
#
|
||||||
|
# NOTE: Must match value used in u-boot.lds (in this directory).
|
||||||
|
#
|
||||||
|
|
||||||
|
TEXT_BASE = 0x8FFC0000
|
294
board/ms7722se/lowlevel_init.S
Normal file
294
board/ms7722se/lowlevel_init.S
Normal file
|
@ -0,0 +1,294 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Kenati Technologies, Inc.
|
||||||
|
*
|
||||||
|
* board/ms7722se/lowlevel_init.S
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
#include <version.h>
|
||||||
|
|
||||||
|
#include <asm/processor.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Board specific low level init code, called _very_ early in the
|
||||||
|
* startup sequence. Relocation to SDRAM has not happened yet, no
|
||||||
|
* stack is available, bss section has not been initialised, etc.
|
||||||
|
*
|
||||||
|
* (Note: As no stack is available, no subroutines can be called...).
|
||||||
|
*/
|
||||||
|
|
||||||
|
.global lowlevel_init
|
||||||
|
|
||||||
|
.text
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
lowlevel_init:
|
||||||
|
|
||||||
|
mov.l CCR_A, r1 ! Address of Cache Control Register
|
||||||
|
mov.l CCR_D, r0 ! Instruction Cache Invalidate
|
||||||
|
mov.l r0, @r1
|
||||||
|
|
||||||
|
mov.l MMUCR_A, r1 ! Address of MMU Control Register
|
||||||
|
mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit
|
||||||
|
mov.l r0, @r1
|
||||||
|
|
||||||
|
mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
|
||||||
|
mov.l MSTPCR0_D, r0 !
|
||||||
|
mov.l r0, @r1
|
||||||
|
|
||||||
|
mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
|
||||||
|
mov.l MSTPCR2_D, r0 !
|
||||||
|
mov.l r0, @r1
|
||||||
|
|
||||||
|
mov.l SBSCR_A, r1 !
|
||||||
|
mov.w SBSCR_D, r0 !
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l PSCR_A, r1 !
|
||||||
|
mov.w PSCR_D, r0 !
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
|
||||||
|
! mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max
|
||||||
|
! mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register)
|
||||||
|
mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
|
||||||
|
mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
|
||||||
|
mov.l FRQCR_D, r0 !
|
||||||
|
mov.l r0, @r1
|
||||||
|
|
||||||
|
mov.l CCR_A, r1 ! Address of Cache Control Register
|
||||||
|
mov.l CCR_D_2, r0 ! ??
|
||||||
|
mov.l r0, @r1
|
||||||
|
|
||||||
|
bsc_init:
|
||||||
|
|
||||||
|
mov.l PSELA_A, r1
|
||||||
|
mov.w PSELA_D, r0
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l DRVCR_A, r1
|
||||||
|
mov.w DRVCR_D, r0
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l PCCR_A, r1
|
||||||
|
mov.w PCCR_D, r0
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l PECR_A, r1
|
||||||
|
mov.w PECR_D, r0
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l PJCR_A, r1
|
||||||
|
mov.w PJCR_D, r0
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l PXCR_A, r1
|
||||||
|
mov.w PXCR_D, r0
|
||||||
|
mov.w r0, @r1
|
||||||
|
|
||||||
|
mov.l CMNCR_A, r1 ! CMNCR address -> R1
|
||||||
|
mov.l CMNCR_D, r0 ! CMNCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CMNCR set
|
||||||
|
|
||||||
|
mov.l CS0BCR_A, r1 ! CS0BCR address -> R1
|
||||||
|
mov.l CS0BCR_D, r0 ! CS0BCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS0BCR set
|
||||||
|
|
||||||
|
mov.l CS2BCR_A, r1 ! CS2BCR address -> R1
|
||||||
|
mov.l CS2BCR_D, r0 ! CS2BCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS2BCR set
|
||||||
|
|
||||||
|
mov.l CS4BCR_A, r1 ! CS4BCR address -> R1
|
||||||
|
mov.l CS4BCR_D, r0 ! CS4BCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS4BCR set
|
||||||
|
|
||||||
|
mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1
|
||||||
|
mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS5ABCR set
|
||||||
|
|
||||||
|
mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1
|
||||||
|
mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS5BBCR set
|
||||||
|
|
||||||
|
mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1
|
||||||
|
mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS6ABCR set
|
||||||
|
|
||||||
|
mov.l CS0WCR_A, r1 ! CS0WCR address -> R1
|
||||||
|
mov.l CS0WCR_D, r0 ! CS0WCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS0WCR set
|
||||||
|
|
||||||
|
mov.l CS2WCR_A, r1 ! CS2WCR address -> R1
|
||||||
|
mov.l CS2WCR_D, r0 ! CS2WCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS2WCR set
|
||||||
|
|
||||||
|
mov.l CS4WCR_A, r1 ! CS4WCR address -> R1
|
||||||
|
mov.l CS4WCR_D, r0 ! CS4WCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS4WCR set
|
||||||
|
|
||||||
|
mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1
|
||||||
|
mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS5AWCR set
|
||||||
|
|
||||||
|
mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1
|
||||||
|
mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS5BWCR set
|
||||||
|
|
||||||
|
mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1
|
||||||
|
mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0
|
||||||
|
mov.l r0, @r1 ! CS6AWCR set
|
||||||
|
|
||||||
|
! SDRAM initialization
|
||||||
|
mov.l SDCR_A, r1 ! SB_SDCR address -> R1
|
||||||
|
mov.l SDCR_D, r0 ! SB_SDCR data -> R0
|
||||||
|
mov.l r0, @r1 ! SB_SDCR set
|
||||||
|
|
||||||
|
mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1
|
||||||
|
mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0
|
||||||
|
mov.l r0, @r1 ! SB_SDWCR set
|
||||||
|
|
||||||
|
mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1
|
||||||
|
mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0
|
||||||
|
mov.l r0, @r1 ! SB_SDPCR set
|
||||||
|
|
||||||
|
mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1
|
||||||
|
mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0
|
||||||
|
mov.l r0, @r1 ! SB_RTCOR set
|
||||||
|
|
||||||
|
mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1
|
||||||
|
mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0
|
||||||
|
mov.l r0, @r1 ! SB_RTCSR set
|
||||||
|
|
||||||
|
mov.l SDMR3_A, r1 ! SDMR3 address -> R1
|
||||||
|
mov #0x00, r0 ! SDMR3 data -> R0
|
||||||
|
mov.b r0, @r1 ! SDMR3 set
|
||||||
|
|
||||||
|
! BL bit off (init = ON) (?!?)
|
||||||
|
|
||||||
|
stc sr, r0 ! BL bit off(init=ON)
|
||||||
|
mov.l SR_MASK_D, r1
|
||||||
|
and r1, r0
|
||||||
|
ldc r0, sr
|
||||||
|
|
||||||
|
rts
|
||||||
|
mov #0, r0
|
||||||
|
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
CCR_A: .long CCR
|
||||||
|
MMUCR_A: .long MMUCR
|
||||||
|
MSTPCR0_A: .long MSTPCR0
|
||||||
|
MSTPCR2_A: .long MSTPCR2
|
||||||
|
SBSCR_A: .long SBSCR
|
||||||
|
PSCR_A: .long PSCR
|
||||||
|
RWTCSR_A: .long RWTCSR
|
||||||
|
RWTCNT_A: .long RWTCNT
|
||||||
|
FRQCR_A: .long FRQCR
|
||||||
|
|
||||||
|
CCR_D: .long 0x00000800
|
||||||
|
CCR_D_2: .long 0x00000103
|
||||||
|
MMUCR_D: .long 0x00000004
|
||||||
|
MSTPCR0_D: .long 0x00001001
|
||||||
|
MSTPCR2_D: .long 0xffffffff
|
||||||
|
FRQCR_D: .long 0x07022538
|
||||||
|
|
||||||
|
PSELA_A: .long 0xa405014E
|
||||||
|
PSELA_D: .word 0x0A10
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
DRVCR_A: .long 0xa405018A
|
||||||
|
DRVCR_D: .word 0x0554
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
PCCR_A: .long 0xa4050104
|
||||||
|
PCCR_D: .word 0x8800
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
PECR_A: .long 0xa4050108
|
||||||
|
PECR_D: .word 0x0000
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
PJCR_A: .long 0xa4050110
|
||||||
|
PJCR_D: .word 0x1000
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
PXCR_A: .long 0xa4050148
|
||||||
|
PXCR_D: .word 0x0AAA
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
CMNCR_A: .long CMNCR
|
||||||
|
CMNCR_D: .long 0x00000013
|
||||||
|
CS0BCR_A: .long CS0BCR ! Flash bank 1
|
||||||
|
CS0BCR_D: .long 0x24920400
|
||||||
|
CS2BCR_A: .long CS2BCR ! SRAM
|
||||||
|
CS2BCR_D: .long 0x24920400
|
||||||
|
CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
|
||||||
|
CS4BCR_D: .long 0x24920400
|
||||||
|
CS5ABCR_A: .long CS5ABCR ! Ext slot
|
||||||
|
CS5ABCR_D: .long 0x24920400
|
||||||
|
CS5BBCR_A: .long CS5BBCR ! USB controller
|
||||||
|
CS5BBCR_D: .long 0x24920400
|
||||||
|
CS6ABCR_A: .long CS6ABCR ! Ethernet
|
||||||
|
CS6ABCR_D: .long 0x24920400
|
||||||
|
|
||||||
|
CS0WCR_A: .long CS0WCR
|
||||||
|
CS0WCR_D: .long 0x00000300
|
||||||
|
CS2WCR_A: .long CS2WCR
|
||||||
|
CS2WCR_D: .long 0x00000300
|
||||||
|
CS4WCR_A: .long CS4WCR
|
||||||
|
CS4WCR_D: .long 0x00000300
|
||||||
|
CS5AWCR_A: .long CS5AWCR
|
||||||
|
CS5AWCR_D: .long 0x00000300
|
||||||
|
CS5BWCR_A: .long CS5BWCR
|
||||||
|
CS5BWCR_D: .long 0x00000300
|
||||||
|
CS6AWCR_A: .long CS6AWCR
|
||||||
|
CS6AWCR_D: .long 0x00000300
|
||||||
|
|
||||||
|
SDCR_A: .long SBSC_SDCR
|
||||||
|
SDCR_D: .long 0x00020809
|
||||||
|
SDWCR_A: .long SBSC_SDWCR
|
||||||
|
SDWCR_D: .long 0x00164d0d
|
||||||
|
SDPCR_A: .long SBSC_SDPCR
|
||||||
|
SDPCR_D: .long 0x00000087
|
||||||
|
RTCOR_A: .long SBSC_RTCOR
|
||||||
|
RTCOR_D: .long 0xA55A0034
|
||||||
|
RTCSR_A: .long SBSC_RTCSR
|
||||||
|
RTCSR_D: .long 0xA55A0010
|
||||||
|
SDMR3_A: .long 0xFE500180
|
||||||
|
|
||||||
|
.align 1
|
||||||
|
|
||||||
|
SBSCR_D: .word 0x0040
|
||||||
|
PSCR_D: .word 0x0000
|
||||||
|
RWTCSR_D_1: .word 0xA507
|
||||||
|
RWTCSR_D_2: .word 0xA507
|
||||||
|
RWTCNT_D: .word 0x5A00
|
||||||
|
|
||||||
|
SR_MASK_D: .long 0xEFFFFF0F
|
59
board/ms7722se/ms7722se.c
Normal file
59
board/ms7722se/ms7722se.c
Normal file
|
@ -0,0 +1,59 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007
|
||||||
|
* Kenati Technologies, Inc.
|
||||||
|
*
|
||||||
|
* board/ms7722se/ms7722se.c
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/io.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
|
||||||
|
#define LED_BASE 0xB0800000
|
||||||
|
|
||||||
|
int checkboard(void)
|
||||||
|
{
|
||||||
|
puts("BOARD: Hitachi UL MS7722SE\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
/* Setup PTXMD[1:0] for /CS6A */
|
||||||
|
outw(inw(PXCR) & ~0xf000, PXCR);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int dram_init (void)
|
||||||
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
gd->bd->bi_memstart = CFG_SDRAM_BASE;
|
||||||
|
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
|
||||||
|
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void led_set_state (unsigned short value)
|
||||||
|
{
|
||||||
|
*((volatile unsigned short *) LED_BASE) = (value & 0xFF);
|
||||||
|
}
|
105
board/ms7722se/u-boot.lds
Normal file
105
board/ms7722se/u-boot.lds
Normal file
|
@ -0,0 +1,105 @@
|
||||||
|
/*
|
||||||
|
* Copyrigth (c) 2007
|
||||||
|
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
|
||||||
|
OUTPUT_ARCH(sh)
|
||||||
|
ENTRY(_start)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
Base address of internal SDRAM is 0x0C000000.
|
||||||
|
Although size of SDRAM can be either 16 or 32 MBytes,
|
||||||
|
we assume 16 MBytes (ie ignore upper half if the full
|
||||||
|
32 MBytes is present).
|
||||||
|
|
||||||
|
NOTE: This address must match with the definition of
|
||||||
|
TEXT_BASE in config.mk (in this directory).
|
||||||
|
|
||||||
|
*/
|
||||||
|
. = 0x8C000000 + (64*1024*1024) - (256*1024);
|
||||||
|
|
||||||
|
PROVIDE (reloc_dst = .);
|
||||||
|
|
||||||
|
PROVIDE (_ftext = .);
|
||||||
|
PROVIDE (_fcode = .);
|
||||||
|
PROVIDE (_start = .);
|
||||||
|
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
cpu/sh4/start.o (.text)
|
||||||
|
. = ALIGN(8192);
|
||||||
|
common/environment.o (.ppcenv)
|
||||||
|
. = ALIGN(8192);
|
||||||
|
common/environment.o (.ppcenvr)
|
||||||
|
. = ALIGN(8192);
|
||||||
|
*(.text)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} =0xFF
|
||||||
|
PROVIDE (_ecode = .);
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
*(.rodata)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (_etext = .);
|
||||||
|
|
||||||
|
|
||||||
|
PROVIDE (_fdata = .);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.data)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (_edata = .);
|
||||||
|
|
||||||
|
PROVIDE (_fgot = .);
|
||||||
|
.got :
|
||||||
|
{
|
||||||
|
*(.got)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (_egot = .);
|
||||||
|
|
||||||
|
PROVIDE (__u_boot_cmd_start = .);
|
||||||
|
.u_boot_cmd :
|
||||||
|
{
|
||||||
|
*(.u_boot_cmd)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (__u_boot_cmd_end = .);
|
||||||
|
|
||||||
|
PROVIDE (reloc_dst_end = .);
|
||||||
|
/* _reloc_dst_end = .; */
|
||||||
|
|
||||||
|
PROVIDE (bss_start = .);
|
||||||
|
PROVIDE (__bss_start = .);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
*(.bss)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (bss_end = .);
|
||||||
|
|
||||||
|
PROVIDE (_end = .);
|
||||||
|
}
|
43
board/ms7750se/Makefile
Normal file
43
board/ms7750se/Makefile
Normal file
|
@ -0,0 +1,43 @@
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007
|
||||||
|
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
|
LIB = lib$(BOARD).a
|
||||||
|
|
||||||
|
OBJS := ms7750se.o
|
||||||
|
SOBJS := lowlevel_init.o
|
||||||
|
|
||||||
|
$(LIB): $(OBJS) $(SOBJS)
|
||||||
|
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||||
|
|
||||||
|
clean:
|
||||||
|
rm -f $(SOBJS) $(OBJS)
|
||||||
|
|
||||||
|
distclean: clean
|
||||||
|
rm -f $(LIB) core *.bak .depend
|
||||||
|
|
||||||
|
#################################################################
|
||||||
|
|
||||||
|
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||||
|
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||||
|
|
||||||
|
-include .depend
|
||||||
|
|
||||||
|
#################################################################
|
23
board/ms7750se/config.mk
Normal file
23
board/ms7750se/config.mk
Normal file
|
@ -0,0 +1,23 @@
|
||||||
|
#
|
||||||
|
# Copyright (C) 2007
|
||||||
|
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
#
|
||||||
|
# NOTE: Must match value used in u-boot.lds (in this directory).
|
||||||
|
#
|
||||||
|
TEXT_BASE = 0x8FFC0000
|
179
board/ms7750se/lowlevel_init.S
Normal file
179
board/ms7750se/lowlevel_init.S
Normal file
|
@ -0,0 +1,179 @@
|
||||||
|
/*
|
||||||
|
modified from SH-IPL+g
|
||||||
|
Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
|
||||||
|
|
||||||
|
Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
|
||||||
|
|
||||||
|
Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
|
||||||
|
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
#include <version.h>
|
||||||
|
|
||||||
|
#include <asm/processor.h>
|
||||||
|
|
||||||
|
#ifdef CONFIG_CPU_SH7751
|
||||||
|
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
|
||||||
|
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
|
||||||
|
#ifdef CONFIG_MARUBUN_PCCARD
|
||||||
|
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
|
||||||
|
A3:2 A2:15 A1:15 A0:6 A0B:7 */
|
||||||
|
#else /* CONFIG_MARUBUN_PCCARD */
|
||||||
|
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
|
||||||
|
A3:2 A2:15 A1:15 A0:6 A0B:7 */
|
||||||
|
#endif /* CONFIG_MARUBUN_PCCARD */
|
||||||
|
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
|
||||||
|
A2: 1-3 A1: 1-3 A0: 0-1 */
|
||||||
|
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
|
||||||
|
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
|
||||||
|
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, ... */
|
||||||
|
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
|
||||||
|
#else /* CONFIG_CPU_SH7751 */
|
||||||
|
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
|
||||||
|
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
|
||||||
|
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
|
||||||
|
A3:2 A2:15 A1:15 A0:15 A0B:7 */
|
||||||
|
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
|
||||||
|
A2: 1-3 A1: 1-3 A0: 0-1 */
|
||||||
|
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
|
||||||
|
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
|
||||||
|
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, ... */
|
||||||
|
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
|
||||||
|
#endif /* CONFIG_CPU_SH7751 */
|
||||||
|
|
||||||
|
.global lowlevel_init
|
||||||
|
.text
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
lowlevel_init:
|
||||||
|
|
||||||
|
mov.l CCR_A, r1 ! CCR Address
|
||||||
|
mov.l CCR_D_DISABLE, r0 ! CCR Data
|
||||||
|
mov.l r0, @r1
|
||||||
|
|
||||||
|
init_bsc:
|
||||||
|
mov.l FRQCR_A,r1 /* FRQCR Address */
|
||||||
|
mov.l FRQCR_D,r0 /* FRQCR Data */
|
||||||
|
mov.w r0,@r1
|
||||||
|
|
||||||
|
mov.l BCR1_A,r1 /* BCR1 Address */
|
||||||
|
mov.l BCR1_D,r0 /* BCR1 Data */
|
||||||
|
mov.l r0,@r1
|
||||||
|
|
||||||
|
mov.l BCR2_A,r1 /* BCR2 Address */
|
||||||
|
mov.l BCR2_D,r0 /* BCR2 Data */
|
||||||
|
mov.w r0,@r1
|
||||||
|
|
||||||
|
mov.l WCR1_A,r1 /* WCR1 Address */
|
||||||
|
mov.l WCR1_D,r0 /* WCR1 Data */
|
||||||
|
mov.l r0,@r1
|
||||||
|
|
||||||
|
mov.l WCR2_A,r1 /* WCR2 Address */
|
||||||
|
mov.l WCR2_D,r0 /* WCR2 Data */
|
||||||
|
mov.l r0,@r1
|
||||||
|
|
||||||
|
mov.l WCR3_A,r1 /* WCR3 Address */
|
||||||
|
mov.l WCR3_D,r0 /* WCR3 Data */
|
||||||
|
mov.l r0,@r1
|
||||||
|
|
||||||
|
mov.l MCR_A,r1 /* MCR Address */
|
||||||
|
mov.l MCR_D1,r0 /* MCR Data1 */
|
||||||
|
mov.l r0,@r1
|
||||||
|
|
||||||
|
mov.l SDMR3_A,r1 /* Set SDRAM mode */
|
||||||
|
mov #0,r0
|
||||||
|
mov.b r0,@r1
|
||||||
|
|
||||||
|
! Do you need PCMCIA setting?
|
||||||
|
! If so, please add the lines here...
|
||||||
|
|
||||||
|
mov.l RTCNT_A,r1 /* RTCNT Address */
|
||||||
|
mov.l RTCNT_D,r0 /* RTCNT Data */
|
||||||
|
mov.w r0,@r1
|
||||||
|
|
||||||
|
mov.l RTCOR_A,r1 /* RTCOR Address */
|
||||||
|
mov.l RTCOR_D,r0 /* RTCOR Data */
|
||||||
|
mov.w r0,@r1
|
||||||
|
|
||||||
|
mov.l RTCSR_A,r1 /* RTCSR Address */
|
||||||
|
mov.l RTCSR_D,r0 /* RTCSR Data */
|
||||||
|
mov.w r0,@r1
|
||||||
|
|
||||||
|
mov.l RFCR_A,r1 /* RFCR Address */
|
||||||
|
mov.l RFCR_D,r0 /* RFCR Data */
|
||||||
|
mov.w r0,@r1 /* Clear reflesh counter */
|
||||||
|
/* Wait DRAM refresh 30 times */
|
||||||
|
mov #30,r3
|
||||||
|
1:
|
||||||
|
mov.w @r1,r0
|
||||||
|
extu.w r0,r2
|
||||||
|
cmp/hi r3,r2
|
||||||
|
bf 1b
|
||||||
|
|
||||||
|
mov.l MCR_A,r1 /* MCR Address */
|
||||||
|
mov.l MCR_D2,r0 /* MCR Data2 */
|
||||||
|
mov.l r0,@r1
|
||||||
|
|
||||||
|
mov.l SDMR3_A,r1 /* Set SDRAM mode */
|
||||||
|
mov #0,r0
|
||||||
|
mov.b r0,@r1
|
||||||
|
|
||||||
|
rts
|
||||||
|
nop
|
||||||
|
|
||||||
|
.align 2
|
||||||
|
|
||||||
|
CCR_A: .long CCR
|
||||||
|
CCR_D_DISABLE: .long 0x0808
|
||||||
|
FRQCR_A: .long FRQCR
|
||||||
|
FRQCR_D:
|
||||||
|
#ifdef CONFIG_CPU_TYPE_R
|
||||||
|
.long 0x00000e1a /* 12:3:3 */
|
||||||
|
#else /* CONFIG_CPU_TYPE_R */
|
||||||
|
#ifdef CONFIG_GOOD_SESH4
|
||||||
|
.long 0x00000e13 /* 6:2:1 */
|
||||||
|
#else
|
||||||
|
.long 0x00000e23 /* 6:1:1 */
|
||||||
|
#endif
|
||||||
|
#endif /* CONFIG_CPU_TYPE_R */
|
||||||
|
|
||||||
|
BCR1_A: .long BCR1
|
||||||
|
BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
|
||||||
|
BCR2_A: .long BCR2
|
||||||
|
BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
|
||||||
|
WCR1_A: .long WCR1
|
||||||
|
WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
|
||||||
|
WCR2_A: .long WCR2
|
||||||
|
WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
|
||||||
|
WCR3_A: .long WCR3
|
||||||
|
WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
|
||||||
|
RTCSR_A: .long RTCSR
|
||||||
|
RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */
|
||||||
|
RTCNT_A: .long RTCNT
|
||||||
|
RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */
|
||||||
|
RTCOR_A: .long RTCOR
|
||||||
|
RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */
|
||||||
|
SDMR3_A: .long SDMR3_ADDRESS
|
||||||
|
MCR_A: .long MCR
|
||||||
|
MCR_D1: .long MCR_D1_VALUE
|
||||||
|
MCR_D2: .long MCR_D2_VALUE
|
||||||
|
RFCR_A: .long RFCR
|
||||||
|
RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */
|
|
@ -1,5 +1,6 @@
|
||||||
/*
|
/*
|
||||||
* Copyright 2004-2007 Freescale Semiconductor.
|
* Copyright (C) 2007
|
||||||
|
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
* project.
|
* project.
|
||||||
|
@ -11,7 +12,7 @@
|
||||||
*
|
*
|
||||||
* This program is distributed in the hope that it will be useful,
|
* This program is distributed in the hope that it will be useful,
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
* GNU General Public License for more details.
|
* GNU General Public License for more details.
|
||||||
*
|
*
|
||||||
* You should have received a copy of the GNU General Public License
|
* You should have received a copy of the GNU General Public License
|
||||||
|
@ -21,25 +22,30 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
#include <asm/processor.h>
|
||||||
|
|
||||||
#include <ft_build.h>
|
int checkboard(void)
|
||||||
|
|
||||||
extern void ft_cpu_setup(void *blob, bd_t *bd);
|
|
||||||
|
|
||||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
|
||||||
void
|
|
||||||
ft_board_setup(void *blob, bd_t *bd)
|
|
||||||
{
|
{
|
||||||
u32 *p;
|
puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
|
||||||
int len;
|
return 0;
|
||||||
#ifdef CONFIG_PCI
|
}
|
||||||
ft_pci_setup(blob, bd);
|
|
||||||
#endif
|
int board_init(void)
|
||||||
ft_cpu_setup(blob, bd);
|
{
|
||||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
return 0;
|
||||||
if (p != NULL) {
|
}
|
||||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
|
||||||
*p = cpu_to_be32(bd->bi_memsize);
|
int dram_init (void)
|
||||||
}
|
{
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
gd->bd->bi_memstart = CFG_SDRAM_BASE;
|
||||||
|
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
|
||||||
|
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_late_init(void)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_OF_FLAT_TREE && CONFIG_OF_BOARD_SETUP */
|
|
105
board/ms7750se/u-boot.lds
Normal file
105
board/ms7750se/u-boot.lds
Normal file
|
@ -0,0 +1,105 @@
|
||||||
|
/*
|
||||||
|
* Copyrigth (c) 2007
|
||||||
|
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
|
||||||
|
OUTPUT_ARCH(sh)
|
||||||
|
ENTRY(_start)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/*
|
||||||
|
Base address of internal SDRAM is 0x0C000000.
|
||||||
|
Although size of SDRAM can be either 16 or 32 MBytes,
|
||||||
|
we assume 16 MBytes (ie ignore upper half if the full
|
||||||
|
32 MBytes is present).
|
||||||
|
|
||||||
|
NOTE: This address must match with the definition of
|
||||||
|
TEXT_BASE in config.mk (in this directory).
|
||||||
|
|
||||||
|
*/
|
||||||
|
. = 0x8C000000 + (64*1024*1024) - (256*1024);
|
||||||
|
|
||||||
|
PROVIDE (reloc_dst = .);
|
||||||
|
|
||||||
|
PROVIDE (_ftext = .);
|
||||||
|
PROVIDE (_fcode = .);
|
||||||
|
PROVIDE (_start = .);
|
||||||
|
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
cpu/sh4/start.o (.text)
|
||||||
|
. = ALIGN(8192);
|
||||||
|
common/environment.o (.ppcenv)
|
||||||
|
. = ALIGN(8192);
|
||||||
|
common/environment.o (.ppcenvr)
|
||||||
|
. = ALIGN(8192);
|
||||||
|
*(.text)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} =0xFF
|
||||||
|
PROVIDE (_ecode = .);
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
*(.rodata)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (_etext = .);
|
||||||
|
|
||||||
|
|
||||||
|
PROVIDE (_fdata = .);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.data)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (_edata = .);
|
||||||
|
|
||||||
|
PROVIDE (_fgot = .);
|
||||||
|
.got :
|
||||||
|
{
|
||||||
|
*(.got)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (_egot = .);
|
||||||
|
|
||||||
|
PROVIDE (__u_boot_cmd_start = .);
|
||||||
|
.u_boot_cmd :
|
||||||
|
{
|
||||||
|
*(.u_boot_cmd)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (__u_boot_cmd_end = .);
|
||||||
|
|
||||||
|
PROVIDE (reloc_dst_end = .);
|
||||||
|
/* _reloc_dst_end = .; */
|
||||||
|
|
||||||
|
PROVIDE (bss_start = .);
|
||||||
|
PROVIDE (__bss_start = .);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
*(.bss)
|
||||||
|
. = ALIGN(4);
|
||||||
|
}
|
||||||
|
PROVIDE (bss_end = .);
|
||||||
|
|
||||||
|
PROVIDE (_end = .);
|
||||||
|
}
|
|
@ -45,8 +45,7 @@ long int fixed_sdram(void);
|
||||||
int board_early_init_f (void)
|
int board_early_init_f (void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
|
||||||
volatile ccsr_pcix_t *pci = &immr->im_pcix;
|
|
||||||
|
|
||||||
pci->peer &= 0xffffffdf; /* disable master abort */
|
pci->peer &= 0xffffffdf; /* disable master abort */
|
||||||
#endif
|
#endif
|
||||||
|
@ -79,13 +78,12 @@ initdram(int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
extern long spd_sdram (void);
|
extern long spd_sdram (void);
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
puts("Initializing\n");
|
puts("Initializing\n");
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_DLL)
|
#if defined(CONFIG_DDR_DLL)
|
||||||
{
|
{
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
int i,x;
|
int i,x;
|
||||||
|
|
||||||
x = 10;
|
x = 10;
|
||||||
|
@ -133,9 +131,8 @@ initdram(int board_type)
|
||||||
void
|
void
|
||||||
local_bus_init(void)
|
local_bus_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
@ -229,8 +226,7 @@ int testdram (void)
|
||||||
long int fixed_sdram (void)
|
long int fixed_sdram (void)
|
||||||
{
|
{
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
|
||||||
|
|
||||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||||||
|
|
|
@ -232,13 +232,12 @@ initdram(int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
extern long spd_sdram (void);
|
extern long spd_sdram (void);
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
puts("Initializing\n");
|
puts("Initializing\n");
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_DLL)
|
#if defined(CONFIG_DDR_DLL)
|
||||||
{
|
{
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
int i,x;
|
int i,x;
|
||||||
|
|
||||||
x = 10;
|
x = 10;
|
||||||
|
@ -287,9 +286,8 @@ initdram(int board_type)
|
||||||
void
|
void
|
||||||
local_bus_init(void)
|
local_bus_init(void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
@ -382,8 +380,7 @@ int testdram (void)
|
||||||
long int fixed_sdram (void)
|
long int fixed_sdram (void)
|
||||||
{
|
{
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
|
||||||
|
|
||||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||||||
|
|
|
@ -195,8 +195,7 @@ const iop_conf_t iop_conf_tab[4][32] = {
|
||||||
int board_early_init_f (void)
|
int board_early_init_f (void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
|
||||||
volatile ccsr_pcix_t *pci = &immr->im_pcix;
|
|
||||||
|
|
||||||
pci->peer &= 0xfffffffdf; /* disable master abort */
|
pci->peer &= 0xfffffffdf; /* disable master abort */
|
||||||
#endif
|
#endif
|
||||||
|
@ -264,16 +263,15 @@ long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
extern long spd_sdram (void);
|
extern long spd_sdram (void);
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
#if 0
|
#if 0
|
||||||
#if !defined(CONFIG_RAM_AS_FLASH)
|
#if !defined(CONFIG_RAM_AS_FLASH)
|
||||||
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
sys_info_t sysinfo;
|
sys_info_t sysinfo;
|
||||||
uint temp_lbcdll = 0;
|
uint temp_lbcdll = 0;
|
||||||
#endif
|
#endif
|
||||||
#endif /* 0 */
|
#endif /* 0 */
|
||||||
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
|
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_DDR_DLL)
|
#if defined(CONFIG_DDR_DLL)
|
||||||
uint temp_ddrdll = 0;
|
uint temp_ddrdll = 0;
|
||||||
|
@ -336,8 +334,7 @@ long int initdram (int board_type)
|
||||||
* enable errors */
|
* enable errors */
|
||||||
uint *p = 0;
|
uint *p = 0;
|
||||||
uint i = 0;
|
uint i = 0;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
|
||||||
dma_init();
|
dma_init();
|
||||||
for (*p = 0; p < (uint *)(8 * 1024); p++) {
|
for (*p = 0; p < (uint *)(8 * 1024); p++) {
|
||||||
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
|
if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
|
||||||
|
@ -424,8 +421,7 @@ long int fixed_sdram (void)
|
||||||
#define CFG_DDR_CONTROL 0xc2000000
|
#define CFG_DDR_CONTROL 0xc2000000
|
||||||
|
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr;
|
|
||||||
|
|
||||||
ddr->cs0_bnds = 0x00000007;
|
ddr->cs0_bnds = 0x00000007;
|
||||||
ddr->cs1_bnds = 0x0010001f;
|
ddr->cs1_bnds = 0x0010001f;
|
||||||
|
|
|
@ -203,8 +203,7 @@ int
|
||||||
board_early_init_f(void)
|
board_early_init_f(void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
|
||||||
volatile ccsr_pcix_t *pci = &immr->im_pcix;
|
|
||||||
|
|
||||||
pci->peer &= 0xfffffffdf; /* disable master abort */
|
pci->peer &= 0xfffffffdf; /* disable master abort */
|
||||||
#endif
|
#endif
|
||||||
|
@ -283,11 +282,10 @@ initdram (int board_type)
|
||||||
{
|
{
|
||||||
long dram_size = 0;
|
long dram_size = 0;
|
||||||
extern long spd_sdram (void);
|
extern long spd_sdram (void);
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_DLL)
|
#if defined(CONFIG_DDR_DLL)
|
||||||
{
|
{
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
uint temp_ddrdll = 0;
|
uint temp_ddrdll = 0;
|
||||||
|
|
||||||
/* Work around to stabilize DDR DLL */
|
/* Work around to stabilize DDR DLL */
|
||||||
|
|
|
@ -252,8 +252,7 @@ int
|
||||||
board_early_init_f(void)
|
board_early_init_f(void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_PCI)
|
#if defined(CONFIG_PCI)
|
||||||
volatile immap_t *immr = (immap_t *)CFG_IMMR;
|
volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
|
||||||
volatile ccsr_pcix_t *pci = &immr->im_pcix;
|
|
||||||
|
|
||||||
pci->peer &= 0xffffffdf; /* disable master abort */
|
pci->peer &= 0xffffffdf; /* disable master abort */
|
||||||
#endif
|
#endif
|
||||||
|
@ -302,8 +301,7 @@ initdram (int board_type)
|
||||||
|
|
||||||
#if defined(CONFIG_DDR_DLL)
|
#if defined(CONFIG_DDR_DLL)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
|
||||||
uint temp_ddrdll = 0;
|
uint temp_ddrdll = 0;
|
||||||
|
|
||||||
/* Work around to stabilize DDR DLL */
|
/* Work around to stabilize DDR DLL */
|
||||||
|
|
|
@ -57,8 +57,7 @@ int cas_latency(void);
|
||||||
long int sdram_setup(int casl)
|
long int sdram_setup(int casl)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
|
||||||
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
|
|
||||||
unsigned long cfg_ddr_timing1;
|
unsigned long cfg_ddr_timing1;
|
||||||
unsigned long cfg_ddr_mode;
|
unsigned long cfg_ddr_mode;
|
||||||
|
|
||||||
|
@ -150,8 +149,7 @@ long int initdram (int board_type)
|
||||||
* This DLL-Override only used on TQM8540 and TQM8560
|
* This DLL-Override only used on TQM8540 and TQM8560
|
||||||
*/
|
*/
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
|
||||||
int i,x;
|
int i,x;
|
||||||
|
|
||||||
x = 10;
|
x = 10;
|
||||||
|
|
|
@ -262,8 +262,7 @@ int checkboard (void)
|
||||||
|
|
||||||
int misc_init_r (void)
|
int misc_init_r (void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Adjust flash start and offset to detected values
|
* Adjust flash start and offset to detected values
|
||||||
|
@ -324,9 +323,8 @@ int misc_init_r (void)
|
||||||
*/
|
*/
|
||||||
void local_bus_init (void)
|
void local_bus_init (void)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
|
||||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
|
||||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
|
||||||
|
|
||||||
uint clkdiv;
|
uint clkdiv;
|
||||||
uint lbc_hz;
|
uint lbc_hz;
|
||||||
|
|
|
@ -33,6 +33,8 @@
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
#if !defined(CFG_FLASH_CFI_DRIVER) /* do not use if CFI driver is configured */
|
||||||
|
|
||||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
|
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
|
||||||
&& !defined(CONFIG_TQM885D)
|
&& !defined(CONFIG_TQM885D)
|
||||||
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
|
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
|
||||||
|
@ -828,3 +830,5 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
/*-----------------------------------------------------------------------
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#endif /* !defined(CFG_FLASH_CFI_DRIVER) */
|
||||||
|
|
|
@ -37,6 +37,7 @@ static long int dram_size (long int, long int *, long int);
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFFFFF
|
#define _NOT_USED_ 0xFFFFFFFF
|
||||||
|
|
||||||
|
/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] =
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
|
@ -63,14 +64,14 @@ const uint sdram_table[] =
|
||||||
/*
|
/*
|
||||||
* Single Write. (Offset 18 in UPMA RAM)
|
* Single Write. (Offset 18 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
|
0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
0x1FF5FC47, /* last */
|
||||||
|
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
/*
|
/*
|
||||||
* Burst Write. (Offset 20 in UPMA RAM)
|
* Burst Write. (Offset 20 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
|
0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
|
||||||
0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
|
0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
|
||||||
_NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
/*
|
/*
|
||||||
|
@ -83,7 +84,7 @@ const uint sdram_table[] =
|
||||||
/*
|
/*
|
||||||
* Exception. (Offset 3c in UPMA RAM)
|
* Exception. (Offset 3c in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x7FFFFC07, /* last */
|
0xFFFFFC07, /* last */
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -183,7 +184,7 @@ long int initdram (int board_type)
|
||||||
#ifndef CONFIG_CAN_DRIVER
|
#ifndef CONFIG_CAN_DRIVER
|
||||||
if ((board_type != 'L') &&
|
if ((board_type != 'L') &&
|
||||||
(board_type != 'M') &&
|
(board_type != 'M') &&
|
||||||
(board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
|
(board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
|
||||||
memctl->memc_or3 = CFG_OR3_PRELIM;
|
memctl->memc_or3 = CFG_OR3_PRELIM;
|
||||||
memctl->memc_br3 = CFG_BR3_PRELIM;
|
memctl->memc_br3 = CFG_BR3_PRELIM;
|
||||||
}
|
}
|
||||||
|
@ -259,7 +260,7 @@ long int initdram (int board_type)
|
||||||
#ifndef CONFIG_CAN_DRIVER
|
#ifndef CONFIG_CAN_DRIVER
|
||||||
if ((board_type != 'L') &&
|
if ((board_type != 'L') &&
|
||||||
(board_type != 'M') &&
|
(board_type != 'M') &&
|
||||||
(board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
|
(board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
|
||||||
/*
|
/*
|
||||||
* Check Bank 1 Memory Size
|
* Check Bank 1 Memory Size
|
||||||
* use current column settings
|
* use current column settings
|
||||||
|
|
|
@ -260,6 +260,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
if (hdr->ih_arch != IH_CPU_NIOS2)
|
if (hdr->ih_arch != IH_CPU_NIOS2)
|
||||||
#elif defined(__PPC__)
|
#elif defined(__PPC__)
|
||||||
if (hdr->ih_arch != IH_CPU_PPC)
|
if (hdr->ih_arch != IH_CPU_PPC)
|
||||||
|
#elif defined(__sh__)
|
||||||
|
if (hdr->ih_arch != IH_CPU_SH)
|
||||||
#else
|
#else
|
||||||
# error Unknown CPU type
|
# error Unknown CPU type
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -886,7 +886,7 @@ input_swap_data(int dev, ulong *sect_buf, int words)
|
||||||
#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
|
#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
|
||||||
|
|
||||||
|
|
||||||
#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
|
#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
|
||||||
static void
|
static void
|
||||||
output_data(int dev, ulong *sect_buf, int words)
|
output_data(int dev, ulong *sect_buf, int words)
|
||||||
{
|
{
|
||||||
|
@ -938,7 +938,7 @@ output_data(int dev, ulong *sect_buf, int words)
|
||||||
}
|
}
|
||||||
#endif /* __PPC__ */
|
#endif /* __PPC__ */
|
||||||
|
|
||||||
#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA)
|
#if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH)
|
||||||
static void
|
static void
|
||||||
input_data(int dev, ulong *sect_buf, int words)
|
input_data(int dev, ulong *sect_buf, int words)
|
||||||
{
|
{
|
||||||
|
|
|
@ -21,6 +21,7 @@
|
||||||
*/
|
*/
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
|
|
||||||
|
#include <asm/arch/chip-features.h>
|
||||||
#include <asm/arch/gpio.h>
|
#include <asm/arch/gpio.h>
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -52,6 +53,7 @@ void gpio_enable_ebi(void)
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef AT32AP700x_CHIP_HAS_USART
|
||||||
void gpio_enable_usart0(void)
|
void gpio_enable_usart0(void)
|
||||||
{
|
{
|
||||||
gpio_select_periph_B(GPIO_PIN_PA8, 0);
|
gpio_select_periph_B(GPIO_PIN_PA8, 0);
|
||||||
|
@ -72,10 +74,12 @@ void gpio_enable_usart2(void)
|
||||||
|
|
||||||
void gpio_enable_usart3(void)
|
void gpio_enable_usart3(void)
|
||||||
{
|
{
|
||||||
|
gpio_select_periph_B(GPIO_PIN_PB17, 0);
|
||||||
gpio_select_periph_B(GPIO_PIN_PB18, 0);
|
gpio_select_periph_B(GPIO_PIN_PB18, 0);
|
||||||
gpio_select_periph_B(GPIO_PIN_PB19, 0);
|
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef AT32AP700x_CHIP_HAS_MACB
|
||||||
void gpio_enable_macb0(void)
|
void gpio_enable_macb0(void)
|
||||||
{
|
{
|
||||||
gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
|
gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
|
||||||
|
@ -125,7 +129,9 @@ void gpio_enable_macb1(void)
|
||||||
gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */
|
gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef AT32AP700x_CHIP_HAS_MMCI
|
||||||
void gpio_enable_mmci(void)
|
void gpio_enable_mmci(void)
|
||||||
{
|
{
|
||||||
gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */
|
gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */
|
||||||
|
@ -135,3 +141,4 @@ void gpio_enable_mmci(void)
|
||||||
gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */
|
gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */
|
||||||
gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */
|
gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */
|
||||||
}
|
}
|
||||||
|
#endif
|
|
@ -198,11 +198,11 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
|
||||||
|
|
||||||
/* Put the device into Transfer state */
|
/* Put the device into Transfer state */
|
||||||
ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
|
ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
|
||||||
if (ret) goto fail;
|
if (ret) goto out;
|
||||||
|
|
||||||
/* Set block length */
|
/* Set block length */
|
||||||
ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
|
ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
|
||||||
if (ret) goto fail;
|
if (ret) goto out;
|
||||||
|
|
||||||
pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
|
pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
|
||||||
|
|
||||||
|
@ -211,7 +211,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
|
||||||
start * mmc_blkdev.blksz, resp,
|
start * mmc_blkdev.blksz, resp,
|
||||||
(R1 | NCR | TRCMD_START | TRDIR_READ
|
(R1 | NCR | TRCMD_START | TRDIR_READ
|
||||||
| TRTYP_BLOCK));
|
| TRTYP_BLOCK));
|
||||||
if (ret) goto fail;
|
if (ret) goto out;
|
||||||
|
|
||||||
ret = -EIO;
|
ret = -EIO;
|
||||||
wordcount = 0;
|
wordcount = 0;
|
||||||
|
@ -219,7 +219,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
|
||||||
do {
|
do {
|
||||||
status = mmci_readl(SR);
|
status = mmci_readl(SR);
|
||||||
if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
|
if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
|
||||||
goto fail;
|
goto read_error;
|
||||||
} while (!(status & MMCI_BIT(RXRDY)));
|
} while (!(status & MMCI_BIT(RXRDY)));
|
||||||
|
|
||||||
if (status & MMCI_BIT(RXRDY)) {
|
if (status & MMCI_BIT(RXRDY)) {
|
||||||
|
@ -244,9 +244,10 @@ out:
|
||||||
mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
|
mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
|
||||||
return i;
|
return i;
|
||||||
|
|
||||||
fail:
|
read_error:
|
||||||
mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
|
mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
|
||||||
printf("mmc: bread failed, card status = %08x\n", card_status);
|
printf("mmc: bread failed, status = %08x, card status = %08x\n",
|
||||||
|
status, card_status);
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue