Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl
Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis
with 3 independent TEMPEST zones. Two independent P2020 computers may
be found inside each zone. Complete hardware support is included.
High-level hardware overview:
* DO-160 certified for passenger aircraft (noncritical)
* TEMPEST ceritified for RED/BLACK separation
* 3 zones per chassis, 2 computers per zone (total of 6)
* Dual-core 1.066GHz P2020 per computer
* One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB)
* Removable 80GB or 160GB Intel X18-M SSD per computer
* Front-accessible dual-port E1000E per computer
* Front-accessible serial console per computer
* Front-accessible USB port per computer
* Internal Gigabit crossover within each TEMPEST zone
* Internal unidirectional fiber links across TEMPEST zones
* Battery-backed DS1339 I2C RTC on each CPU.
Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz,
12 front-accessible Gigabit Ethernet ports and 960GB of solid-state
storage with a total power consumption of ~200W.
Additional notes:
* SPD detection is only known to work with the DO-160-certified DIMMs
* CPU reset is a little quirky due to hardware misfeature. Proper
support for the hardware reset mechanism has been left for a later
patch series to address.
Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun