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9 Commits (ff9c4c535a8b722c54d45e77aa083fa08552341d)

Author SHA1 Message Date
Stefan Roese ff9c4c535a fpga: altera: Add StratixV support
This patch adds support for programming of the StratixV FPGAs. Programming
is done in this case (board theadorable) via SPI. The board may provide
board specific code for bitstream programming.

This StratixV support will be used by the theadorable board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:47:43 +01:00
Pavel Machek 230fe9b202 arm: socfpga: fpga: Add SoCFPGA FPGA programming interface
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

V2: Move the not-CPU specific stuff into drivers/fpga/ and base
    this on the cleaned up altera FPGA support.
2014-10-06 17:46:50 +02:00
Masahiro Yamada 7b6af41ef3 drivers: descend into sub directories only when it is necessary
- Descend into drivers/fpga/ only when CONFIG_FPGA=y
  - Descend into drivers/bios_emulator only when CONFIG_BIOSEMU=y

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-11-17 14:11:30 -05:00
Masahiro Yamada 710f1d3d5f drivers: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2013-10-31 13:26:01 -04:00
Wolfgang Denk 1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Michal Simek d5dae85f23 fpga: zynq: Add support for loading bitstream
Devcfg device requires to load bitstream in binary format.
But u-boot also has an option for loading bitstream in bit
format. Let's handle both cases by zynqpl driver.
Also add suport for loading partial bitstreams.

The first driver version was done by:
Joe Hershberger <joe.hershberger@ni.com>

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
2013-05-06 10:41:24 +02:00
Sebastien Carlier 6d8962e814 Switch from archive libraries to partial linking
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils.  As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".

This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.

The name of each former library archive is preserved except for
extensions which change from ".a" to ".o".  This commit updates
references accordingly where needed, in particular in some linker
scripts.

This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols.  Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.

Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
2010-11-17 21:02:18 +01:00
Stefano Babic 3b8ac464f2 FPGA: add support for downloading Lattice bitstream
The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.

The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.

Signed-off-by: Stefano Babic <sbabic@denx.de>
2010-10-13 18:09:31 +02:00
Jean-Christophe PLAGNIOL-VILLARD c8aa7dfc18 FPGA: move fpga drivers to drivers/fpga
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-12-05 22:41:33 +01:00