71398b89a0
Update the ddrc Qos setting for B1 to align with B0'ssetting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit 566b798213ab9690966f163de2765acdbfe647a7) |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| imx8mq_evk.c | ||
| lpddr4_timing.c | ||
| lpddr4_timing_b0.c | ||
| spl.c | ||