Bai Ping 71398b89a0 MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip ... Update the ddrc Qos setting for B1 to align with B0'ssetting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com> (cherry picked from commit 566b798213ab9690966f163de2765acdbfe647a7)		2018-11-20 18:28:22 +08:00
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altera	ddr: altera: silence PHY calibration unless in debug mode	2018-01-25 09:59:37 +01:00
fsl	Revert "drivers/ddr/fsl: Dual-license DDR driver"	2018-02-14 21:34:05 -05:00
imx8m	MLK-20394 imx8mq: Update the ddrc QoS setting for B1 chip	2018-11-20 18:28:22 +08:00
marvell	ddr: marvell: update ddr controller init and freq	2018-01-19 16:30:29 +01:00
microchip	wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2018-01-24 12:03:43 +05:30
Kconfig	arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig	2017-04-14 14:06:57 +02:00