45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* Copyright (C) 2016 ARM Ltd.
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*
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* ARM and ARM64 barrier instructions
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* split from armv7.h to allow sharing between ARM and ARM64
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*
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* Original copyright in armv7.h was:
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* (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh@ti.com>
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*
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* Much of the original barrier code was contributed by:
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* Valentine Barshak <valentine.barshak@cogentembedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __BARRIERS_H__
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#define __BARRIERS_H__
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#ifndef __ASSEMBLY__
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#ifndef CONFIG_ARM64
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/*
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* CP15 Barrier instructions
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* Please note that we have separate barrier instructions in ARMv7
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* However, we use the CP15 based instructtions because we use
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* -march=armv5 in U-Boot
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*/
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#define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0))
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#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
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#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
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#endif /* !CONFIG_ARM64 */
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#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64)
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#define ISB asm volatile ("isb sy" : : : "memory")
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#define DSB asm volatile ("dsb sy" : : : "memory")
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#define DMB asm volatile ("dmb sy" : : : "memory")
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#else
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#define ISB CP15ISB
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#define DSB CP15DSB
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#define DMB CP15DMB
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BARRIERS_H__ */
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