42 lines
1.0 KiB
C
42 lines
1.0 KiB
C
/*
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* Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2012 Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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void lowlevel_init(void)
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{
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zynq_slcr_unlock();
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/* remap DDR to zero, FILTERSTART */
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writel(0, &scu_base->filter_start);
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/* Device config APB, unlock the PCAP */
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writel(0x757BDF0D, &devcfg_base->unlock);
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writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
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/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
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writel(0x1F, &slcr_base->ocm_cfg);
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/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
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writel(0x0, &slcr_base->fpga_rst_ctrl);
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/* TZ_DDR_RAM, Set DDR trust zone non-secure */
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writel(0xFFFFFFFF, &slcr_base->trust_zone);
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/* Set urgent bits with register */
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writel(0x0, &slcr_base->ddr_urgent_sel);
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/* Urgent write, ports S2/S3 */
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writel(0xC, &slcr_base->ddr_urgent);
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zynq_slcr_lock();
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}
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void reset_cpu(ulong addr)
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{
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zynq_slcr_cpu_reset();
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while (1)
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;
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}
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