52 lines
977 B
C
52 lines
977 B
C
/*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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/* Tegra vpr routines */
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/mc.h>
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#include <fdt_support.h>
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static bool _configured;
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void tegra_gpu_config(void)
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{
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struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
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/* Turn VPR off */
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writel(0, &mc->mc_video_protect_size_mb);
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writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
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&mc->mc_video_protect_reg_ctrl);
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/* read back to ensure the write went through */
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readl(&mc->mc_video_protect_reg_ctrl);
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debug("configured VPR\n");
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_configured = true;
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}
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#if defined(CONFIG_OF_LIBFDT)
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int tegra_gpu_enable_node(void *blob, const char *gpupath)
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{
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int offset;
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if (_configured) {
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offset = fdt_path_offset(blob, gpupath);
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if (offset > 0) {
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fdt_status_okay(blob, offset);
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debug("enabled GPU node %s\n", gpupath);
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}
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}
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return 0;
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}
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#endif
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