559 lines
13 KiB
C
559 lines
13 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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* Copyright (C) 2019 reMarkable AS
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*
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* SPDX-License-Identifier: GPL-2.0+
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* Author: Lars Miljeteig <lars.ivar.miljeteig@remarkable.com>
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*
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../../freescale/common/pfuze.h"
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#include <i2c.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/crm_regs.h>
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#include <command.h>
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#include <dm/uclass.h>
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#include <asm/mach-imx/video.h>
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#ifdef CONFIG_FSL_FASTBOOT
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#include <fsl_fastboot.h>
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#ifdef CONFIG_ANDROID_RECOVERY
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#include <recovery.h>
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#endif
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#endif /*CONFIG_FSL_FASTBOOT*/
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
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PAD_CTL_DSE_3P3V_49OHM)
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#define BUTTON_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_DSE_3P3V_98OHM)
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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static iomux_v3_cfg_t const wdog_pads[] = {
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MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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#define BOARD_REV_C 0x300
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#define BOARD_REV_B 0x200
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#define BOARD_REV_A 0x100
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static int mx7sabre_rev(void)
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{
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/*
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* Get Board ID information from OCOTP_GP1[15:8]
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* i.MX7D SDB RevA: 0x41
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* i.MX7D SDB RevB: 0x42
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*/
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[14];
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int reg = readl(&bank->fuse_regs[0]);
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int ret;
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if (reg != 0) {
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switch (reg >> 8 & 0x0F) {
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case 0x3:
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ret = BOARD_REV_C;
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break;
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case 0x02:
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ret = BOARD_REV_B;
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break;
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case 0x01:
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default:
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ret = BOARD_REV_A;
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break;
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}
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} else {
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/* If the gp1 fuse is not burn, we have to use TO rev for the board rev */
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if (is_soc_rev(CHIP_REV_1_0))
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ret = BOARD_REV_A;
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else if (is_soc_rev(CHIP_REV_1_1))
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ret = BOARD_REV_B;
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else
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ret = BOARD_REV_C;
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}
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return ret;
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}
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u32 get_board_rev(void)
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{
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int rev = mx7sabre_rev();
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return (get_cpu_rev() & ~(0xF << 8)) | rev;
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}
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#ifdef CONFIG_VIDEO_MXS
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static iomux_v3_cfg_t const lcd_pads[] = {
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MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
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};
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static iomux_v3_cfg_t const pwm_pads[] = {
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/* Use GPIO for Brightness adjustment, duty cycle = period */
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MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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void do_enable_parallel_lcd(struct display_info_t const *dev)
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{
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imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
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imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
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}
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struct display_info_t const displays[] = {{
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.bus = ELCDIF1_IPS_BASE_ADDR,
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.addr = 0,
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.pixfmt = 24,
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.detect = NULL,
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.enable = do_enable_parallel_lcd,
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.mode = {
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.name = "TFT43AB",
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.xres = 480,
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.yres = 272,
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.pixclock = 108695,
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.left_margin = 8,
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.right_margin = 4,
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.upper_margin = 2,
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.lower_margin = 4,
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.hsync_len = 41,
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.vsync_len = 10,
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.sync = 0,
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.vmode = FB_VMODE_NONINTERLACED
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} } };
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size_t display_count = ARRAY_SIZE(displays);
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#endif
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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int board_mmc_get_env_dev(int devno)
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{
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if (devno == 2)
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devno--;
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return devno;
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}
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int mmc_map_to_kernel_blk(int dev_no)
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{
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if (dev_no == 1)
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dev_no++;
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return dev_no;
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}
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#ifdef CONFIG_FEC_MXC
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static int setup_fec(int fec_id)
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{
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struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
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= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
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int ret;
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unsigned int gpio;
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ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio);
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if (ret) {
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printf("GPIO: 'gpio_spi@0_5' not found\n");
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return -ENODEV;
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}
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ret = gpio_request(gpio, "enet_phy_rst");
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if (ret && ret != -EBUSY) {
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printf("gpio: requesting pin %u failed\n", gpio);
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return ret;
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}
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gpio_direction_output(gpio, 0);
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udelay(500);
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gpio_direction_output(gpio, 1);
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if (0 == fec_id) {
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/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
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(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
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IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
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} else {
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/* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
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(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
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IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
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if (mx7sabre_rev() >= BOARD_REV_B) {
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/* On RevB, GPIO1_IO04 is used for ENET2 EN,
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* so set its output to low to enable ENET2 signals
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*/
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gpio_request(IMX_GPIO_NR(1, 4), "fec2_en");
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gpio_direction_output(IMX_GPIO_NR(1, 4), 0);
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}
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}
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return set_clk_enet(ENET_125MHZ);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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#define SY7636A_I2C_BUS 3
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#define SY7636A_I2C_ADDR 0x62
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#define SY7636A_REG_OPERATIONMODE 0x00
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#define SY7636A_OPERATIONMODE_ONOFF 0x80
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#define SY7636A_OPERATIONMODE_VCOMCTRL 0x40
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#define SY7636A_REG_VCOMADJUST_L 0x01
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#define SY7636A_REG_VCOMADJUST_H 0x02
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#define SY7636A_VCOMADJUST_LMASK 0xff
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#define SY7636A_VCOMADJUST_HMASK 0x80
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static int sy7636a_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data)
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{
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u8 valb;
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int ret;
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if (mask != 0xff) {
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ret = dm_i2c_read(dev, addr, &valb, 1);
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if (ret)
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return ret;
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valb &= ~mask;
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valb |= data;
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} else {
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valb = data;
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}
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ret = dm_i2c_write(dev, addr, &valb, 1);
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return ret;
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}
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static int sy7636a_i2c_reg_read(struct udevice *dev, u8 addr, u8 *data)
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{
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u8 valb;
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int ret;
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ret = dm_i2c_read(dev, addr, &valb, 1);
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if (ret)
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return ret;
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*data = (int)valb;
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return 0;
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}
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static int sy7636a_vcom_get(struct udevice *dev, int *vcom)
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{
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u8 low, high;
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int ret;
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ret = sy7636a_i2c_reg_read(dev, SY7636A_REG_VCOMADJUST_L, &low);
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if (ret)
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return ret;
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ret = sy7636a_i2c_reg_read(dev, SY7636A_REG_VCOMADJUST_H, &high);
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if (ret)
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return ret;
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low &= SY7636A_VCOMADJUST_LMASK;
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high &= SY7636A_VCOMADJUST_HMASK;
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*vcom = -10 * (low | ((u16)high << 1));
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*vcom = (*vcom < -5000) ? -5000 : *vcom;
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return 0;
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}
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static int sy7636a_vcom_set(struct udevice *dev, int vcom)
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{
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u8 high, low;
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int ret;
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if (vcom < 0)
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vcom = -vcom;
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vcom /= 10;
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if (vcom > 0x01FF)
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return -EINVAL;
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low = vcom & SY7636A_VCOMADJUST_LMASK;
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high = ((u16)vcom >> 1) & SY7636A_VCOMADJUST_HMASK;
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ret = sy7636a_i2c_reg_write(dev, SY7636A_REG_VCOMADJUST_L, SY7636A_VCOMADJUST_LMASK, low);
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if (ret)
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return ret;
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return sy7636a_i2c_reg_write(dev, SY7636A_REG_VCOMADJUST_H, SY7636A_VCOMADJUST_HMASK, high);
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}
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static int do_epd_power_on(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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struct udevice *bus, *dev;
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u8 mask, val;
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ulong vcom;
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int ivcom;
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_I2C, SY7636A_I2C_BUS, &bus);
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if (ret) {
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printf("%s: No bus %d\n", __func__, SY7636A_I2C_BUS);
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return -1;
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}
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ret = dm_i2c_probe(bus, SY7636A_I2C_ADDR, 0, &dev);
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if (ret) {
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printf("%s: Can't find device id=0x%x, on bus %d\n",
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__func__, SY7636A_I2C_ADDR, SY7636A_I2C_BUS);
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return -1;
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}
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ret = sy7636a_vcom_get(dev, &ivcom);
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if (ret)
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return ret;
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vcom = env_get_ulong("vcom", 10, 1250);
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printf("vcom was %dmV, setting to -%lumV\n", ivcom, vcom);
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ret = sy7636a_vcom_set(dev, vcom);
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if (ret)
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return ret;
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/* Power on, include VCOM in power sequence */
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mask = (SY7636A_OPERATIONMODE_ONOFF | SY7636A_OPERATIONMODE_VCOMCTRL);
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val = SY7636A_OPERATIONMODE_ONOFF;
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return sy7636a_i2c_reg_write(dev, SY7636A_REG_OPERATIONMODE, mask, val);
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}
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U_BOOT_CMD(
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epd_power_on, 1, 1, do_epd_power_on,
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"Turn on power for eInk Display",
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""
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);
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_FEC_MXC
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setup_fec(CONFIG_FEC_ENET_DEV);
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#endif
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return 0;
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}
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#ifdef CONFIG_CMD_BMODE
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static const struct boot_mode board_boot_modes[] = {
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/* 4 bit bus width */
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{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
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{"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
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/* TODO: Nand */
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{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
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{NULL, 0},
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};
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#endif
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#ifdef CONFIG_DM_PMIC
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret, dev_id, rev_id;
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u32 sw3mode;
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ret = pmic_get("pfuze3000", &dev);
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if (ret == -ENODEV)
|
|
return 0;
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
|
|
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
|
|
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
|
|
|
|
pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
|
|
|
|
/*
|
|
* Set the voltage of VLDO4 output to 2.8V which feeds
|
|
* the MIPI DSI and MIPI CSI inputs.
|
|
*/
|
|
pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
|
|
|
|
/* change sw3 mode to avoid DDR power off */
|
|
sw3mode = pmic_reg_read(dev, PFUZE3000_SW3MODE);
|
|
ret = pmic_reg_write(dev, PFUZE3000_SW3MODE, sw3mode | 0x20);
|
|
if (ret < 0)
|
|
printf("PMIC: PFUZE3000 change sw3 mode failed\n");
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_late_init(void)
|
|
{
|
|
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
|
#ifdef CONFIG_CMD_BMODE
|
|
add_board_boot_modes(board_boot_modes);
|
|
#endif
|
|
|
|
env_set("tee", "no");
|
|
#ifdef CONFIG_IMX_OPTEE
|
|
env_set("tee", "yes");
|
|
#endif
|
|
|
|
#ifdef CONFIG_ENV_IS_IN_MMC
|
|
board_late_mmc_env_init();
|
|
#endif
|
|
|
|
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
|
|
|
set_wdog_reset(wdog);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
int rev = mx7sabre_rev();
|
|
char *mode;
|
|
char *revname;
|
|
|
|
if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
|
|
mode = "secure";
|
|
else
|
|
mode = "non-secure";
|
|
|
|
switch (rev) {
|
|
case BOARD_REV_C:
|
|
revname = "C";
|
|
break;
|
|
case BOARD_REV_B:
|
|
revname = "B";
|
|
break;
|
|
case BOARD_REV_A:
|
|
default:
|
|
revname = "A";
|
|
break;
|
|
}
|
|
|
|
printf("Board: i.MX7D SABRESD Rev%s in %s mode\n", revname, mode);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_FSL_FASTBOOT
|
|
#ifdef CONFIG_ANDROID_RECOVERY
|
|
|
|
/* Use S3 button for recovery key */
|
|
#define GPIO_VOL_DN_KEY IMX_GPIO_NR(5, 10)
|
|
iomux_v3_cfg_t const recovery_key_pads[] = {
|
|
(MX7D_PAD_SD2_WP__GPIO5_IO10 | MUX_PAD_CTRL(BUTTON_PAD_CTRL)),
|
|
};
|
|
|
|
int is_recovery_key_pressing(void)
|
|
{
|
|
int button_pressed = 0;
|
|
|
|
/* Check Recovery Combo Button press or not. */
|
|
imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
|
|
ARRAY_SIZE(recovery_key_pads));
|
|
|
|
gpio_request(GPIO_VOL_DN_KEY, "volume_dn_key");
|
|
gpio_direction_input(GPIO_VOL_DN_KEY);
|
|
|
|
if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
|
|
button_pressed = 1;
|
|
printf("Recovery key pressed\n");
|
|
}
|
|
|
|
return button_pressed;
|
|
}
|
|
|
|
#endif /*CONFIG_ANDROID_RECOVERY*/
|
|
#endif /*CONFIG_FSL_FASTBOOT*/
|