![wdenk](/assets/img/avatar_default.png)
* Patch by Curt Brune, 17 May 2004: - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC) - Add support for ESPD-Inc. EVB4510 Board
158 lines
4.6 KiB
ArmAsm
158 lines
4.6 KiB
ArmAsm
/*
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* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
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* Curt Brune <curt@cucy.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/hardware.h>
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/***********************************************************************
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* Configure Memory Map
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*
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* This memory map allows us to relocate from FLASH to SRAM. After
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* power-on reset the CPU only knows about the FLASH memory at address
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* 0x00000000. After memsetup completes the memory map will be:
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*
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* Memory Addr
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* 0x00000000
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* to 8MB SRAM (U5) -- 8MB Map
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* 0x00800000
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*
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* 0x01000000
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* to 2MB Flash @ 0x00000000 (U7) -- 2MB Map
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* 0x01200000
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*
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* 0x02000000
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* to 512KB Flash @ 0x02000000 (U9) -- 2MB Map
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* 0x02080000
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*
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* Load all 12 memory registers with the STMIA instruction since
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* memory access is disabled once these registers are written. The
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* last register written re-enables memory access. For more info see
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* the user's manual for the S3C4510B, available from Samsung's web
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* site. Search for part number "S3C4510B".
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*
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***********************************************************************/
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.globl memsetup
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memsetup:
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/* preserve the temp register (r12 AKA ip) and remap it. */
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ldr r1, =SRAM_BASE+0xC
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add r0, r12, #0x01000000
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str r0, [r1]
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/* remap the link register for when we return */
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add lr, lr, #0x01000000
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/* store a short program in the on chip SRAM, which is
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* unaffected when remapping memory. Note the cache must be
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* disabled for the on chip SRAM to be available.
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*/
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ldr r1, =SRAM_BASE
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ldr r0, =0xe8801ffe /* stmia r0, {r1-r12} */
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str r0, [r1]
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add r1, r1, #4
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ldr r0, =0xe59fc000 /* ldr r12, [pc, #0] */
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str r0, [r1]
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add r1, r1, #4
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ldr r0, =0xe1a0f00e /* mov pc, lr */
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str r0, [r1]
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adr r0, memory_map_data
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ldmia r0, {r1-r12}
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ldr r0, =REG_EXTDBWTH
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ldr pc, =SRAM_BASE
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.globl reset_cpu
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reset_cpu:
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/*
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* reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
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* address 0x0. We accomplish this by storing a few
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* instructions into the on chip SRAM (8KB) and run from
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* there. Note the cache must be disabled for the on chip
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* SRAM to be available.
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*
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* load r2 with REG_ROMCON0
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* load r3 with 0x12040060 configure FLASH bank 0 @ 0x00000000
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* load r4 with REG_DRAMCON0
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* load r5 with 0x08000380 configure RAM bank 0 @ 0x01000000
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* load r6 with REG_REFEXTCON
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* load r7 with 0x9c218360
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* load r8 with 0x0
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* store str r3,[r2] @ SRAM_BASE
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* store str r5,[r4] @ SRAM_BASE + 0x4
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* store str r7,[r6] @ SRAM_BASE + 0x8
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* store mov pc,r8 @ SRAM_BASE + 0xC
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* mov pc, SRAM_BASE
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*
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*/
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/* disable cache */
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ldr r0, =REG_SYSCFG
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ldr r1, =0x83ffffa0 /* cache-disabled */
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str r1, [r0]
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ldr r2, =REG_ROMCON0
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ldr r3, =0x02000060 /* Bank0 2MB FLASH @ 0x00000000 */
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ldr r4, =REG_DRAMCON0
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ldr r5, =0x18040380 /* DRAM0 8MB SRAM @ 0x01000000 */
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ldr r6, =REG_REFEXTCON
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ldr r7, =0xce278360
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ldr r8, =0x00000000
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ldr r1, =SRAM_BASE
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ldr r0, =0xe5823000 /* str r3, [r2] */
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str r0, [r1]
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ldr r1, =SRAM_BASE+4
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ldr r0, =0xe5845000 /* str r5, [r4] */
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str r0, [r1]
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ldr r1, =SRAM_BASE+8
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ldr r0, =0xe5867000 /* str r7, [r6] */
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str r0, [r1]
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ldr r1, =SRAM_BASE+0xC
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ldr r0, =0xe1a0f008 /* mov pc, r8 */
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str r0, [r1]
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ldr r1, =SRAM_BASE
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mov pc, r1
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/* never return */
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/************************************************************************
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* Below are twelve 32-bit values for the twelve memory registers of
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* the system manager, starting with register REG_EXTDBWTH.
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***********************************************************************/
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memory_map_data:
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.long 0x00f03005 /* memory widths */
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.long 0x12040060 /* Bank0 2MB FLASH @ 0x01000000 */
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.long 0x22080060 /* Bank1 512KB FLASH @ 0x02000000 */
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.long 0x00000000
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.long 0x00000000
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.long 0x00000000
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.long 0x00000000
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.long 0x08000380 /* DRAM0 8MB SRAM @ 0x00000000 */
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.long 0x00000000
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.long 0x00000000
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.long 0x00000000
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.long 0x9c218360 /* enable memory */
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