333 lines
9.4 KiB
Plaintext
333 lines
9.4 KiB
Plaintext
menu "x86 architecture"
|
|
depends on X86
|
|
|
|
config SYS_ARCH
|
|
default "x86"
|
|
|
|
choice
|
|
prompt "Mainboard vendor"
|
|
default VENDOR_EMULATION
|
|
|
|
config VENDOR_COREBOOT
|
|
bool "coreboot"
|
|
|
|
config VENDOR_EMULATION
|
|
bool "emulation"
|
|
|
|
config VENDOR_GOOGLE
|
|
bool "Google"
|
|
|
|
config VENDOR_INTEL
|
|
bool "Intel"
|
|
|
|
endchoice
|
|
|
|
# board-specific options below
|
|
source "board/coreboot/Kconfig"
|
|
source "board/emulation/Kconfig"
|
|
source "board/google/Kconfig"
|
|
source "board/intel/Kconfig"
|
|
|
|
# platform-specific options below
|
|
source "arch/x86/cpu/baytrail/Kconfig"
|
|
source "arch/x86/cpu/coreboot/Kconfig"
|
|
source "arch/x86/cpu/ivybridge/Kconfig"
|
|
source "arch/x86/cpu/qemu/Kconfig"
|
|
source "arch/x86/cpu/quark/Kconfig"
|
|
source "arch/x86/cpu/queensbay/Kconfig"
|
|
|
|
# architecture-specific options below
|
|
|
|
config SYS_MALLOC_F_LEN
|
|
default 0x800
|
|
|
|
config RAMBASE
|
|
hex
|
|
default 0x100000
|
|
|
|
config XIP_ROM_SIZE
|
|
hex
|
|
depends on X86_RESET_VECTOR
|
|
default ROM_SIZE
|
|
|
|
config CPU_ADDR_BITS
|
|
int
|
|
default 36
|
|
|
|
config HPET_ADDRESS
|
|
hex
|
|
default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
|
|
|
|
config SMM_TSEG
|
|
bool
|
|
default n
|
|
|
|
config SMM_TSEG_SIZE
|
|
hex
|
|
|
|
config X86_RESET_VECTOR
|
|
bool
|
|
default n
|
|
|
|
config SYS_X86_START16
|
|
hex
|
|
depends on X86_RESET_VECTOR
|
|
default 0xfffff800
|
|
|
|
config BOARD_ROMSIZE_KB_512
|
|
bool
|
|
config BOARD_ROMSIZE_KB_1024
|
|
bool
|
|
config BOARD_ROMSIZE_KB_2048
|
|
bool
|
|
config BOARD_ROMSIZE_KB_4096
|
|
bool
|
|
config BOARD_ROMSIZE_KB_8192
|
|
bool
|
|
config BOARD_ROMSIZE_KB_16384
|
|
bool
|
|
|
|
choice
|
|
prompt "ROM chip size"
|
|
depends on X86_RESET_VECTOR
|
|
default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
|
|
default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
|
|
default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
|
|
default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
|
|
default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
|
|
default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
|
|
help
|
|
Select the size of the ROM chip you intend to flash U-Boot on.
|
|
|
|
The build system will take care of creating a u-boot.rom file
|
|
of the matching size.
|
|
|
|
config UBOOT_ROMSIZE_KB_512
|
|
bool "512 KB"
|
|
help
|
|
Choose this option if you have a 512 KB ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_1024
|
|
bool "1024 KB (1 MB)"
|
|
help
|
|
Choose this option if you have a 1024 KB (1 MB) ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_2048
|
|
bool "2048 KB (2 MB)"
|
|
help
|
|
Choose this option if you have a 2048 KB (2 MB) ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_4096
|
|
bool "4096 KB (4 MB)"
|
|
help
|
|
Choose this option if you have a 4096 KB (4 MB) ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_8192
|
|
bool "8192 KB (8 MB)"
|
|
help
|
|
Choose this option if you have a 8192 KB (8 MB) ROM chip.
|
|
|
|
config UBOOT_ROMSIZE_KB_16384
|
|
bool "16384 KB (16 MB)"
|
|
help
|
|
Choose this option if you have a 16384 KB (16 MB) ROM chip.
|
|
|
|
endchoice
|
|
|
|
# Map the config names to an integer (KB).
|
|
config UBOOT_ROMSIZE_KB
|
|
int
|
|
default 512 if UBOOT_ROMSIZE_KB_512
|
|
default 1024 if UBOOT_ROMSIZE_KB_1024
|
|
default 2048 if UBOOT_ROMSIZE_KB_2048
|
|
default 4096 if UBOOT_ROMSIZE_KB_4096
|
|
default 8192 if UBOOT_ROMSIZE_KB_8192
|
|
default 16384 if UBOOT_ROMSIZE_KB_16384
|
|
|
|
# Map the config names to a hex value (bytes).
|
|
config ROM_SIZE
|
|
hex
|
|
default 0x80000 if UBOOT_ROMSIZE_KB_512
|
|
default 0x100000 if UBOOT_ROMSIZE_KB_1024
|
|
default 0x200000 if UBOOT_ROMSIZE_KB_2048
|
|
default 0x400000 if UBOOT_ROMSIZE_KB_4096
|
|
default 0x800000 if UBOOT_ROMSIZE_KB_8192
|
|
default 0xc00000 if UBOOT_ROMSIZE_KB_12288
|
|
default 0x1000000 if UBOOT_ROMSIZE_KB_16384
|
|
|
|
config HAVE_INTEL_ME
|
|
bool "Platform requires Intel Management Engine"
|
|
help
|
|
Newer higher-end devices have an Intel Management Engine (ME)
|
|
which is a very large binary blob (typically 1.5MB) which is
|
|
required for the platform to work. This enforces a particular
|
|
SPI flash format. You will need to supply the me.bin file in
|
|
your board directory.
|
|
|
|
config X86_RAMTEST
|
|
bool "Perform a simple RAM test after SDRAM initialisation"
|
|
help
|
|
If there is something wrong with SDRAM then the platform will
|
|
often crash within U-Boot or the kernel. This option enables a
|
|
very simple RAM test that quickly checks whether the SDRAM seems
|
|
to work correctly. It is not exhaustive but can save time by
|
|
detecting obvious failures.
|
|
|
|
config MARK_GRAPHICS_MEM_WRCOMB
|
|
bool "Mark graphics memory as write-combining"
|
|
default n
|
|
help
|
|
The graphics performance may increase if the graphics
|
|
memory is set as write-combining cache type. This option
|
|
enables marking the graphics memory as write-combining.
|
|
|
|
config HAVE_FSP
|
|
bool "Add an Firmware Support Package binary"
|
|
help
|
|
Select this option to add an Firmware Support Package binary to
|
|
the resulting U-Boot image. It is a binary blob which U-Boot uses
|
|
to set up SDRAM and other chipset specific initialization.
|
|
|
|
Note: Without this binary U-Boot will not be able to set up its
|
|
SDRAM so will not boot.
|
|
|
|
config FSP_FILE
|
|
string "Firmware Support Package binary filename"
|
|
depends on HAVE_FSP
|
|
default "fsp.bin"
|
|
help
|
|
The filename of the file to use as Firmware Support Package binary
|
|
in the board directory.
|
|
|
|
config FSP_ADDR
|
|
hex "Firmware Support Package binary location"
|
|
depends on HAVE_FSP
|
|
default 0xfffc0000
|
|
help
|
|
FSP is not Position Independent Code (PIC) and the whole FSP has to
|
|
be rebased if it is placed at a location which is different from the
|
|
perferred base address specified during the FSP build. Use Intel's
|
|
Binary Configuration Tool (BCT) to do the rebase.
|
|
|
|
The default base address of 0xfffc0000 indicates that the binary must
|
|
be located at offset 0xc0000 from the beginning of a 1MB flash device.
|
|
|
|
config FSP_TEMP_RAM_ADDR
|
|
hex
|
|
depends on HAVE_FSP
|
|
default 0x2000000
|
|
help
|
|
Stack top address which is used in FspInit after DRAM is ready and
|
|
CAR is disabled.
|
|
|
|
config MAX_CPUS
|
|
int "Maximum number of CPUs permitted"
|
|
default 4
|
|
help
|
|
When using multi-CPU chips it is possible for U-Boot to start up
|
|
more than one CPU. The stack memory used by all of these CPUs is
|
|
pre-allocated so at present U-Boot wants to know the maximum
|
|
number of CPUs that may be present. Set this to at least as high
|
|
as the number of CPUs in your system (it uses about 4KB of RAM for
|
|
each CPU).
|
|
|
|
config SMP
|
|
bool "Enable Symmetric Multiprocessing"
|
|
default n
|
|
help
|
|
Enable use of more than one CPU in U-Boot and the Operating System
|
|
when loaded. Each CPU will be started up and information can be
|
|
obtained using the 'cpu' command. If this option is disabled, then
|
|
only one CPU will be enabled regardless of the number of CPUs
|
|
available.
|
|
|
|
config AP_STACK_SIZE
|
|
hex
|
|
default 0x1000
|
|
help
|
|
Each additional CPU started by U-Boot requires its own stack. This
|
|
option sets the stack size used by each CPU and directly affects
|
|
the memory used by this initialisation process. Typically 4KB is
|
|
enough space.
|
|
|
|
config TSC_CALIBRATION_BYPASS
|
|
bool "Bypass Time-Stamp Counter (TSC) calibration"
|
|
default n
|
|
help
|
|
By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
|
|
running frequency via Model-Specific Register (MSR) and Programmable
|
|
Interval Timer (PIT). If the calibration does not work on your board,
|
|
select this option and provide a hardcoded TSC running frequency with
|
|
CONFIG_TSC_FREQ_IN_MHZ below.
|
|
|
|
Normally this option should be turned on in a simulation environment
|
|
like qemu.
|
|
|
|
config TSC_FREQ_IN_MHZ
|
|
int "Time-Stamp Counter (TSC) running frequency in MHz"
|
|
depends on TSC_CALIBRATION_BYPASS
|
|
default 1000
|
|
help
|
|
The running frequency in MHz of Time-Stamp Counter (TSC).
|
|
|
|
menu "System tables"
|
|
|
|
config GENERATE_PIRQ_TABLE
|
|
bool "Generate a PIRQ table"
|
|
default n
|
|
help
|
|
Generate a PIRQ routing table for this board. The PIRQ routing table
|
|
is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
|
|
at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
|
|
It specifies the interrupt router information as well how all the PCI
|
|
devices' interrupt pins are wired to PIRQs.
|
|
|
|
config GENERATE_SFI_TABLE
|
|
bool "Generate a SFI (Simple Firmware Interface) table"
|
|
help
|
|
The Simple Firmware Interface (SFI) provides a lightweight method
|
|
for platform firmware to pass information to the operating system
|
|
via static tables in memory. Kernel SFI support is required to
|
|
boot on SFI-only platforms. If you have ACPI tables then these are
|
|
used instead.
|
|
|
|
U-Boot writes this table in write_sfi_table() just before booting
|
|
the OS.
|
|
|
|
For more information, see http://simplefirmware.org
|
|
|
|
endmenu
|
|
|
|
config MAX_PIRQ_LINKS
|
|
int
|
|
default 8
|
|
help
|
|
This variable specifies the number of PIRQ interrupt links which are
|
|
routable. On most older chipsets, this is 4, PIRQA through PIRQD.
|
|
Some newer chipsets offer more than four links, commonly up to PIRQH.
|
|
|
|
config IRQ_SLOT_COUNT
|
|
int
|
|
default 128
|
|
help
|
|
U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
|
|
which in turns forms a table of exact 4KiB. The default value 128
|
|
should be enough for most boards. If this does not fit your board,
|
|
change it according to your needs.
|
|
|
|
config PCIE_ECAM_BASE
|
|
hex
|
|
default 0xe0000000
|
|
help
|
|
This is the memory-mapped address of PCI configuration space, which
|
|
is only available through the Enhanced Configuration Access
|
|
Mechanism (ECAM) with PCI Express. It can be set up almost
|
|
anywhere. Before it is set up, it is possible to access PCI
|
|
configuration space through I/O access, but memory access is more
|
|
convenient. Using this, PCI can be scanned and configured. This
|
|
should be set to a region that does not conflict with memory
|
|
assigned to PCI devices - i.e. the memory and prefetch regions, as
|
|
passed to pci_set_region().
|
|
|
|
endmenu
|