York Sun 938bbb6013 driver/ddr/fsl: Fix MRC_CYC calculation for DDR3 ... For DDR controller version 4.7 or newer, MRC_CYC (mode register set cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD is max(12nCK, 15ns) according to JEDEC spec. DDR4 is not affected by this change. Signed-off-by: York Sun <yorksun@freescale.com>		2014-12-15 09:15:12 -08:00
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Makefile	driver/ddr/fsl: Add DDR4 support to Freescale DDR driver	2014-04-22 17:58:48 -07:00
arm_ddr_gen3.c	fsl/sleep: updated the deep sleep framework for QorIQ platforms	2014-12-11 09:41:18 -08:00
ctrl_regs.c	driver/ddr/fsl: Fix MRC_CYC calculation for DDR3	2014-12-15 09:15:12 -08:00
ddr1_dimm_params.c	Driver/DDR: Moving Freescale DDR driver to a common driver	2013-11-25 11:43:43 -08:00
ddr2_dimm_params.c	Driver/DDR: Moving Freescale DDR driver to a common driver	2013-11-25 11:43:43 -08:00
ddr3_dimm_params.c	Driver/DDR: Moving Freescale DDR driver to a common driver	2013-11-25 11:43:43 -08:00
ddr4_dimm_params.c	driver/ddr/fsl: Add workaround for faulty SPD	2014-12-05 08:06:14 -08:00
fsl_ddr_gen4.c	fsl/sleep: updated the deep sleep framework for QorIQ platforms	2014-12-11 09:41:18 -08:00
interactive.c	driver/ddr/fsl: Fix tXP and tCKE	2014-09-25 08:36:18 -07:00
lc_common_dimm_params.c	linux/kernel.h: sync min, max, min3, max3 macros with Linux	2014-11-23 06:48:30 -05:00
main.c	linux/kernel.h: sync min, max, min3, max3 macros with Linux	2014-11-23 06:48:30 -05:00
mpc85xx_ddr_gen1.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen2.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen3.c	fsl/sleep: updated the deep sleep framework for QorIQ platforms	2014-12-11 09:41:18 -08:00
mpc86xx_ddr.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
options.c	driver/ddr/fsl: Fix tXP and tCKE	2014-09-25 08:36:18 -07:00
util.c	driver/ddr: Restruct driver to allow standalone memory space	2014-09-25 08:36:18 -07:00