371 lines
7.8 KiB
C
371 lines
7.8 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 (440 port)
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* Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <commproc.h>
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#include "vecnum.h"
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/****************************************************************************/
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/*
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* CPM interrupt vector functions.
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*/
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struct irq_action {
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interrupt_handler_t *handler;
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void *arg;
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int count;
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};
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static struct irq_action irq_vecs[32];
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#if defined(CONFIG_440)
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static struct irq_action irq_vecs1[32]; /* For UIC1 */
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void uic1_interrupt( void * parms); /* UIC1 handler */
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#endif
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/****************************************************************************/
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#if defined(CONFIG_440)
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/* SPRN changed in 440 */
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static __inline__ void set_evpr(unsigned long val)
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{
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asm volatile("mtspr 0x03f,%0" : : "r" (val));
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}
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#else /* !defined(CONFIG_440) */
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static __inline__ void set_pit(unsigned long val)
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{
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asm volatile("mtpit %0" : : "r" (val));
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}
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static __inline__ void set_tcr(unsigned long val)
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{
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asm volatile("mttcr %0" : : "r" (val));
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}
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static __inline__ void set_evpr(unsigned long val)
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{
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asm volatile("mtevpr %0" : : "r" (val));
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}
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#endif /* defined(CONFIG_440 */
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/****************************************************************************/
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int interrupt_init_cpu (unsigned *decrementer_count)
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{
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DECLARE_GLOBAL_DATA_PTR;
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int vec;
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unsigned long val;
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/* decrementer is automatically reloaded */
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*decrementer_count = 0;
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/*
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* Mark all irqs as free
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*/
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for (vec=0; vec<32; vec++) {
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irq_vecs[vec].handler = NULL;
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irq_vecs[vec].arg = NULL;
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irq_vecs[vec].count = 0;
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#if defined(CONFIG_440)
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irq_vecs1[vec].handler = NULL;
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irq_vecs1[vec].arg = NULL;
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irq_vecs1[vec].count = 0;
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#endif
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}
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#ifdef CONFIG_4xx
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/*
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* Init PIT
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*/
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#if defined(CONFIG_440)
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val = mfspr( tcr );
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val &= (~0x04400000); /* clear DIS & ARE */
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mtspr( tcr, val );
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mtspr( dec, 0 ); /* Prevent exception after TSR clear*/
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mtspr( decar, 0 ); /* clear reload */
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mtspr( tsr, 0x08000000 ); /* clear DEC status */
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val = gd->bd->bi_intfreq/100; /* 10 msec */
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mtspr( decar, val ); /* Set auto-reload value */
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mtspr( dec, val ); /* Set inital val */
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#else
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set_pit(gd->bd->bi_intfreq / 1000);
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#endif
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#endif /* CONFIG_4xx */
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#ifdef CONFIG_ADCIOP
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/*
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* Init PIT
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*/
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set_pit(66000);
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#endif
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/*
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* Enable PIT
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*/
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val = mfspr(tcr);
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val |= 0x04400000;
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mtspr(tcr, val);
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/*
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* Set EVPR to 0
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*/
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set_evpr(0x00000000);
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#if defined(CONFIG_440)
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/* Install the UIC1 handlers */
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irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0);
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irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0);
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#endif
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return (0);
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}
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/****************************************************************************/
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/*
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* Handle external interrupts
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*/
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void external_interrupt(struct pt_regs *regs)
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{
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ulong uic_msr;
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ulong msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic_msr = mfdcr(uicmsr);
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msr_shift = uic_msr;
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vec = 0;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs[vec].count++;
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if (irq_vecs[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs[vec].handler)(irq_vecs[vec].arg);
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} else {
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mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> vec));
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printf ("Masking bogus interrupt vector 0x%x\n", vec);
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}
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/*
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* After servicing the interrupt, we have to remove the status indicator.
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*/
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mtdcr(uicsr, (0x80000000 >> vec));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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#if defined(CONFIG_440)
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/* Handler for UIC1 interrupt */
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void uic1_interrupt( void * parms)
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{
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ulong uic1_msr;
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ulong msr_shift;
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int vec;
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/*
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* Read masked interrupt status register to determine interrupt source
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*/
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uic1_msr = mfdcr(uic1msr);
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msr_shift = uic1_msr;
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vec = 0;
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while (msr_shift != 0) {
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if (msr_shift & 0x80000000) {
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/*
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* Increment irq counter (for debug purpose only)
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*/
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irq_vecs1[vec].count++;
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if (irq_vecs1[vec].handler != NULL) {
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/* call isr */
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(*irq_vecs1[vec].handler)(irq_vecs1[vec].arg);
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} else {
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mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> vec));
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printf ("Masking bogus interrupt vector (uic1) 0x%x\n", vec);
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}
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/*
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* After servicing the interrupt, we have to remove the status indicator.
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*/
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mtdcr(uic1sr, (0x80000000 >> vec));
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}
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/*
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* Shift msr to next position and increment vector
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*/
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msr_shift <<= 1;
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vec++;
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}
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}
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#endif /* defined(CONFIG_440) */
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/****************************************************************************/
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/*
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* Install and free a interrupt handler.
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*/
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void
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irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
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{
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struct irq_action *irqa = irq_vecs;
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int i = vec;
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#if defined(CONFIG_440)
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if (vec > 31) {
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i = vec - 32;
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irqa = irq_vecs1;
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}
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#endif
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if (irqa[i].handler != NULL) {
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printf ("Interrupt vector %d: handler 0x%x replacing 0x%x\n",
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vec, (uint)handler, (uint)irqa[i].handler);
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}
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irqa[i].handler = handler;
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irqa[i].arg = arg;
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#if defined(CONFIG_440)
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if( vec > 31 )
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mtdcr(uic1er, mfdcr(uic1er) | (0x80000000 >> i));
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else
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#endif
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mtdcr(uicer, mfdcr(uicer) | (0x80000000 >> i));
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#if 0
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printf ("Install interrupt for vector %d ==> %p\n", vec, handler);
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#endif
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}
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void
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irq_free_handler(int vec)
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{
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struct irq_action *irqa = irq_vecs;
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int i = vec;
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#if defined(CONFIG_440)
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if (vec > 31) {
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irqa = irq_vecs1;
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i = vec - 32;
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}
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#endif
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#if 0
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printf ("Free interrupt for vector %d ==> %p\n",
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vec, irq_vecs[vec].handler);
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#endif
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#if defined(CONFIG_440)
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if (vec > 31)
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mtdcr(uic1er, mfdcr(uic1er) & ~(0x80000000 >> i));
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else
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#endif
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mtdcr(uicer, mfdcr(uicer) & ~(0x80000000 >> i));
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irqa[i].handler = NULL;
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irqa[i].arg = NULL;
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}
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/****************************************************************************/
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void timer_interrupt_cpu (struct pt_regs *regs)
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{
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/* nothing to do here */
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return;
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}
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/****************************************************************************/
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#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
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/*******************************************************************************
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*
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* irqinfo - print information about PCI devices
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*
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*/
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int
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do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int vec;
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printf ("\nInterrupt-Information:\n");
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#if defined(CONFIG_440)
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printf ("\nUIC 0\n");
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#endif
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printf ("Nr Routine Arg Count\n");
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for (vec=0; vec<32; vec++) {
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if (irq_vecs[vec].handler != NULL) {
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printf ("%02d %08lx %08lx %d\n",
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vec,
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(ulong)irq_vecs[vec].handler,
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(ulong)irq_vecs[vec].arg,
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irq_vecs[vec].count);
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}
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}
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#if defined(CONFIG_440)
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printf ("\nUIC 1\n");
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printf ("Nr Routine Arg Count\n");
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for (vec=0; vec<32; vec++)
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{
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if (irq_vecs1[vec].handler != NULL)
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printf ("%02d %08lx %08lx %d\n",
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vec+31, (ulong)irq_vecs1[vec].handler,
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(ulong)irq_vecs1[vec].arg, irq_vecs1[vec].count);
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}
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printf("\n");
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#endif
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return 0;
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}
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#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
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