160 lines
6.8 KiB
INI
160 lines
6.8 KiB
INI
/*
|
|
* Copyright (C) 2013 Freescale Semiconductor, Inc.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*
|
|
* Refer docs/README.imxmage for more details about how-to configure
|
|
* and create imximage boot image
|
|
*
|
|
* The syntax is taken as close as possible with the kwbimage
|
|
*/
|
|
|
|
/* image version */
|
|
|
|
IMAGE_VERSION 2
|
|
|
|
/*
|
|
* Boot Device : one of
|
|
* spi, sd (the board has no nand neither onenand)
|
|
*/
|
|
|
|
BOOT_FROM sd
|
|
|
|
/*
|
|
* Device Configuration Data (DCD)
|
|
*
|
|
* Each entry must have the format:
|
|
* Addr-type Address Value
|
|
*
|
|
* where:
|
|
* Addr-type register length (1,2 or 4 bytes)
|
|
* Address absolute address of the register
|
|
* value value to be stored in the register
|
|
*/
|
|
|
|
/* ============================================================================= */
|
|
/* Enable all clocks (they are disabled by ROM code) */
|
|
/* Full speed until we get calibrations */
|
|
/* ============================================================================= */
|
|
DATA 4 0x020c4068 0xffffffff
|
|
DATA 4 0x020c406c 0xffffffff
|
|
DATA 4 0x020c4070 0xffffffff
|
|
DATA 4 0x020c4074 0xffffffff
|
|
DATA 4 0x020c4078 0xffffffff
|
|
DATA 4 0x020c407c 0xffffffff
|
|
DATA 4 0x020c4080 0xffffffff
|
|
DATA 4 0x020c4084 0xffffffff
|
|
|
|
/* ============================================================================= */
|
|
/* IOMUX */
|
|
/* ============================================================================= */
|
|
/* DDR IO TYPE: */
|
|
DATA 4 0x020e0774 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
|
|
DATA 4 0x020e0754 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
|
|
|
|
/* CLOCK: */
|
|
DATA 4 0x020e04ac 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
|
|
DATA 4 0x020e04b0 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 */
|
|
|
|
/* ADDRESS: */
|
|
DATA 4 0x020e0464 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
|
|
DATA 4 0x020e0490 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
|
|
DATA 4 0x020e074c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
|
|
|
|
/* Control: */
|
|
DATA 4 0x020e0494 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
|
|
DATA 4 0x020e04a0 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS */
|
|
DATA 4 0x020e04b4 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 */
|
|
DATA 4 0x020e04b8 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 */
|
|
DATA 4 0x020e076c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
|
|
|
|
/* Data Strobes: */
|
|
DATA 4 0x020e0750 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
|
|
DATA 4 0x020e04bc 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 */
|
|
DATA 4 0x020e04c0 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 */
|
|
DATA 4 0x020e04c4 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 */
|
|
DATA 4 0x020e04c8 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 */
|
|
/* DATA 4 0x020e04cc 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 */
|
|
/* DATA 4 0x020e04d0 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 */
|
|
/* DATA 4 0x020e04d4 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 */
|
|
/* DATA 4 0x020e04d8 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 */
|
|
|
|
/* Data: */
|
|
DATA 4 0x020e0760 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
|
|
DATA 4 0x020e0764 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
|
|
DATA 4 0x020e0770 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
|
|
DATA 4 0x020e0778 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B2DS */
|
|
DATA 4 0x020e077c 0x00000028 /* IOMUXC_SW_PAD_CTL_GRP_B3DS */
|
|
/* DATA 4 0x020e0780 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B4DS */
|
|
/* DATA 4 0x020e0784 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B5DS */
|
|
/* DATA 4 0x020e078c 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B6DS */
|
|
/* DATA 4 0x020e0748 0x00000028 # IOMUXC_SW_PAD_CTL_GRP_B7DS */
|
|
|
|
DATA 4 0x020e0470 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
|
|
DATA 4 0x020e0474 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
|
|
DATA 4 0x020e0478 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 */
|
|
DATA 4 0x020e047c 0x00000028 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 */
|
|
/* DATA 4 0x020e0480 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 */
|
|
/* DATA 4 0x020e0484 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 */
|
|
/* DATA 4 0x020e0488 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 */
|
|
/* DATA 4 0x020e048c 0x00000028 # IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 */
|
|
|
|
|
|
/* ============================================================================= */
|
|
/* DDR Controller Registers */
|
|
/* ============================================================================= */
|
|
/* Manufacturer: Micron */
|
|
/* Device Part Number: MT41K128M16JT-125 */
|
|
/* Clock Freq.: 400MHz */
|
|
/* Density per CS in Gb: 4 */
|
|
/* Chip Selects used: 1 */
|
|
/* Number of Banks: 8 */
|
|
/* Row address: 14 */
|
|
/* Column address: 10 */
|
|
/* Data bus width 32 */
|
|
/* ============================================================================= */
|
|
DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
|
|
|
|
/* MMDC init: */
|
|
DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
|
|
DATA 4 0x021b0008 0x00333040 /* MMDC0_MDOTC */
|
|
DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
|
|
DATA 4 0x021b0010 0xB66D8B63 /* MMDC0_MDCFG1 */
|
|
DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
|
|
|
|
/* MDMISC: RALAT kept to the high level of 5. */
|
|
/* MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: */
|
|
/* a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 */
|
|
/* b. Small performence improvment */
|
|
DATA 4 0x021b0018 0x00011740 /* MMDC0_MDMISC */
|
|
DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit during MMDC set up */
|
|
DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
|
|
DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
|
|
DATA 4 0x021b0040 0x00000017 /* Chan0 CS0_END */
|
|
DATA 4 0x021b0000 0x83190000 /* MMDC0_MDCTL */
|
|
|
|
/* Mode register writes */
|
|
DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
|
|
DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
|
|
DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
|
|
DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0write, CS0 */
|
|
DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to device on CS0 */
|
|
|
|
/* DATA 4 0x021b001c 0x0200803A # MMDC0_MDSCR, MR2 write, CS1 */
|
|
/* DATA 4 0x021b001c 0x0000803B # MMDC0_MDSCR, MR3 write, CS1 */
|
|
/* DATA 4 0x021b001c 0x00048039 # MMDC0_MDSCR, MR1 write, CS1 */
|
|
/* DATA 4 0x021b001c 0x15208038 # MMDC0_MDSCR, MR0write, CS1 */
|
|
/* DATA 4 0x021b001c 0x04008048 # MMDC0_MDSCR, ZQ calibration command sent to device on CS1 */
|
|
|
|
DATA 4 0x021b0020 0x00007800 /* MMDC0_MDREF */
|
|
|
|
DATA 4 0x021b0818 0x00022227 /* DDR_PHY_P0_MPODTCTRL */
|
|
/* DATA 4 0x021b4818 0x00022227 # DDR_PHY_P1_MPODTCTRL */
|
|
|
|
DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
|
|
|
|
DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached. */
|
|
|
|
DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete) */
|
|
|