405 lines
10 KiB
C
405 lines
10 KiB
C
/*
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* board.c
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*
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* Board functions for TI AM43XX based boards
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/errno.h>
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#include <spl.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/gpio.h>
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#include <asm/emif.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Read header information from EEPROM into global structure.
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*/
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static int read_eeprom(struct am43xx_board_id *header)
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{
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/* Check if baseboard eeprom is available */
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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printf("Could not probe the EEPROM at 0x%x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return -ENODEV;
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}
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/* read the eeprom using i2c */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
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sizeof(struct am43xx_board_id))) {
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printf("Could not read the EEPROM\n");
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return -EIO;
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}
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if (header->magic != 0xEE3355AA) {
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/*
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* read the eeprom using i2c again,
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* but use only a 1 byte address
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*/
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
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sizeof(struct am43xx_board_id))) {
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printf("Could not read the EEPROM at 0x%x\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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return -EIO;
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}
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if (header->magic != 0xEE3355AA) {
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printf("Incorrect magic number (0x%x) in EEPROM\n",
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header->magic);
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return -EINVAL;
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}
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}
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strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
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am43xx_board_name[sizeof(header->name)] = 0;
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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#define NUM_OPPS 6
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const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
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{ /* 19.2 MHz */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP 100 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP 120 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP TB */
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{-1, -1, -1, -1, -1, -1, -1} /* OPP NT */
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},
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{ /* 24 MHz */
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{300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */
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{720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */
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{800, 23, 1, -1, -1, -1, -1}, /* OPP TB */
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{1000, 23, 1, -1, -1, -1, -1} /* OPP NT */
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},
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{ /* 25 MHz */
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{300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */
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{720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */
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{800, 24, 1, -1, -1, -1, -1}, /* OPP TB */
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{1000, 24, 1, -1, -1, -1, -1} /* OPP NT */
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},
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{ /* 26 MHz */
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{300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */
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{-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */
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{600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */
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{720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */
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{800, 25, 1, -1, -1, -1, -1}, /* OPP TB */
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{1000, 25, 1, -1, -1, -1, -1} /* OPP NT */
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},
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};
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const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = {
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{-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */
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{1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */
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{1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */
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};
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const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = {
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{-1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{960, 23, 5, -1, -1, -1, -1}, /* 24 MHz */
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{960, 24, 5, -1, -1, -1, -1}, /* 25 MHz */
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{960, 25, 5, -1, -1, -1, -1} /* 26 MHz */
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};
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const struct dpll_params epos_evm_dpll_ddr = {
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266, 24, 1, -1, 1, -1, -1};
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const struct dpll_params gp_evm_dpll_ddr = {
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400, 23, 1, -1, 1, -1, -1};
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const struct ctrl_ioregs ioregs_lpddr2 = {
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.cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE,
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.cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE,
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.cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE,
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.dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
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.dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE,
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.dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
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.dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE,
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.emif_sdram_config_ext = 0x1,
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};
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const struct emif_regs emif_regs_lpddr2 = {
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.sdram_config = 0x808012BA,
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.ref_ctrl = 0x0000040D,
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.sdram_tim1 = 0xEA86B411,
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.sdram_tim2 = 0x103A094A,
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.sdram_tim3 = 0x0F6BA37F,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x50074BE4,
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.temp_alert_config = 0x0,
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.emif_rd_wr_lvl_rmp_win = 0x0,
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.emif_rd_wr_lvl_rmp_ctl = 0x0,
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.emif_rd_wr_lvl_ctl = 0x0,
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.emif_ddr_phy_ctlr_1 = 0x0E084006,
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.emif_rd_wr_exec_thresh = 0x00000405,
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.emif_ddr_ext_phy_ctrl_1 = 0x04010040,
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.emif_ddr_ext_phy_ctrl_2 = 0x00500050,
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.emif_ddr_ext_phy_ctrl_3 = 0x00500050,
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.emif_ddr_ext_phy_ctrl_4 = 0x00500050,
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.emif_ddr_ext_phy_ctrl_5 = 0x00500050
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};
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const u32 ext_phy_ctrl_const_base_lpddr2[] = {
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0x00500050,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x40001000,
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0x08102040
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};
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const struct ctrl_ioregs ioregs_ddr3 = {
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.cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE,
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.cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE,
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.cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE,
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.dt0ioctl = DDR3_DATA0_IOCTRL_VALUE,
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.dt1ioctl = DDR3_DATA0_IOCTRL_VALUE,
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.dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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.dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE,
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.emif_sdram_config_ext = 0x0143,
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};
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const struct emif_regs ddr3_emif_regs_400Mhz = {
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.sdram_config = 0x638413B2,
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.ref_ctrl = 0x00000C30,
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.sdram_tim1 = 0xEAAAD4DB,
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.sdram_tim2 = 0x266B7FDA,
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.sdram_tim3 = 0x107F8678,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x50074BE4,
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.temp_alert_config = 0x0,
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.emif_ddr_phy_ctlr_1 = 0x0E084008,
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.emif_ddr_ext_phy_ctrl_1 = 0x08020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_3 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_4 = 0x00400040,
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.emif_ddr_ext_phy_ctrl_5 = 0x00400040,
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.emif_rd_wr_lvl_rmp_win = 0x0,
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.emif_rd_wr_lvl_rmp_ctl = 0x0,
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.emif_rd_wr_lvl_ctl = 0x0,
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.emif_rd_wr_exec_thresh = 0x00000405
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};
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const u32 ext_phy_ctrl_const_base_ddr3[] = {
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0x00400040,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00350035,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00340034,
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0x00340034,
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0x00340034,
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0x00340034,
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0x00340034,
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0x0,
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0x0,
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0x40000000,
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0x08102040
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};
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void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
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{
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if (board_is_eposevm()) {
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*regs = ext_phy_ctrl_const_base_lpddr2;
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*size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
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} else if (board_is_gpevm()) {
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*regs = ext_phy_ctrl_const_base_ddr3;
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*size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
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}
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return;
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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struct am43xx_board_id header;
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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if (board_is_eposevm())
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return &epos_evm_dpll_ddr;
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else if (board_is_gpevm())
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return &gp_evm_dpll_ddr;
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puts(" Board not supported\n");
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return NULL;
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}
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/*
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* get_sys_clk_index : returns the index of the sys_clk read from
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* ctrl status register. This value is either
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* read from efuse or sysboot pins.
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*/
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static u32 get_sys_clk_index(void)
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{
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struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
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u32 ind = readl(&ctrl->statusreg), src;
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src = (ind & CTRL_CRYSTAL_FREQ_SRC_MASK) >> CTRL_CRYSTAL_FREQ_SRC_SHIFT;
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if (src == CTRL_CRYSTAL_FREQ_SRC_EFUSE) /* Value read from EFUSE */
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return ((ind & CTRL_CRYSTAL_FREQ_SELECTION_MASK) >>
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CTRL_CRYSTAL_FREQ_SELECTION_SHIFT);
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else /* Value read from SYS BOOT pins */
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return ((ind & CTRL_SYSBOOT_15_14_MASK) >>
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CTRL_SYSBOOT_15_14_SHIFT);
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}
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/*
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* get_opp_offset:
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* Returns the index for safest OPP of the device to boot.
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* max_off: Index of the MAX OPP in DEV ATTRIBUTE register.
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* min_off: Index of the MIN OPP in DEV ATTRIBUTE register.
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* This data is read from dev_attribute register which is e-fused.
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* A'1' in bit indicates OPP disabled and not available, a '0' indicates
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* OPP available. Lowest OPP starts with min_off. So returning the
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* bit with rightmost '0'.
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*/
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static int get_opp_offset(int max_off, int min_off)
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{
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struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
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int opp = readl(&ctrl->dev_attr), offset, i;
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for (i = max_off; i >= min_off; i--) {
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offset = opp & (1 << i);
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if (!offset)
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return i;
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}
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return min_off;
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}
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const struct dpll_params *get_dpll_mpu_params(void)
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{
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int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET);
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u32 ind = get_sys_clk_index();
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return &dpll_mpu[ind][opp];
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}
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const struct dpll_params *get_dpll_core_params(void)
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{
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int ind = get_sys_clk_index();
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return &dpll_core[ind];
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}
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const struct dpll_params *get_dpll_per_params(void)
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{
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int ind = get_sys_clk_index();
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return &dpll_per[ind];
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}
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void set_uart_mux_conf(void)
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{
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enable_uart0_pin_mux();
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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static void enable_vtt_regulator(void)
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{
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u32 temp;
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/* enable module */
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writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
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/* enable output for GPIO5_7 */
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writel(GPIO_SETDATAOUT(7),
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AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
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temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
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temp = temp & ~(GPIO_OE_ENABLE(7));
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writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
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}
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void sdram_init(void)
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{
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/*
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* EPOS EVM has 1GB LPDDR2 connected to EMIF.
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* GP EMV has 1GB DDR3 connected to EMIF
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* along with VTT regulator.
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*/
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if (board_is_eposevm()) {
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config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
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} else if (board_is_gpevm()) {
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enable_vtt_regulator();
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config_ddr(0, &ioregs_ddr3, NULL, NULL,
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&ddr3_emif_regs_400Mhz, 0);
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}
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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char safe_string[HDR_NAME_LEN + 1];
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struct am43xx_board_id header;
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if (read_eeprom(&header) < 0)
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puts("Could not get board ID.\n");
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/* Now set variables based on the header. */
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strncpy(safe_string, (char *)header.name, sizeof(header.name));
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safe_string[sizeof(header.name)] = 0;
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setenv("board_name", safe_string);
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strncpy(safe_string, (char *)header.version, sizeof(header.version));
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safe_string[sizeof(header.version)] = 0;
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setenv("board_rev", safe_string);
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#endif
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return 0;
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}
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#endif
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