176 lines
3.9 KiB
C
176 lines
3.9 KiB
C
/* Initializes CPU and basic hardware such as memory
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* controllers, IRQ controller and system timer 0.
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*
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* (C) Copyright 2007, 2015
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* Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/asi.h>
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#include <asm/leon.h>
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#include <ambapp.h>
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#include <grlib/irqmp.h>
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#include <grlib/gptimer.h>
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#include <config.h>
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/* Default Plug&Play I/O area */
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#ifndef CONFIG_AMBAPP_IOAREA
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#define CONFIG_AMBAPP_IOAREA AMBA_DEFAULT_IOAREA
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#endif
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#define TIMER_BASE_CLK 1000000
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#define US_PER_TICK (1000000 / CONFIG_SYS_HZ)
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DECLARE_GLOBAL_DATA_PTR;
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/* reset CPU (jump to 0, without reset) */
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void start(void);
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ambapp_dev_irqmp *irqmp = NULL;
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ambapp_dev_gptimer *gptimer = NULL;
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unsigned int gptimer_irq = 0;
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int leon3_snooping_avail = 0;
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struct {
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gd_t gd_area;
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bd_t bd;
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} global_data;
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/*
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* Breath some life into the CPU...
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*
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* Run from FLASH/PROM:
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* - until memory controller is set up, only registers available
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* - memory controller has already been setup up, stack can be used
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* - no global variables available for writing
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* - constants available
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*/
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void cpu_init_f(void)
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{
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}
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/* Routine called from start.S,
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*
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* Run from FLASH/PROM:
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* - memory controller has already been setup up, stack can be used
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* - global variables available for read/writing
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* - constants avaiable
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*/
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void cpu_init_f2(void)
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{
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/* Initialize the AMBA Plug & Play bus structure, the bus
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* structure represents the AMBA bus that the CPU is located at.
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*/
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ambapp_bus_init(CONFIG_AMBAPP_IOAREA, CONFIG_SYS_CLK_FREQ, &ambapp_plb);
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}
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/*
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* initialize higher level parts of CPU like time base and timers
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*/
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int cpu_init_r(void)
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{
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ambapp_apbdev apbdev;
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int index, cpu;
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ambapp_dev_gptimer *timer = NULL;
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unsigned int bus_freq;
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/*
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* Find AMBA APB IRQMP Controller,
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*/
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if (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER,
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GAISLER_IRQMP, 0, &apbdev) != 1) {
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panic("%s: IRQ controller not found\n", __func__);
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return -1;
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}
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irqmp = (ambapp_dev_irqmp *)apbdev.address;
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/* initialize the IRQMP */
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irqmp->ilevel = 0xf; /* all IRQ off */
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irqmp->iforce = 0;
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irqmp->ipend = 0;
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irqmp->iclear = 0xfffe; /* clear all old pending interrupts */
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for (cpu = 0; cpu < 16; cpu++) {
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/* mask and clear force for all IRQs on CPU[N] */
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irqmp->cpu_mask[cpu] = 0;
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irqmp->cpu_force[cpu] = 0;
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}
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/* timer */
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index = 0;
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while (ambapp_apb_find(&ambapp_plb, VENDOR_GAISLER, GAISLER_GPTIMER,
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index, &apbdev) == 1) {
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timer = (ambapp_dev_gptimer *)apbdev.address;
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if (gptimer == NULL) {
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gptimer = timer;
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gptimer_irq = apbdev.irq;
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}
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/* Different buses may have different frequency, the
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* frequency of the bus tell in which frequency the timer
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* prescaler operates.
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*/
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bus_freq = ambapp_bus_freq(&ambapp_plb, apbdev.ahb_bus_index);
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/* initialize prescaler common to all timers to 1MHz */
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timer->scalar = timer->scalar_reload =
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(((bus_freq / 1000) + 500) / 1000) - 1;
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index++;
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}
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if (!gptimer) {
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printf("%s: gptimer not found!\n", __func__);
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return 1;
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}
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return 0;
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}
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/* Uses Timer 0 to get accurate
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* pauses. Max 2 raised to 32 ticks
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*
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*/
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void cpu_wait_ticks(unsigned long ticks)
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{
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unsigned long start = get_timer(0);
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while (get_timer(start) < ticks) ;
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}
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/* initiate and setup timer0 interrupt to configured HZ. Base clock is 1MHz.
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* Return irq number for timer int or a negative number for
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* dealing with self
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*/
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int timer_interrupt_init_cpu(void)
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{
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/* SYS_HZ ticks per second */
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gptimer->e[0].val = 0;
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gptimer->e[0].rld = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
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gptimer->e[0].ctrl =
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(GPTIMER_CTRL_EN | GPTIMER_CTRL_RS |
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GPTIMER_CTRL_LD | GPTIMER_CTRL_IE);
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return gptimer_irq;
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}
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ulong get_tbclk(void)
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{
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return TIMER_BASE_CLK;
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}
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/*
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* This function is intended for SHORT delays only.
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*/
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unsigned long cpu_usec2ticks(unsigned long usec)
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{
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if (usec < US_PER_TICK)
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return 1;
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return usec / US_PER_TICK;
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}
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unsigned long cpu_ticks2usec(unsigned long ticks)
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{
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return ticks * US_PER_TICK;
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}
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