From 20eb68b17901df31ba7b808463c636081e606284 Mon Sep 17 00:00:00 2001 From: Adeeb <8762862+adeebshihadeh@users.noreply.github.com> Date: Wed, 3 Jun 2020 15:08:57 -0700 Subject: [PATCH] Add pre-commit hooks (#551) * add more pre-commit hooks * revert misra coverage table * fix coverage table exclusion --- .pre-commit-config.yaml | 6 +++-- board/drivers/llcan.h | 2 +- board/drivers/rtc.h | 6 ++--- board/drivers/uart.h | 6 ++--- board/inc/cmsis_gcc.h | 24 ++++++++--------- board/inc/mpu_armv7.h | 30 ++++++++++----------- board/pedal/Makefile | 2 +- board/power_saving.h | 2 +- board/safety/safety_toyota.h | 2 +- docs/panda_wifi_setup.md | 4 +-- drivers/windows/panda_playground/ReadMe.txt | 4 +-- 11 files changed, 45 insertions(+), 43 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 9b9597f..82bfe4e 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -3,9 +3,11 @@ repos: rev: master hooks: - id: check-ast - - id: check-json - - id: check-xml - id: check-yaml + - id: check-merge-conflict + - id: check-symlinks + - id: trailing-whitespace + exclude: '^(board/inc)|[tests/misra/coverage_table]/' - repo: https://github.com/pre-commit/mirrors-mypy rev: master hooks: diff --git a/board/drivers/llcan.h b/board/drivers/llcan.h index 0e33152..68ca242 100644 --- a/board/drivers/llcan.h +++ b/board/drivers/llcan.h @@ -92,7 +92,7 @@ bool llcan_init(CAN_TypeDef *CAN_obj) { break; } } - + if(ret){ // no mask // For some weird reason some of these registers do not want to set properly on CAN2 and CAN3. Probably something to do with the single/dual mode and their different filters. diff --git a/board/drivers/rtc.h b/board/drivers/rtc.h index 301c4de..1e79696 100644 --- a/board/drivers/rtc.h +++ b/board/drivers/rtc.h @@ -56,14 +56,14 @@ void rtc_set_time(timestamp_t time){ // Enable initialization mode register_set_bits(&(RTC->ISR), RTC_ISR_INIT); while((RTC->ISR & RTC_ISR_INITF) == 0){} - + // Set time RTC->TR = (to_bcd(time.hour) << RTC_TR_HU_Pos) | (to_bcd(time.minute) << RTC_TR_MNU_Pos) | (to_bcd(time.second) << RTC_TR_SU_Pos); RTC->DR = (to_bcd(time.year - YEAR_OFFSET) << RTC_DR_YU_Pos) | (time.weekday << RTC_DR_WDU_Pos) | (to_bcd(time.month) << RTC_DR_MU_Pos) | (to_bcd(time.day) << RTC_DR_DU_Pos); // Set options register_set(&(RTC->CR), 0U, 0xFCFFFFU); - + // Disable initalization mode register_clear_bits(&(RTC->ISR), RTC_ISR_INIT); @@ -95,7 +95,7 @@ timestamp_t rtc_get_time(void){ uint32_t time = RTC->TR; uint32_t date = RTC->DR; - // Parse values + // Parse values result.year = from_bcd((date & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos) + YEAR_OFFSET; result.month = from_bcd((date & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); result.day = from_bcd((date & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos); diff --git a/board/drivers/uart.h b/board/drivers/uart.h index da45803..cbf5c59 100644 --- a/board/drivers/uart.h +++ b/board/drivers/uart.h @@ -135,14 +135,14 @@ uint32_t prev_w_index = 0; void dma_pointer_handler(uart_ring *q, uint32_t dma_ndtr) { ENTER_CRITICAL(); uint32_t w_index = (q->rx_fifo_size - dma_ndtr); - + // Check for new data if (w_index != prev_w_index){ // Check for overflow if ( ((prev_w_index < q->r_ptr_rx) && (q->r_ptr_rx <= w_index)) || // No rollover ((w_index < prev_w_index) && ((q->r_ptr_rx <= w_index) || (prev_w_index < q->r_ptr_rx))) // Rollover - ){ + ){ // We lost data. Set the new read pointer to the oldest byte still available q->r_ptr_rx = (w_index + 1U) % q->rx_fifo_size; } @@ -243,7 +243,7 @@ void dma_rx_init(uart_ring *q) { // Circular, Increment memory, byte size, periph -> memory, enable // Transfer complete, half transfer, transfer error and direct mode error interrupt enable DMA2_Stream5->CR = DMA_SxCR_CHSEL_2 | DMA_SxCR_MINC | DMA_SxCR_CIRC | DMA_SxCR_HTIE | DMA_SxCR_TCIE | DMA_SxCR_TEIE | DMA_SxCR_DMEIE | DMA_SxCR_EN; - + // Enable DMA receiver in UART q->uart->CR3 |= USART_CR3_DMAR; diff --git a/board/inc/cmsis_gcc.h b/board/inc/cmsis_gcc.h index 3589d18..2f68473 100644 --- a/board/inc/cmsis_gcc.h +++ b/board/inc/cmsis_gcc.h @@ -46,9 +46,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -126,23 +126,23 @@ \details This default implementations initialized all data and additional bss sections relying on .copy.table and .zero.table specified properly in the used linker script. - + */ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) { extern void _start(void) __NO_RETURN; - + typedef struct { uint32_t const* src; uint32_t* dest; uint32_t wlen; } __copy_table_t; - + typedef struct { uint32_t* dest; uint32_t wlen; } __zero_table_t; - + extern const __copy_table_t __copy_table_start__; extern const __copy_table_t __copy_table_end__; extern const __zero_table_t __zero_table_start__; @@ -153,16 +153,16 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) pTable->dest[i] = pTable->src[i]; } } - + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { for(uint32_t i=0u; iwlen; ++i) { pTable->dest[i] = 0u; } } - + _start(); } - + #define __PROGRAM_START __cmsis_start #endif @@ -652,7 +652,7 @@ __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence zero is returned always in non-secure mode. - + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). \return PSPLIM Register value */ @@ -697,7 +697,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure Stack Pointer Limit register hence the write is silently ignored in non-secure mode. - + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set */ @@ -834,7 +834,7 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) { #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) +#if __has_builtin(__builtin_arm_get_fpscr) // Re-enable using built-in when GCC has been fixed // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ diff --git a/board/inc/mpu_armv7.h b/board/inc/mpu_armv7.h index ef8e681..e72cc46 100644 --- a/board/inc/mpu_armv7.h +++ b/board/inc/mpu_armv7.h @@ -21,13 +21,13 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + #if defined ( __ICCARM__ ) #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) #pragma clang system_header /* treat file as system include file */ #endif - + #ifndef ARM_MPU_ARMV7_H #define ARM_MPU_ARMV7_H @@ -79,12 +79,12 @@ /** * MPU Memory Access Attributes -* +* * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. * \param IsShareable Region is shareable between multiple bus masters. * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ +*/ #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ @@ -93,7 +93,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. @@ -110,7 +110,7 @@ /** * MPU Region Attribute and Size Register Value -* +* * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. @@ -119,7 +119,7 @@ * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. * \param SubRegionDisable Sub-region disable field. * \param Size Region size of the region to be configured, for example 4K, 8K. -*/ +*/ #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) @@ -129,7 +129,7 @@ * - Shareable * - Non-cacheable * - Non-bufferable -*/ +*/ #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) /** @@ -140,7 +140,7 @@ * - Bufferable (if shareable) or non-bufferable (if non-shareable) * * \param IsShareable Configures the device memory as shareable or non-shareable. -*/ +*/ #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) /** @@ -153,7 +153,7 @@ * \param OuterCp Configures the outer cache policy. * \param InnerCp Configures the inner cache policy. * \param IsShareable Configures the memory as shareable or non-shareable. -*/ +*/ #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) /** @@ -184,7 +184,7 @@ typedef struct { uint32_t RBAR; //!< The region base address register value (RBAR) uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR } ARM_MPU_Region_t; - + /** Enable the MPU. * \param MPU_Control Default access permissions for unconfigured regions. */ @@ -221,7 +221,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) /** Configure an MPU region. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) { MPU->RBAR = rbar; @@ -232,7 +232,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) * \param rnr Region number to be configured. * \param rbar Value for RBAR register. * \param rsar Value for RSAR register. -*/ +*/ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) { MPU->RNR = rnr; @@ -248,7 +248,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; - for (i = 0U; i < len; ++i) + for (i = 0U; i < len; ++i) { dst[i] = src[i]; } @@ -258,7 +258,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_ * \param table Pointer to the MPU configuration table. * \param cnt Amount of regions to be configured. */ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) { const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; while (cnt > MPU_TYPE_RALIASES) { diff --git a/board/pedal/Makefile b/board/pedal/Makefile index 7ce6dd0..19937ec 100644 --- a/board/pedal/Makefile +++ b/board/pedal/Makefile @@ -61,7 +61,7 @@ obj/$(PROJ_NAME).bin: obj/$(STARTUP_FILE).o obj/main.o obj/bootstub.bin: obj/$(STARTUP_FILE).o obj/bootstub.o obj/sha.o obj/rsa.o $(CC) $(CFLAGS) -o obj/bootstub.$(PROJ_NAME).elf $^ $(OBJCOPY) -v -O binary obj/bootstub.$(PROJ_NAME).elf $@ - + clean: rm -f obj/* diff --git a/board/power_saving.h b/board/power_saving.h index f7e4237..3df750c 100644 --- a/board/power_saving.h +++ b/board/power_saving.h @@ -52,7 +52,7 @@ void set_power_save_state(int state) { // Switch off IR when in power saving if(!enable){ current_board->set_ir_power(0U); - } + } power_save_status = state; } diff --git a/board/safety/safety_toyota.h b/board/safety/safety_toyota.h index 4aef23e..ef881c0 100644 --- a/board/safety/safety_toyota.h +++ b/board/safety/safety_toyota.h @@ -186,7 +186,7 @@ static int toyota_tx_hook(CAN_FIFOMailBox_TypeDef *to_send) { bool violation = (unsafe_mode & UNSAFE_RAISE_LONGITUDINAL_LIMITS_TO_ISO_MAX)? max_limit_check(desired_accel, TOYOTA_ISO_MAX_ACCEL, TOYOTA_ISO_MIN_ACCEL) : max_limit_check(desired_accel, TOYOTA_MAX_ACCEL, TOYOTA_MIN_ACCEL); - + if (violation) { tx = 0; } diff --git a/docs/panda_wifi_setup.md b/docs/panda_wifi_setup.md index a6dfaf1..4e9c80c 100644 --- a/docs/panda_wifi_setup.md +++ b/docs/panda_wifi_setup.md @@ -6,10 +6,10 @@ 3. Inside the web interface enable secured mode by clinking the **secure it** link/button (this should make the White Panda's Wi-Fi network visible) - ### If you need your White Panda's Wi-Fi Password + ### If you need your White Panda's Wi-Fi Password * Run the **get_panda_password.py** script in found in **examples/** (Must have panda paw for this step because you need to connect White Panda via USB to retrive the Wi-Fi password) - * Also ensure that you are connected to your White Panda's Wi-Fi pairing network + * Also ensure that you are connected to your White Panda's Wi-Fi pairing network 4. Connect to your White Panda's default Wi-Fi network (this should be the Wi-Fi network WITHOUT the "-pair" at the end) diff --git a/drivers/windows/panda_playground/ReadMe.txt b/drivers/windows/panda_playground/ReadMe.txt index 37dba5d..61ce2c1 100644 --- a/drivers/windows/panda_playground/ReadMe.txt +++ b/drivers/windows/panda_playground/ReadMe.txt @@ -15,8 +15,8 @@ panda_playground.vcxproj Application Wizard. panda_playground.vcxproj.filters - This is the filters file for VC++ projects generated using an Application Wizard. - It contains information about the association between the files in your project + This is the filters file for VC++ projects generated using an Application Wizard. + It contains information about the association between the files in your project and the filters. This association is used in the IDE to show grouping of files with similar extensions under a specific node (for e.g. ".cpp" files are associated with the "Source Files" filter).