From 45d0d286f4b5c893590a98ec1438b8a143b9605d Mon Sep 17 00:00:00 2001 From: dekerr Date: Fri, 19 Jul 2019 22:35:50 -0400 Subject: [PATCH] remove whitespace (#255) --- board/inc/stm32f205xx.h | 408 +- board/inc/stm32f2xx.h | 46 +- board/inc/stm32f2xx_hal_def.h | 46 +- board/inc/stm32f2xx_hal_gpio_ex.h | 118 +- board/inc/stm32f413xx.h | 8568 ++++++++--------- board/inc/stm32f4xx.h | 52 +- board/inc/stm32f4xx_hal_def.h | 58 +- board/inc/stm32f4xx_hal_gpio_ex.h | 976 +- board/inc/system_stm32f2xx.h | 20 +- board/inc/system_stm32f4xx.h | 22 +- board/startup_stm32f205xx.s | 40 +- board/startup_stm32f413xx.s | 58 +- boardesp/webserver.c | 10 +- crypto/sha.c | 2 +- .../pandaJ2534DLL/PandaJ2534Device.cpp | 2 +- drivers/windows/pandaJ2534DLL/resource.h | 2 +- examples/can_unique.md | 4 +- examples/get_panda_password.py | 6 +- examples/tesla_tester.py | 16 +- python/flash_release.py | 2 +- python/isotp.py | 2 +- 21 files changed, 5229 insertions(+), 5229 deletions(-) diff --git a/board/inc/stm32f205xx.h b/board/inc/stm32f205xx.h index ba825d1..622faea 100644 --- a/board/inc/stm32f205xx.h +++ b/board/inc/stm32f205xx.h @@ -4,8 +4,8 @@ * @author MCD Application Team * @version V2.1.2 * @date 29-June-2016 - * @brief CMSIS STM32F205xx Device Peripheral Access Layer Header File. - * This file contains : + * @brief CMSIS STM32F205xx Device Peripheral Access Layer Header File. + * This file contains : * - Data structures and the address mapping for all peripherals * - Peripherals registers declarations and bits definition * - Macros to access peripheral’s registers hardware @@ -47,21 +47,21 @@ /** @addtogroup stm32f205xx * @{ */ - + #ifndef __STM32F205xx_H #define __STM32F205xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ - + /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals */ #define __CM3_REV 0x0200U /*!< Core revision r0p1 */ #define __MPU_PRESENT 1U /*!< STM32F2XX provides an MPU */ @@ -71,14 +71,14 @@ /** * @} */ - + /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** - * @brief STM32F2XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section + * @brief STM32F2XX Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section */ typedef enum { @@ -126,7 +126,7 @@ typedef enum I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ @@ -134,7 +134,7 @@ typedef enum USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ @@ -181,16 +181,16 @@ typedef enum /** @addtogroup Peripheral_registers_structures * @{ - */ + */ -/** - * @brief Analog to Digital Converter +/** + * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ @@ -220,8 +220,8 @@ typedef struct } ADC_Common_TypeDef; -/** - * @brief Controller Area Network TxMailBox +/** + * @brief Controller Area Network TxMailBox */ typedef struct @@ -232,10 +232,10 @@ typedef struct __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; -/** - * @brief Controller Area Network FIFOMailBox +/** + * @brief Controller Area Network FIFOMailBox */ - + typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ @@ -244,20 +244,20 @@ typedef struct __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; -/** - * @brief Controller Area Network FilterRegister +/** + * @brief Controller Area Network FilterRegister */ - + typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; -/** - * @brief Controller Area Network +/** + * @brief Controller Area Network */ - + typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ @@ -280,12 +280,12 @@ typedef struct __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; -/** - * @brief CRC calculation unit +/** + * @brief CRC calculation unit */ typedef struct @@ -297,7 +297,7 @@ typedef struct __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; -/** +/** * @brief Digital to Analog Converter */ @@ -319,7 +319,7 @@ typedef struct __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; -/** +/** * @brief Debug MCU */ @@ -332,7 +332,7 @@ typedef struct }DBGMCU_TypeDef; -/** +/** * @brief DMA Controller */ @@ -355,7 +355,7 @@ typedef struct } DMA_TypeDef; -/** +/** * @brief External Interrupt/Event Controller */ @@ -369,7 +369,7 @@ typedef struct __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; -/** +/** * @brief FLASH Registers */ @@ -384,28 +384,28 @@ typedef struct } FLASH_TypeDef; -/** +/** * @brief Flexible Static Memory Controller */ typedef struct { - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FSMC_Bank1_TypeDef; -/** +/** * @brief Flexible Static Memory Controller Bank1E */ - + typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FSMC_Bank1E_TypeDef; -/** +/** * @brief Flexible Static Memory Controller Bank2 */ - + typedef struct { __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ @@ -424,10 +424,10 @@ typedef struct __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ } FSMC_Bank2_3_TypeDef; -/** +/** * @brief Flexible Static Memory Controller Bank4 */ - + typedef struct { __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ @@ -435,10 +435,10 @@ typedef struct __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; +} FSMC_Bank4_TypeDef; -/** +/** * @brief General Purpose I/O */ @@ -455,20 +455,20 @@ typedef struct __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; -/** +/** * @brief System configuration controller */ - + typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; -/** +/** * @brief Inter-integrated Circuit Interface */ @@ -485,7 +485,7 @@ typedef struct __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ } I2C_TypeDef; -/** +/** * @brief Independent WATCHDOG */ @@ -497,7 +497,7 @@ typedef struct __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ } IWDG_TypeDef; -/** +/** * @brief Power Control */ @@ -507,7 +507,7 @@ typedef struct __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ } PWR_TypeDef; -/** +/** * @brief Reset and Clock Control */ @@ -546,7 +546,7 @@ typedef struct } RCC_TypeDef; -/** +/** * @brief Real-Time Clock */ @@ -595,7 +595,7 @@ typedef struct } RTC_TypeDef; -/** +/** * @brief SD host Interface */ @@ -623,7 +623,7 @@ typedef struct __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ } SDIO_TypeDef; -/** +/** * @brief Serial Peripheral Interface */ @@ -640,7 +640,7 @@ typedef struct __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; -/** +/** * @brief TIM */ @@ -669,10 +669,10 @@ typedef struct __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ } TIM_TypeDef; -/** +/** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ - + typedef struct { __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ @@ -684,7 +684,7 @@ typedef struct __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; -/** +/** * @brief Window WATCHDOG */ @@ -696,11 +696,11 @@ typedef struct } WWDG_TypeDef; -/** +/** * @brief RNG */ - -typedef struct + +typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ @@ -708,8 +708,8 @@ typedef struct } RNG_TypeDef; - -/** + +/** * @brief __USB_OTG_Core_register */ typedef struct @@ -737,10 +737,10 @@ USB_OTG_GlobalTypeDef; -/** +/** * @brief __device_Registers */ -typedef struct +typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register Address offset : 0x800 */ __IO uint32_t DCTL; /*!< dev Control Register Address offset : 0x804 */ @@ -757,19 +757,19 @@ typedef struct __IO uint32_t DTHRCTL; /*!< dev thr Address offset : 0x830 */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset : 0x834 */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset : 0x838 */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset : 0x83C */ uint32_t Reserved40; /*!< dedicated EP mask Address offset : 0x840 */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset : 0x844 */ uint32_t Reserved44[15]; /*!< Reserved Address offset : 0x844-0x87C */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset : 0x884 */ } USB_OTG_DeviceTypeDef; -/** +/** * @brief __IN_Endpoint-Specific_Register */ -typedef struct +typedef struct { __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h */ @@ -783,10 +783,10 @@ typedef struct USB_OTG_INEndpointTypeDef; -/** +/** * @brief __OUT_Endpoint-Specific_Registers */ -typedef struct +typedef struct { __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ @@ -799,10 +799,10 @@ typedef struct USB_OTG_OUTEndpointTypeDef; -/** +/** * @brief __Host_Mode_Register_Structures */ -typedef struct +typedef struct { __IO uint32_t HCFG; /* Host Configuration Register 400h*/ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ @@ -815,7 +815,7 @@ typedef struct USB_OTG_HostTypeDef; -/** +/** * @brief __Host_Channel_Specific_Registers */ typedef struct @@ -830,8 +830,8 @@ typedef struct } USB_OTG_HostChannelTypeDef; - -/** + +/** * @brief Peripheral_memory_map */ #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ @@ -965,10 +965,10 @@ USB_OTG_HostChannelTypeDef; /** * @} */ - + /** @addtogroup Peripheral_declaration * @{ - */ + */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) @@ -1003,7 +1003,7 @@ USB_OTG_HostChannelTypeDef; #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) @@ -1038,7 +1038,7 @@ USB_OTG_HostChannelTypeDef; #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) @@ -1057,11 +1057,11 @@ USB_OTG_HostChannelTypeDef; /** @addtogroup Exported_constants * @{ */ - + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ - + /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ @@ -1104,7 +1104,7 @@ USB_OTG_HostChannelTypeDef; #define ADC_CR1_RES_0 0x01000000U /*!
© COPYRIGHT(c) 2016 STMicroelectronics
@@ -32,8 +32,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /** @addtogroup CMSIS * @{ @@ -41,8 +41,8 @@ /** @addtogroup stm32f4xx_system * @{ - */ - + */ + /** * @brief Define to prevent recursive inclusion */ @@ -51,7 +51,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /** @addtogroup STM32F4xx_System_Includes * @{ @@ -68,7 +68,7 @@ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. @@ -101,7 +101,7 @@ extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ /** @addtogroup STM32F4xx_System_Exported_Functions * @{ */ - + extern void SystemInit(void); extern void SystemCoreClockUpdate(void); /** @@ -117,8 +117,8 @@ extern void SystemCoreClockUpdate(void); /** * @} */ - + /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/board/startup_stm32f205xx.s b/board/startup_stm32f205xx.s index f4b6c6c..7554efc 100644 --- a/board/startup_stm32f205xx.s +++ b/board/startup_stm32f205xx.s @@ -4,7 +4,7 @@ * @author MCD Application Team * @version V2.1.2 * @date 29-June-2016 - * @brief STM32F205xx Devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F205xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -42,7 +42,7 @@ * ****************************************************************************** */ - + .syntax unified .cpu cortex-m3 .thumb @@ -50,10 +50,10 @@ .global g_pfnVectors .global Default_Handler -/* start address for the initialization values of the .data section. +/* start address for the initialization values of the .data section. defined in linker script */ .word _sidata -/* start address for the .data section. defined in linker script */ +/* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata @@ -67,7 +67,7 @@ defined in linker script */ * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application - * supplied main() routine is called. + * supplied main() routine is called. * @param None * @retval : None */ @@ -75,7 +75,7 @@ defined in linker script */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function -Reset_Handler: +Reset_Handler: ldr sp, =_estack /* set stack pointer */ bl __initialize_hardware_early @@ -88,7 +88,7 @@ CopyDataInit: ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 - + LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata @@ -101,7 +101,7 @@ LoopCopyDataInit: FillZerobss: movs r3, #0 str r3, [r2], #4 - + LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 @@ -113,15 +113,15 @@ LoopFillZerobss: /*bl __libc_init_array*/ /* Call the application's entry point.*/ bl main - bx lr + bx lr .size Reset_Handler, .-Reset_Handler /** - * @brief This is the code that gets called when the processor receives an + * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. - * @param None - * @retval None + * @param None + * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: @@ -133,14 +133,14 @@ Infinite_Loop: * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. -* +* *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - - + + g_pfnVectors: .word _estack .word Reset_Handler @@ -159,7 +159,7 @@ g_pfnVectors: .word 0 .word PendSV_Handler .word SysTick_Handler - + /* External Interrupts */ .word WWDG_IRQHandler /* Window WatchDog */ .word PVD_IRQHandler /* PVD through EXTI Line detection */ @@ -248,7 +248,7 @@ g_pfnVectors: * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. -* +* *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler @@ -302,7 +302,7 @@ g_pfnVectors: .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler + .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler @@ -320,7 +320,7 @@ g_pfnVectors: .thumb_set DMA1_Stream2_IRQHandler,Default_Handler .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler .weak DMA1_Stream4_IRQHandler .thumb_set DMA1_Stream4_IRQHandler,Default_Handler @@ -432,7 +432,7 @@ g_pfnVectors: .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler - + .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler diff --git a/board/startup_stm32f413xx.s b/board/startup_stm32f413xx.s index 00b645d..6e6fb5f 100644 --- a/board/startup_stm32f413xx.s +++ b/board/startup_stm32f413xx.s @@ -4,7 +4,7 @@ * @author MCD Application Team * @version V2.6.0 * @date 04-November-2016 - * @brief STM32F413xx Devices vector table for GCC based toolchains. + * @brief STM32F413xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -42,7 +42,7 @@ * ****************************************************************************** */ - + .syntax unified .cpu cortex-m4 .fpu softvfp @@ -51,7 +51,7 @@ .global g_pfnVectors .global Default_Handler -/* start address for the initialization values of the .data section. +/* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ @@ -68,7 +68,7 @@ defined in linker script */ * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application - * supplied main() routine is called. + * supplied main() routine is called. * @param None * @retval : None */ @@ -76,7 +76,7 @@ defined in linker script */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function -Reset_Handler: +Reset_Handler: ldr sp, =_estack /* set stack pointer */ bl __initialize_hardware_early @@ -89,7 +89,7 @@ CopyDataInit: ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 - + LoopCopyDataInit: ldr r0, =_sdata ldr r3, =_edata @@ -102,7 +102,7 @@ LoopCopyDataInit: FillZerobss: movs r3, #0 str r3, [r2], #4 - + LoopFillZerobss: ldr r3, = _ebss cmp r2, r3 @@ -114,15 +114,15 @@ LoopFillZerobss: /* bl __libc_init_array */ /* Call the application's entry point.*/ bl main - bx lr + bx lr .size Reset_Handler, .-Reset_Handler /** - * @brief This is the code that gets called when the processor receives an + * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. - * @param None - * @retval None + * @param None + * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: @@ -134,12 +134,12 @@ Infinite_Loop: * The minimal vector table for a Cortex M3. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. -* +* *******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors - + g_pfnVectors: .word _estack .word Reset_Handler @@ -261,11 +261,11 @@ g_pfnVectors: .word DFSDM2_FLT1_IRQHandler /* DFSDM2 Filter1 */ .word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */ .word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */ - + /******************************************************************************* * -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ @@ -277,7 +277,7 @@ g_pfnVectors: .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler - + .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler @@ -321,7 +321,7 @@ g_pfnVectors: .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler + .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler @@ -439,9 +439,9 @@ g_pfnVectors: .weak DMA1_Stream7_IRQHandler .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - + .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler + .thumb_set FSMC_IRQHandler,Default_Handler .weak SDIO_IRQHandler .thumb_set SDIO_IRQHandler,Default_Handler @@ -451,12 +451,12 @@ g_pfnVectors: .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler - + .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler + .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler @@ -517,7 +517,7 @@ g_pfnVectors: .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler - + .weak CAN3_TX_IRQHandler .thumb_set CAN3_TX_IRQHandler,Default_Handler @@ -528,26 +528,26 @@ g_pfnVectors: .thumb_set CAN3_RX1_IRQHandler,Default_Handler .weak CAN3_SCE_IRQHandler - .thumb_set CAN3_SCE_IRQHandler,Default_Handler + .thumb_set CAN3_SCE_IRQHandler,Default_Handler .weak RNG_IRQHandler .thumb_set RNG_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler - + .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler + .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler - + .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler @@ -555,7 +555,7 @@ g_pfnVectors: .thumb_set UART9_IRQHandler,Default_Handler .weak UART10_IRQHandler - .thumb_set UART10_IRQHandler,Default_Handler + .thumb_set UART10_IRQHandler,Default_Handler .weak QUADSPI_IRQHandler .thumb_set QUADSPI_IRQHandler,Default_Handler @@ -565,7 +565,7 @@ g_pfnVectors: .weak FMPI2C1_ER_IRQHandler .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler - + .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler diff --git a/boardesp/webserver.c b/boardesp/webserver.c index f855f88..65e0258 100644 --- a/boardesp/webserver.c +++ b/boardesp/webserver.c @@ -84,7 +84,7 @@ int ICACHE_FLASH_ATTR usb_cmd(int ep, int len, int request, return recv[0]; } - + void ICACHE_FLASH_ATTR st_flash() { if (st_firmware != NULL) { @@ -212,14 +212,14 @@ static void ICACHE_FLASH_ATTR web_rx_cb(void *arg, char *data, uint16_t len) { } else { ets_strcat(resp, "\nin INSECURE mode...secure it"); } - + ets_strcat(resp,"\nSet USB Mode:" "" "" "\n"); ets_strcat(resp, pagefooter); - + espconn_send_string(&web_conn, resp); espconn_disconnect(conn); } else if (memcmp(data, "GET /secure", 11) == 0 && !wifi_secure_mode) { @@ -235,7 +235,7 @@ static void ICACHE_FLASH_ATTR web_rx_cb(void *arg, char *data, uint16_t len) { os_sprintf(resp, "%sUSB Mode set to %02x\n\n", OK_header, mode_value); espconn_send_string(&web_conn, resp); espconn_disconnect(conn); - } + } } else if (memcmp(data, "PUT /stupdate ", 14) == 0 && wifi_secure_mode) { os_printf("init st firmware\n"); char *cl = strstr(data, "Content-Length: "); @@ -251,7 +251,7 @@ static void ICACHE_FLASH_ATTR web_rx_cb(void *arg, char *data, uint16_t len) { memset(st_firmware, 0, real_content_length); state = RECEIVING_ST_FIRMWARE; } - + } else if (((memcmp(data, "PUT /espupdate1 ", 16) == 0) || (memcmp(data, "PUT /espupdate2 ", 16) == 0)) && wifi_secure_mode) { // 0x1000 = user1.bin diff --git a/crypto/sha.c b/crypto/sha.c index 8e17155..a13162c 100644 --- a/crypto/sha.c +++ b/crypto/sha.c @@ -130,7 +130,7 @@ const uint8_t* SHA_final(SHA_CTX* ctx) { /* Hack - right shift operator with non const argument requires * libgcc.a which is missing in EON - * thus expanding for loop from + * thus expanding for loop from for (i = 0; i < 8; ++i) { uint8_t tmp = (uint8_t) (cnt >> ((7 - i) * 8)); diff --git a/drivers/windows/pandaJ2534DLL/PandaJ2534Device.cpp b/drivers/windows/pandaJ2534DLL/PandaJ2534Device.cpp index 4cda1fa..19ae43b 100644 --- a/drivers/windows/pandaJ2534DLL/PandaJ2534Device.cpp +++ b/drivers/windows/pandaJ2534DLL/PandaJ2534Device.cpp @@ -93,7 +93,7 @@ DWORD PandaJ2534Device::can_process_thread() { if (count == 0) { continue; } - + for (int i = 0; i < count; i++) { auto msg_in = msg_recv[i]; J2534Frame msg_out(msg_in); diff --git a/drivers/windows/pandaJ2534DLL/resource.h b/drivers/windows/pandaJ2534DLL/resource.h index 771e7b8..af0e13c 100644 --- a/drivers/windows/pandaJ2534DLL/resource.h +++ b/drivers/windows/pandaJ2534DLL/resource.h @@ -3,7 +3,7 @@ // Used by pandaJ2534DLL.rc // Next default values for new objects -// +// #ifdef APSTUDIO_INVOKED #ifndef APSTUDIO_READONLY_SYMBOLS #define _APS_NEXT_RESOURCE_VALUE 101 diff --git a/examples/can_unique.md b/examples/can_unique.md index bf31694..4d8ac46 100644 --- a/examples/can_unique.md +++ b/examples/can_unique.md @@ -10,8 +10,8 @@ First record a few minutes of background CAN messages with all the doors closed ./can_logger.py mv output.csv background.csv ``` -Then run can_logger.py for a few seconds while performing the action you're interested, such as opening and then closing the -front-left door and save it as door-fl-1.csv +Then run can_logger.py for a few seconds while performing the action you're interested, such as opening and then closing the +front-left door and save it as door-fl-1.csv Repeat the process and save it as door-f1-2.csv to have an easy way to confirm any suspicions. Now we'll use can_unique.py to look for unique bits: diff --git a/examples/get_panda_password.py b/examples/get_panda_password.py index 11071d0..575cbb0 100644 --- a/examples/get_panda_password.py +++ b/examples/get_panda_password.py @@ -2,11 +2,11 @@ from panda import Panda def get_panda_password(): - + try: print("Trying to connect to Panda over USB...") p = Panda() - + except AssertionError: print("USB connection failed") sys.exit(0) @@ -15,6 +15,6 @@ def get_panda_password(): #print('[%s]' % ', '.join(map(str, wifi))) print("SSID: " + wifi[0]) print("Password: " + wifi[1]) - + if __name__ == "__main__": get_panda_password() \ No newline at end of file diff --git a/examples/tesla_tester.py b/examples/tesla_tester.py index 99d8d92..4365e42 100644 --- a/examples/tesla_tester.py +++ b/examples/tesla_tester.py @@ -4,14 +4,14 @@ import binascii from panda import Panda def tesla_tester(): - + try: print("Trying to connect to Panda over USB...") p = Panda() - + except AssertionError: print("USB connection failed. Trying WiFi...") - + try: p = Panda("WIFI") except: @@ -21,12 +21,12 @@ def tesla_tester(): body_bus_speed = 125 # Tesla Body busses (B, BF) are 125kbps, rest are 500kbps body_bus_num = 1 # My TDC to OBD adapter has PT on bus0 BDY on bus1 and CH on bus2 p.set_can_speed_kbps(body_bus_num, body_bus_speed) - + # Now set the panda from its default of SAFETY_NOOUTPUT (read only) to SAFETY_ALLOUTPUT # Careful, as this will let us send any CAN messages we want (which could be very bad!) print("Setting Panda to output mode...") p.set_safety_mode(Panda.SAFETY_ALLOUTPUT) - + # BDY 0x248 is the MCU_commands message, which includes folding mirrors, opening the trunk, frunk, setting the cars lock state and more. For our test, we will edit the 3rd byte, which is MCU_lockRequest. 0x01 will lock, 0x02 will unlock: print("Unlocking Tesla...") p.can_send(0x248, "\x00\x00\x02\x00\x00\x00\x00\x00", body_bus_num) @@ -34,13 +34,13 @@ def tesla_tester(): #Or, we can set the first byte, MCU_frontHoodCommand + MCU_liftgateSwitch, to 0x01 to pop the frunk, or 0x04 to open/close the trunk (0x05 should open both) print("Opening Frunk...") p.can_send(0x248, "\x01\x00\x00\x00\x00\x00\x00\x00", body_bus_num) - + #Back to safety... print("Disabling output on Panda...") p.set_safety_mode(Panda.SAFETY_NOOUTPUT) - + print("Reading VIN from 0x568. This is painfully slow and can take up to 3 minutes (1 minute per message; 3 messages needed for full VIN)...") - + vin = {} while True: #Read the VIN diff --git a/python/flash_release.py b/python/flash_release.py index 51f6a72..0f407ff 100755 --- a/python/flash_release.py +++ b/python/flash_release.py @@ -89,7 +89,7 @@ def flash_release(path=None, st_serial=None): # done! status("6. Success!") - + if __name__ == "__main__": flash_release(*sys.argv[1:]) diff --git a/python/isotp.py b/python/isotp.py index d68aa4d..9718270 100644 --- a/python/isotp.py +++ b/python/isotp.py @@ -29,7 +29,7 @@ def recv(panda, cnt, addr, nbus): def isotp_recv_subaddr(panda, addr, bus, sendaddr, subaddr): msg = recv(panda, 1, addr, bus)[0] - # TODO: handle other subaddr also communicating + # TODO: handle other subaddr also communicating assert ord(msg[0]) == subaddr if ord(msg[1])&0xf0 == 0x10: