139 lines
4.2 KiB
C
139 lines
4.2 KiB
C
// this is needed for 1 mbps support
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#define CAN_QUANTA 8U
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#define CAN_SEQ1 6 // roundf(quanta * 0.875f) - 1;
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#define CAN_SEQ2 1 // roundf(quanta * 0.125f);
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#define CAN_PCLK 24000U
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// 333 = 33.3 kbps
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// 5000 = 500 kbps
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#define can_speed_to_prescaler(x) (CAN_PCLK / CAN_QUANTA * 10U / (x))
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#define GET_BUS(msg) (((msg)->RDTR >> 4) & 0xFF)
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#define GET_LEN(msg) ((msg)->RDTR & 0xF)
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#define GET_ADDR(msg) ((((msg)->RIR & 4) != 0) ? ((msg)->RIR >> 3) : ((msg)->RIR >> 21))
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#define GET_BYTE(msg, b) (((int)(b) > 3) ? (((msg)->RDHR >> (8U * ((unsigned int)(b) % 4U))) & 0xFFU) : (((msg)->RDLR >> (8U * (unsigned int)(b))) & 0xFFU))
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#define GET_BYTES_04(msg) ((msg)->RDLR)
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#define GET_BYTES_48(msg) ((msg)->RDHR)
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#define GET_FLAG(value, mask) (((__typeof__(mask))param & mask) == mask)
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#define CAN_INIT_TIMEOUT_MS 500U
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#define CAN_NAME_FROM_CANIF(CAN_DEV) (((CAN_DEV)==CAN1) ? "CAN1" : (((CAN_DEV) == CAN2) ? "CAN2" : "CAN3"))
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void puts(const char *a);
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bool llcan_set_speed(CAN_TypeDef *CAN_obj, uint32_t speed, bool loopback, bool silent) {
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bool ret = true;
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// initialization mode
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register_set(&(CAN_obj->MCR), CAN_MCR_TTCM | CAN_MCR_INRQ, 0x180FFU);
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uint32_t timeout_counter = 0U;
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while((CAN_obj->MSR & CAN_MSR_INAK) != CAN_MSR_INAK){
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
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puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(" set_speed timed out (1)!\n");
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ret = false;
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break;
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}
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}
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if(ret){
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// set time quanta from defines
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register_set(&(CAN_obj->BTR), ((CAN_BTR_TS1_0 * (CAN_SEQ1-1)) |
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(CAN_BTR_TS2_0 * (CAN_SEQ2-1)) |
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(can_speed_to_prescaler(speed) - 1U)), 0xC37F03FFU);
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// silent loopback mode for debugging
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if (loopback) {
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register_set_bits(&(CAN_obj->BTR), CAN_BTR_SILM | CAN_BTR_LBKM);
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}
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if (silent) {
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register_set_bits(&(CAN_obj->BTR), CAN_BTR_SILM);
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}
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// reset
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register_set(&(CAN_obj->MCR), CAN_MCR_TTCM | CAN_MCR_ABOM, 0x180FFU);
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timeout_counter = 0U;
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while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
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puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(" set_speed timed out (2)!\n");
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ret = false;
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break;
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}
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}
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}
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return ret;
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}
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bool llcan_init(CAN_TypeDef *CAN_obj) {
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bool ret = true;
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// Enter init mode
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register_set_bits(&(CAN_obj->FMR), CAN_FMR_FINIT);
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// Wait for INAK bit to be set
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uint32_t timeout_counter = 0U;
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while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
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puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(" initialization timed out!\n");
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ret = false;
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break;
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}
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}
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if(ret){
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// no mask
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// For some weird reason some of these registers do not want to set properly on CAN2 and CAN3. Probably something to do with the single/dual mode and their different filters.
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CAN_obj->sFilterRegister[0].FR1 = 0U;
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CAN_obj->sFilterRegister[0].FR2 = 0U;
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CAN_obj->sFilterRegister[14].FR1 = 0U;
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CAN_obj->sFilterRegister[14].FR2 = 0U;
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CAN_obj->FA1R |= 1U | (1U << 14);
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// Exit init mode, do not wait
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register_clear_bits(&(CAN_obj->FMR), CAN_FMR_FINIT);
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// enable certain CAN interrupts
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register_set_bits(&(CAN_obj->IER), CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_WKUIE);
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if (CAN_obj == CAN1) {
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NVIC_EnableIRQ(CAN1_TX_IRQn);
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NVIC_EnableIRQ(CAN1_RX0_IRQn);
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NVIC_EnableIRQ(CAN1_SCE_IRQn);
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} else if (CAN_obj == CAN2) {
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NVIC_EnableIRQ(CAN2_TX_IRQn);
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NVIC_EnableIRQ(CAN2_RX0_IRQn);
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NVIC_EnableIRQ(CAN2_SCE_IRQn);
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#ifdef CAN3
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} else if (CAN_obj == CAN3) {
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NVIC_EnableIRQ(CAN3_TX_IRQn);
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NVIC_EnableIRQ(CAN3_RX0_IRQn);
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NVIC_EnableIRQ(CAN3_SCE_IRQn);
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#endif
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} else {
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puts("Invalid CAN: initialization failed\n");
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}
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}
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return ret;
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}
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void llcan_clear_send(CAN_TypeDef *CAN_obj) {
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CAN_obj->TSR |= CAN_TSR_ABRQ0;
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register_clear_bits(&(CAN_obj->MSR), CAN_MSR_ERRI);
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// cppcheck-suppress selfAssignment ; needed to clear the register
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CAN_obj->MSR = CAN_obj->MSR;
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}
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