131 lines
3.5 KiB
C
131 lines
3.5 KiB
C
// IRQs: DMA2_Stream2, DMA2_Stream3, EXTI4
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void spi_init(void);
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int spi_cb_rx(uint8_t *data, int len, uint8_t *data_out);
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// end API
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#define SPI_BUF_SIZE 256
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uint8_t spi_buf[SPI_BUF_SIZE];
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int spi_buf_count = 0;
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int spi_total_count = 0;
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void spi_tx_dma(void *addr, int len) {
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// disable DMA
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SPI1->CR2 &= ~SPI_CR2_TXDMAEN;
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DMA2_Stream3->CR &= ~DMA_SxCR_EN;
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// DMA2, stream 3, channel 3
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DMA2_Stream3->M0AR = (uint32_t)addr;
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DMA2_Stream3->NDTR = len;
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DMA2_Stream3->PAR = (uint32_t)&(SPI1->DR);
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// channel3, increment memory, memory -> periph, enable
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DMA2_Stream3->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_EN;
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delay(0);
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DMA2_Stream3->CR |= DMA_SxCR_TCIE;
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SPI1->CR2 |= SPI_CR2_TXDMAEN;
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// signal data is ready by driving low
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// esp must be configured as input by this point
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set_gpio_output(GPIOB, 0, 0);
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}
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void spi_rx_dma(void *addr, int len) {
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// disable DMA
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SPI1->CR2 &= ~SPI_CR2_RXDMAEN;
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DMA2_Stream2->CR &= ~DMA_SxCR_EN;
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// drain the bus
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volatile uint8_t dat = SPI1->DR;
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(void)dat;
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// DMA2, stream 2, channel 3
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DMA2_Stream2->M0AR = (uint32_t)addr;
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DMA2_Stream2->NDTR = len;
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DMA2_Stream2->PAR = (uint32_t)&(SPI1->DR);
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// channel3, increment memory, periph -> memory, enable
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DMA2_Stream2->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 | DMA_SxCR_MINC | DMA_SxCR_EN;
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delay(0);
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DMA2_Stream2->CR |= DMA_SxCR_TCIE;
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SPI1->CR2 |= SPI_CR2_RXDMAEN;
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}
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// ***************************** SPI IRQs *****************************
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// can't go on the stack cause it's DMAed
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uint8_t spi_tx_buf[0x44];
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// SPI RX
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void DMA2_Stream2_IRQ_Handler(void) {
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int *resp_len = (int*)spi_tx_buf;
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(void)memset(spi_tx_buf, 0xaa, 0x44);
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*resp_len = spi_cb_rx(spi_buf, 0x14, spi_tx_buf+4);
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#ifdef DEBUG_SPI
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puts("SPI write: ");
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puth(*resp_len);
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puts("\n");
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#endif
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spi_tx_dma(spi_tx_buf, *resp_len + 4);
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// ack
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DMA2->LIFCR = DMA_LIFCR_CTCIF2;
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}
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// SPI TX
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void DMA2_Stream3_IRQ_Handler(void) {
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#ifdef DEBUG_SPI
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puts("SPI handshake\n");
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#endif
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// reset handshake back to pull up
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set_gpio_mode(GPIOB, 0, MODE_INPUT);
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set_gpio_pullup(GPIOB, 0, PULL_UP);
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// ack
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DMA2->LIFCR = DMA_LIFCR_CTCIF3;
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}
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void EXTI4_IRQ_Handler(void) {
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volatile unsigned int pr = EXTI->PR & (1U << 4);
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#ifdef DEBUG_SPI
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puts("exti4\n");
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#endif
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// SPI CS falling
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if ((pr & (1U << 4)) != 0U) {
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spi_total_count = 0;
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spi_rx_dma(spi_buf, 0x14);
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}
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EXTI->PR = pr;
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}
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// ***************************** SPI init *****************************
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void spi_init(void) {
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// Max SPI clock the ESP can produce is 80MHz. At buffer size of 256 bytes, that's a max of about 40k buffers per second
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REGISTER_INTERRUPT(DMA2_Stream2_IRQn, DMA2_Stream2_IRQ_Handler, 50000U, FAULT_INTERRUPT_RATE_SPI_DMA)
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REGISTER_INTERRUPT(DMA2_Stream3_IRQn, DMA2_Stream3_IRQ_Handler, 50000U, FAULT_INTERRUPT_RATE_SPI_DMA)
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REGISTER_INTERRUPT(EXTI4_IRQn, EXTI4_IRQ_Handler, 50000U, FAULT_INTERRUPT_RATE_SPI_CS) // TODO: Figure out if this is a reasonable limit
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//puts("SPI init\n");
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SPI1->CR1 = SPI_CR1_SPE;
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// enable SPI interrupts
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//SPI1->CR2 = SPI_CR2_RXNEIE | SPI_CR2_ERRIE | SPI_CR2_TXEIE;
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SPI1->CR2 = SPI_CR2_RXNEIE;
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NVIC_EnableIRQ(DMA2_Stream2_IRQn);
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NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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//NVIC_EnableIRQ(SPI1_IRQn);
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// reset handshake back to pull up
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set_gpio_mode(GPIOB, 0, MODE_INPUT);
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set_gpio_pullup(GPIOB, 0, PULL_UP);
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// setup interrupt on falling edge of SPI enable (on PA4)
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SYSCFG->EXTICR[2] = SYSCFG_EXTICR2_EXTI4_PA;
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EXTI->IMR |= (1U << 4);
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EXTI->FTSR |= (1U << 4);
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NVIC_EnableIRQ(EXTI4_IRQn);
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} |