52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
#include "spi.h"
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#include "rev.h"
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void spi_init() {
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//puts("SPI init\n");
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SPI1->CR1 = SPI_CR1_SPE;
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// enable SPI interrupts
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//SPI1->CR2 = SPI_CR2_RXNEIE | SPI_CR2_ERRIE | SPI_CR2_TXEIE;
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SPI1->CR2 = SPI_CR2_RXNEIE;
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}
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void spi_tx_dma(void *addr, int len) {
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// disable DMA
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SPI1->CR2 &= ~SPI_CR2_TXDMAEN;
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DMA2_Stream3->CR &= ~DMA_SxCR_EN;
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// DMA2, stream 3, channel 3
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DMA2_Stream3->M0AR = (uint32_t)addr;
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DMA2_Stream3->NDTR = len;
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DMA2_Stream3->PAR = (uint32_t)&(SPI1->DR);
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// channel3, increment memory, memory -> periph, enable
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DMA2_Stream3->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 |
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DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_EN;
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DMA2_Stream3->CR |= DMA_SxCR_TCIE;
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SPI1->CR2 |= SPI_CR2_TXDMAEN;
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}
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void spi_rx_dma(void *addr, int len) {
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// disable DMA
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SPI1->CR2 &= ~SPI_CR2_RXDMAEN;
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DMA2_Stream2->CR &= ~DMA_SxCR_EN;
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// drain the bus
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uint8_t dat = SPI1->DR;
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(void)dat;
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// DMA2, stream 2, channel 3
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DMA2_Stream2->M0AR = (uint32_t)addr;
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DMA2_Stream2->NDTR = len;
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DMA2_Stream2->PAR = (uint32_t)&(SPI1->DR);
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// channel3, increment memory, periph -> memory, enable
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DMA2_Stream2->CR = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0 |
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DMA_SxCR_MINC | DMA_SxCR_EN;
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DMA2_Stream2->CR |= DMA_SxCR_TCIE;
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SPI1->CR2 |= SPI_CR2_RXDMAEN;
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}
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