41 lines
1.2 KiB
C
41 lines
1.2 KiB
C
void clock_init(void) {
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// enable external oscillator
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register_set_bits(&(RCC->CR), RCC_CR_HSEON);
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while ((RCC->CR & RCC_CR_HSERDY) == 0);
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// divide things
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register_set(&(RCC->CFGR), RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_PPRE1_DIV4, 0xFF7FFCF3U);
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// 16mhz crystal
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register_set(&(RCC->PLLCFGR), RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_5 | RCC_PLLCFGR_PLLSRC_HSE, 0x7F437FFFU);
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// start PLL
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register_set_bits(&(RCC->CR), RCC_CR_PLLON);
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while ((RCC->CR & RCC_CR_PLLRDY) == 0);
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// Configure Flash prefetch, Instruction cache, Data cache and wait state
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// *** without this, it breaks ***
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register_set(&(FLASH->ACR), FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS, 0x1F0FU);
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// switch to PLL
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register_set_bits(&(RCC->CFGR), RCC_CFGR_SW_PLL);
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
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// *** running on PLL ***
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}
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void watchdog_init(void) {
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// setup watchdog
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IWDG->KR = 0x5555U;
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register_set(&(IWDG->PR), 0x0U, 0x7U); // divider/4
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// 0 = 0.125 ms, let's have a 50ms watchdog
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register_set(&(IWDG->RLR), (400U-1U), 0xFFFU);
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IWDG->KR = 0xCCCCU;
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}
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void watchdog_feed(void) {
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IWDG->KR = 0xAAAAU;
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}
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