From 2efe376768e0fa48c2f2c8b49acac19d7d212e69 Mon Sep 17 00:00:00 2001 From: gaurav Date: Mon, 11 Jul 2022 20:20:03 +0200 Subject: [PATCH] Comments no change to logic --- FPGA_Firmware/Source/src/debayer_filter.v | 16 ++++++++-------- FPGA_Firmware/Source/src/lsync_reset_generator.v | 3 +++ .../Source/src/mipi_csi_rx_byte_aligner.v | 2 +- .../src/mipi_csi_rx_packet_decoder_16b2lane.v | 5 +---- .../src/mipi_csi_rx_packet_decoder_16b4lane.v | 6 +----- .../src/mipi_csi_rx_packet_decoder_8b2lane.v | 5 +---- .../src/mipi_csi_rx_packet_decoder_8b4lane.v | 5 +---- .../src/mipi_csi_rx_raw_depacker_16b4lane.v | 4 ++-- .../src/mipi_csi_rx_raw_depacker_8b2lane_2ppc.v | 4 ++-- 9 files changed, 20 insertions(+), 30 deletions(-) diff --git a/FPGA_Firmware/Source/src/debayer_filter.v b/FPGA_Firmware/Source/src/debayer_filter.v index 98c686a..c9c04a9 100644 --- a/FPGA_Firmware/Source/src/debayer_filter.v +++ b/FPGA_Firmware/Source/src/debayer_filter.v @@ -19,13 +19,13 @@ First line is expected to BGBG , second line GRGR Basically BGGR format */ module debayer_filter #(parameter PIXEL_WIDTH=14 , parameter PIXEL_PER_CLK=8 )(clk_i, - reset_i, - line_valid_i, - data_i, //lane 0 is LSbits - data_valid_i, - output_valid_o, //lane 0 is LSbits - output_o - ); + reset_i, + line_valid_i, + data_i, //lane 0 is LSbits + data_valid_i, + output_valid_o, //lane 0 is LSbits + output_o + ); localparam INPUT_WIDTH = PIXEL_PER_CLK * PIXEL_WIDTH; //Upto 8 x 16bit pixels from raw depacker module (if 16bit each channel) localparam OUTPUT_WIDTH = PIXEL_WIDTH * PIXEL_PER_CLK * 3; //Upto 8 x 48bit RGB output @@ -125,7 +125,7 @@ integer i; //line rams, total 4, //The way debayer is implemented in this code. Depending on pixel, we need minimum 2 lines and maximum 3 lines in the ram, To be able to have access to neighboring pixels from previous and next line //There are many ways to implemented debayer, this code implement simplest possible bare minimum. -//IMX219 Camera only output BGGR as defined by the IMX219 Driver in linux repo MEDIA_BUS_FMT_SBGGR10_1X10, Camera datasheet incrorrectly defines output as RGGB and GBRG. Data sheet is incorrect in this case. +//IMX219/IMX477/IMX290/IMX462/IMX327 Camera only output BGGR as defined by Driver in linux repo MEDIA_BUS_FMT_SBGGR10_1X10, Camera datasheet incrorrectly defines output as RGGB and GBRG. Data sheet is incorrect in this case. //Bayer filter type does not affet test pattern. //ebr ram_dp write address and data is latched on same rising edge of write clock diff --git a/FPGA_Firmware/Source/src/lsync_reset_generator.v b/FPGA_Firmware/Source/src/lsync_reset_generator.v index 805620f..7c0c119 100644 --- a/FPGA_Firmware/Source/src/lsync_reset_generator.v +++ b/FPGA_Firmware/Source/src/lsync_reset_generator.v @@ -1,3 +1,6 @@ +//MIPI Data line HS to LP transition can cause gragage data into bus, +//This moduel holds reset a little longer before stable data comes throw + module line_reset_generator(clk_i, lp_data_i, line_reset_o); input clk_i; input lp_data_i; diff --git a/FPGA_Firmware/Source/src/mipi_csi_rx_byte_aligner.v b/FPGA_Firmware/Source/src/mipi_csi_rx_byte_aligner.v index 871418a..1871555 100644 --- a/FPGA_Firmware/Source/src/mipi_csi_rx_byte_aligner.v +++ b/FPGA_Firmware/Source/src/mipi_csi_rx_byte_aligner.v @@ -75,7 +75,7 @@ begin byte_valid_o <= valid_reg; - if (synced & !valid_reg) + if (synced & !valid_reg)// also check for valid_reg to be intive, this make sure that once sync is detected no further sync are concidered till next reset begin sync_offset <= offset; valid_reg <= 1'h1; diff --git a/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_16b2lane.v b/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_16b2lane.v index f5253f3..b43b4a8 100644 --- a/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_16b2lane.v +++ b/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_16b2lane.v @@ -27,8 +27,7 @@ module mipi_csi_rx_packet_decoder_16b2lane( output_valid_o, data_o, packet_length_o, - packet_type_o, - debug_o + packet_type_o ); localparam [7:0]MIPI_GEAR = 16; localparam [3:0]LANES = 3'h2; @@ -46,11 +45,9 @@ output reg output_valid_o; output reg [15:0]packet_length_o; output reg [2:0]packet_type_o; -output [15:0]debug_o; reg [15:0]packet_length_reg; reg [((MIPI_GEAR * LANES) - 1'h1):0]data_reg; -assign debug_o = packet_length_reg; //packet format diff --git a/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_16b4lane.v b/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_16b4lane.v index 9350c9c..1085812 100644 --- a/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_16b4lane.v +++ b/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_16b4lane.v @@ -27,8 +27,7 @@ module mipi_csi_rx_packet_decoder_16b4lane( output_valid_o, data_o, packet_length_o, - packet_type_o, - debug_o + packet_type_o ); localparam [7:0]MIPI_GEAR = 16; localparam [3:0]LANES = 3'h4; @@ -46,12 +45,10 @@ output reg output_valid_o; output reg [15:0]packet_length_o; output reg [2:0]packet_type_o; -output [15:0]debug_o; reg output_valid_reg; reg [15:0]packet_length_reg; reg [((MIPI_GEAR * LANES) - 1'h1):0]data_reg; -assign debug_o = packet_length_reg; //packet format always @(posedge clk_i) @@ -67,7 +64,6 @@ begin end else if (data_reg[7:0] == SYNC_BYTE && (data_reg[15:8] == MIPI_CSI_PACKET_10bRAW || data_reg[15:8] == MIPI_CSI_PACKET_12bRAW || data_reg[15:8] == MIPI_CSI_PACKET_14bRAW)) begin - //TODO: better timings could be achieved by just copy whole data_reg into a reg and later take individual values from that reg packet_type_o <= data_reg[10:8]; packet_length_o <= {data_reg[47:40], data_reg[31:24]}; packet_length_reg <= {data_reg[47:40], data_reg[31:24]}; diff --git a/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_8b2lane.v b/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_8b2lane.v index af0405d..ce22bca 100644 --- a/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_8b2lane.v +++ b/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_8b2lane.v @@ -26,8 +26,7 @@ module mipi_csi_rx_packet_decoder_8b2lane( output_valid_o, data_o, packet_length_o, - packet_type_o, - debug_o + packet_type_o ); localparam [7:0]MIPI_GEAR = 8; localparam [3:0]LANES = 3'h2; @@ -45,13 +44,11 @@ output reg output_valid_o; output reg [15:0]packet_length_o; output reg [2:0]packet_type_o; -output [15:0]debug_o; reg output_valid_reg; reg [15:0]packet_length_reg; reg [((MIPI_GEAR * LANES) - 1'h1) :0]data_reg; -assign debug_o = packet_length_reg; //packet format diff --git a/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_8b4lane.v b/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_8b4lane.v index a61e743..0b719e1 100644 --- a/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_8b4lane.v +++ b/FPGA_Firmware/Source/src/mipi_csi_rx_packet_decoder_8b4lane.v @@ -27,8 +27,7 @@ module mipi_csi_rx_packet_decoder_8b4lane( output_valid_o, data_o, packet_length_o, - packet_type_o, - debug_o + packet_type_o ); localparam [7:0]MIPI_GEAR = 8; localparam [3:0]LANES = 3'h4; @@ -46,11 +45,9 @@ output reg output_valid_o; output reg [15:0]packet_length_o; output reg [2:0]packet_type_o; -output [15:0]debug_o; reg [15:0]packet_length_reg; reg [((MIPI_GEAR * LANES) - 1'h1):0]data_reg; -assign debug_o = packet_length_reg; //packet format always @(posedge clk_i) diff --git a/FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_16b4lane.v b/FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_16b4lane.v index 3d40349..aaf459b 100644 --- a/FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_16b4lane.v +++ b/FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_16b4lane.v @@ -11,7 +11,7 @@ work. If not, see . */ /* -Receives 4 lane raw mipi bytes from packet decoder, rearrange bytes to output 8 pixel 16bit each +Receives 4 lane raw mipi bytes from packet decoder, rearrange bytes to output 8 pixel upto 16bit each output is one clock cycle delayed, because the way , MIPI RAW is packed output come in chunk on each clock cycle, output_valid_o remains active only while 20 pixel chunk is outputted */ @@ -24,7 +24,7 @@ module mipi_csi_rx_raw_depacker_16b4lane( clk_i, output_valid_o, output_o); -localparam [2:0]TRANSFERS_PERCHUNK= 3'h5; // RAW 10 is packed + localparam [7:0]MIPI_CSI_PACKET_10bRAW = 8'h2B; localparam [7:0]MIPI_CSI_PACKET_12bRAW = 8'h2C; localparam [7:0]MIPI_CSI_PACKET_14bRAW = 8'h2D; diff --git a/FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b2lane_2ppc.v b/FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b2lane_2ppc.v index 0424c48..ac784c8 100644 --- a/FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b2lane_2ppc.v +++ b/FPGA_Firmware/Source/src/mipi_csi_rx_raw_depacker_8b2lane_2ppc.v @@ -96,11 +96,11 @@ begin output_10b[(PIXEL_WIDTH) +: PIXEL_WIDTH] = {pipe [offset_pixel_1 +:8], pipe[(offset_pixel_lsb1+2) +:2], {(PIXEL_WIDTH - 10){1'b0}}}; //lane 2 //add ( PIXEL_WIDTH - 10 ) padding in the LSbits output_10b[0 +: PIXEL_WIDTH] = {pipe [offset_pixel_0 +:8], pipe[offset_pixel_lsb1 +:2], {(PIXEL_WIDTH - 10){1'b0}}}; //lane 1 first pixel on wire - //additional LSbits are as follow [ pixel3 pixel2 pixel 1 pixel0] + //RAW10 additional LSbits are as follow [ pixel3 pixel2 pixel 1 pixel0] output_12b[(PIXEL_WIDTH) +: PIXEL_WIDTH] = {pipe [offset12_pixel_1 +:8], pipe[(offset12_pixel_lsb1+4) +:4], {(PIXEL_WIDTH - 12){1'b0}}}; output_12b[0 +: PIXEL_WIDTH] = {pipe [offset12_pixel_0 +:8], pipe[offset12_pixel_lsb1 +:4], {(PIXEL_WIDTH - 12){1'b0}}}; //lane 1 first pixel on wire - //additional LSbits are as follow [pixel 1 pixel0] + //RAW12 additional LSbits are as follow [pixel 1 pixel0] /* output_14b[31:16] = {pipe [offset_15 -:8], pipe [offset_43 -:6]} << 2;