From de5fcf284f24e080c37b0530dbe983ba0452c9b3 Mon Sep 17 00:00:00 2001
From: gaurav <gauravsingh@circuitvalley.com>
Date: Mon, 11 Jul 2022 20:58:41 +0200
Subject: [PATCH] Moved IP and there files

---
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/csi_dphy.cfg       | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/csi_dphy.v         | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/dphy_dummy.cfg     | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/dphy_dummy.v       | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/int_osc.v          | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/line_ram_dp.cfg    | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/line_ram_dp.v      | 0
 .../Source/src/{ => Lattice_specfic}/out_line_ram_dp.cfg          | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/out_line_ram_dp.v  | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/rom_first.cfg      | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/rom_first.v        | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/rom_sec.cfg        | 0
 FPGA_Firmware/Source/src/{ => Lattice_specfic}/rom_sec.v          | 0
 13 files changed, 0 insertions(+), 0 deletions(-)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/csi_dphy.cfg (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/csi_dphy.v (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/dphy_dummy.cfg (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/dphy_dummy.v (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/int_osc.v (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/line_ram_dp.cfg (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/line_ram_dp.v (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/out_line_ram_dp.cfg (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/out_line_ram_dp.v (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/rom_first.cfg (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/rom_first.v (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/rom_sec.cfg (100%)
 rename FPGA_Firmware/Source/src/{ => Lattice_specfic}/rom_sec.v (100%)

diff --git a/FPGA_Firmware/Source/src/csi_dphy.cfg b/FPGA_Firmware/Source/src/Lattice_specfic/csi_dphy.cfg
similarity index 100%
rename from FPGA_Firmware/Source/src/csi_dphy.cfg
rename to FPGA_Firmware/Source/src/Lattice_specfic/csi_dphy.cfg
diff --git a/FPGA_Firmware/Source/src/csi_dphy.v b/FPGA_Firmware/Source/src/Lattice_specfic/csi_dphy.v
similarity index 100%
rename from FPGA_Firmware/Source/src/csi_dphy.v
rename to FPGA_Firmware/Source/src/Lattice_specfic/csi_dphy.v
diff --git a/FPGA_Firmware/Source/src/dphy_dummy.cfg b/FPGA_Firmware/Source/src/Lattice_specfic/dphy_dummy.cfg
similarity index 100%
rename from FPGA_Firmware/Source/src/dphy_dummy.cfg
rename to FPGA_Firmware/Source/src/Lattice_specfic/dphy_dummy.cfg
diff --git a/FPGA_Firmware/Source/src/dphy_dummy.v b/FPGA_Firmware/Source/src/Lattice_specfic/dphy_dummy.v
similarity index 100%
rename from FPGA_Firmware/Source/src/dphy_dummy.v
rename to FPGA_Firmware/Source/src/Lattice_specfic/dphy_dummy.v
diff --git a/FPGA_Firmware/Source/src/int_osc.v b/FPGA_Firmware/Source/src/Lattice_specfic/int_osc.v
similarity index 100%
rename from FPGA_Firmware/Source/src/int_osc.v
rename to FPGA_Firmware/Source/src/Lattice_specfic/int_osc.v
diff --git a/FPGA_Firmware/Source/src/line_ram_dp.cfg b/FPGA_Firmware/Source/src/Lattice_specfic/line_ram_dp.cfg
similarity index 100%
rename from FPGA_Firmware/Source/src/line_ram_dp.cfg
rename to FPGA_Firmware/Source/src/Lattice_specfic/line_ram_dp.cfg
diff --git a/FPGA_Firmware/Source/src/line_ram_dp.v b/FPGA_Firmware/Source/src/Lattice_specfic/line_ram_dp.v
similarity index 100%
rename from FPGA_Firmware/Source/src/line_ram_dp.v
rename to FPGA_Firmware/Source/src/Lattice_specfic/line_ram_dp.v
diff --git a/FPGA_Firmware/Source/src/out_line_ram_dp.cfg b/FPGA_Firmware/Source/src/Lattice_specfic/out_line_ram_dp.cfg
similarity index 100%
rename from FPGA_Firmware/Source/src/out_line_ram_dp.cfg
rename to FPGA_Firmware/Source/src/Lattice_specfic/out_line_ram_dp.cfg
diff --git a/FPGA_Firmware/Source/src/out_line_ram_dp.v b/FPGA_Firmware/Source/src/Lattice_specfic/out_line_ram_dp.v
similarity index 100%
rename from FPGA_Firmware/Source/src/out_line_ram_dp.v
rename to FPGA_Firmware/Source/src/Lattice_specfic/out_line_ram_dp.v
diff --git a/FPGA_Firmware/Source/src/rom_first.cfg b/FPGA_Firmware/Source/src/Lattice_specfic/rom_first.cfg
similarity index 100%
rename from FPGA_Firmware/Source/src/rom_first.cfg
rename to FPGA_Firmware/Source/src/Lattice_specfic/rom_first.cfg
diff --git a/FPGA_Firmware/Source/src/rom_first.v b/FPGA_Firmware/Source/src/Lattice_specfic/rom_first.v
similarity index 100%
rename from FPGA_Firmware/Source/src/rom_first.v
rename to FPGA_Firmware/Source/src/Lattice_specfic/rom_first.v
diff --git a/FPGA_Firmware/Source/src/rom_sec.cfg b/FPGA_Firmware/Source/src/Lattice_specfic/rom_sec.cfg
similarity index 100%
rename from FPGA_Firmware/Source/src/rom_sec.cfg
rename to FPGA_Firmware/Source/src/Lattice_specfic/rom_sec.cfg
diff --git a/FPGA_Firmware/Source/src/rom_sec.v b/FPGA_Firmware/Source/src/Lattice_specfic/rom_sec.v
similarity index 100%
rename from FPGA_Firmware/Source/src/rom_sec.v
rename to FPGA_Firmware/Source/src/Lattice_specfic/rom_sec.v