Agis Zisimatos
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250e636a27
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Fix PN in TRX
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-07-29 16:19:24 +03:00 |
Vasilis Tsiligiannis
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d734fccc39
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gitlab-ci: Make sure commits are signed-off before merge
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
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2022-07-27 13:54:18 +03:00 |
Agis Zisimatos
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bc2c925c7a
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Fixes in net names, PN, new hierirchical labels
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-07-19 14:52:07 +03:00 |
Ilias Daradimos
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40de4742d5
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Sync components
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2022-07-19 14:47:28 +03:00 |
Agis Zisimatos
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cb77450ceb
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Add RC to delay the enable of 2V5 LDO
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-07-15 14:09:57 +03:00 |
Agis Zisimatos
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871bc8ed23
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Replace load switches
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-07-15 13:37:50 +03:00 |
Ilias Daradimos
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6b96ba272d
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Update antenna components
Fix CAN annotation
Add MCU telemetry GPIO
Add OpAmp activation input
Add optocoupled activation input
Signed-off-by: Ilias Daradimos <judgedrid@gmail.com>
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2022-07-12 17:07:59 +03:00 |
Ilias Daradimos
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c06d90993a
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Reannotate
Rename port pins
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2022-06-14 14:17:59 +03:00 |
Ilias Daradimos
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920c27ce8e
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Add isolated kill switch
Rename CS pins
Signed-off-by: Ilias Daradimos <judgedrid@gmail.com>
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2022-06-10 17:57:28 +03:00 |
Ilias Daradimos
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70bf9afa9e
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Redesign RBF
Signed-off-by: Ilias Daradimos <judgedrid@gmail.com>
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2022-05-23 16:17:20 +03:00 |
Ilias Daradimos
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4fa8a92018
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Update BQ24013 symbol
Change MCU TCXO
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-05-20 14:37:50 +03:00 |
Ilias Daradimos
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0bc5d44dd0
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Remove VSEL
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-05-19 17:16:49 +03:00 |
Ilias Daradimos
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5d976e15a8
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PG to RST
Charger always on
Add fuse RBF
Recalculate DCDC RC
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-05-19 15:55:04 +03:00 |
Ilias Daradimos
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f05a79bfc6
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Fix HLabels direction
Add fuse RBF
closes #21
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-05-19 14:21:39 +03:00 |
Ilias Daradimos
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0ba5d4e8ac
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Update part numbers
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-05-12 14:55:55 +03:00 |
Agis Zisimatos
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efe1cafcf9
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Update BOM and delete wrong part description
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-05-02 14:22:23 +03:00 |
Agis Zisimatos
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d2c2e2270d
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Exclude test points form BOM
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-30 20:24:41 +03:00 |
Agis Zisimatos
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276cab3b18
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Fix connections in RN601 that helps in routing
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-30 14:21:21 +03:00 |
Agis Zisimatos
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a8ec6c893f
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Add in series termination in FPGA SPI
Add as option because SPI runs out of board.
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-30 13:18:47 +03:00 |
Agis Zisimatos
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b07c5fff98
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Fix clock-in pins
Add them in clock compatible pins for PLL.
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-30 11:28:11 +03:00 |
Agis Zisimatos
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9d9a499b54
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Add hierarchical label FPGA_3V3 to use it in JTAG
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-26 13:55:56 +03:00 |
Agis Zisimatos
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5b0f13295b
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Add missing capacitor to VCCIO bank-3
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-26 13:46:57 +03:00 |
Agis Zisimatos
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05aedba620
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Change SPI CLK pin to L18 from M20
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-26 13:31:17 +03:00 |
Agis Zisimatos
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9b03d488d5
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Add debug LED of FPGA
Fixes #42
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-19 19:47:58 +03:00 |
Agis Zisimatos
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651edca938
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Split RN in NOR flash to single R's
Helping in FPGA routing
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-19 14:58:39 +03:00 |
Agis Zisimatos
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c8a1410dfc
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Swap pins in RN of JTAG
Helps in PCB routing
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-18 15:34:41 +03:00 |
Agis Zisimatos
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b143aba082
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Add Bank-3 of FPGA for SPI
Helps more in routing
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-18 15:14:00 +03:00 |
Ilias Daradimos
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427ce69151
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Update part numbers
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2022-04-11 17:03:21 +00:00 |
Agis Zisimatos
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892b8d7188
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Fix ERC errors of high level schematic
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-11 13:27:38 +03:00 |
Agis Zisimatos
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6dba8e700b
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Replace single resistors with resistor network
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2022-04-11 09:58:56 +00:00 |
Agis Zisimatos
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0ea9754b22
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Fix FPGA symbol anotation and footprint
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-08 18:07:34 +03:00 |
Ilias Daradimos
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8eca352efe
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Restore footprints
Add RBF diode
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-08 14:09:25 +03:00 |
Agis Zisimatos
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62e9a7579b
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Add SERDES bank and connect supply voltaged to GND
* Add a fpga-power sheet
* Add auto updated kicad files
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-08 11:28:44 +03:00 |
Agis Zisimatos
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791fa839b6
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Remove unused test points
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2022-04-07 17:52:45 +00:00 |
Papadeas Pierros
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cb2ff9e057
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Replace diode footprints and jumpers in CAN
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-04-07 15:30:01 +03:00 |
Ilias Daradimos
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3ea2211549
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Update footprints
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-07 11:21:18 +03:00 |
Ilias Daradimos
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17e77121dc
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Add latching mechanism
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-07 11:07:47 +03:00 |
Ilias Daradimos
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d9640c0ea0
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Add RBF/Kill ports
Add can footprint
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-06 23:27:16 +03:00 |
Agis Zisimatos
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21e81aed53
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Fix connection of INITN and DONE
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-06 19:16:15 +03:00 |
Agis Zisimatos
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5754075d13
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Add changes of auto updated KiCad files
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-06 18:50:03 +03:00 |
Agis Zisimatos
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625d39c64e
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Add missing pull-up resistor
Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 19:54:51 +03:00 |
Agis Zisimatos
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94313541b0
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Clean up the FPGA schematic from comments
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 19:54:51 +03:00 |
Agis Zisimatos
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bdd3c06adf
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Add decoupling capacitors in FPGA schematic
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 19:54:51 +03:00 |
Ilias Daradimos
|
80eade29ba
|
Change battery footprint
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-05 16:00:20 +03:00 |
Ilias Daradimos
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cf1e87d61d
|
Assign footprints
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2022-04-05 14:39:51 +03:00 |
Agis Zisimatos
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be0d0789f9
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Add FPGA_INIT to MCU, fixes #13
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:27:50 +03:00 |
Agis Zisimatos
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c3122ab59c
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Add oscillator in FPGA
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:06:18 +03:00 |
Agis Zisimatos
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fb9e050bc9
|
Add test points for GPIOs
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:06:18 +03:00 |
Agis Zisimatos
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8b5c631826
|
Add MSPI as default boot mode and NOR flash
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:06:18 +03:00 |
Agis Zisimatos
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0e86bb6f49
|
Add LED indicators for DONE and INITN
Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 11:06:18 +03:00 |