From 12dd47cf35e771831b7e184dd9b09258ad01e9d7 Mon Sep 17 00:00:00 2001 From: Agis Zisimatos Date: Tue, 12 Apr 2022 16:02:42 +0300 Subject: [PATCH] Define stack-up and manufacturer rules * Define also net classes and pre-define traces and vias * Fixes #2 Signed-off-by: Agis Zisimatos --- sidloc-schematic | 2 +- sidloc-transceiver.kicad_pcb | 373 +++++++++++++++++++++-------------- sidloc-transceiver.kicad_pro | 86 ++++++-- 3 files changed, 293 insertions(+), 168 deletions(-) diff --git a/sidloc-schematic b/sidloc-schematic index 892b8d7..427ce69 160000 --- a/sidloc-schematic +++ b/sidloc-schematic @@ -1 +1 @@ -Subproject commit 892b8d7188ebc81fd6dd7fa2f54b974cd2a5a430 +Subproject commit 427ce69151eae2cb11805eb1ea140d3b9ef543bd diff --git a/sidloc-transceiver.kicad_pcb b/sidloc-transceiver.kicad_pcb index 6c2579e..b5508e2 100644 --- a/sidloc-transceiver.kicad_pcb +++ b/sidloc-transceiver.kicad_pcb @@ -1,13 +1,15 @@ (kicad_pcb (version 20211014) (generator pcbnew) (general - (thickness 1.6) + (thickness 1.5954) ) (paper "A4") (layers - (0 "F.Cu" signal) - (31 "B.Cu" signal) + (0 "F.Cu" mixed) + (1 "In1.Cu" power) + (2 "In2.Cu" power) + (31 "B.Cu" mixed) (32 "B.Adhes" user "B.Adhesive") (33 "F.Adhes" user "F.Adhesive") (34 "B.Paste" user) @@ -28,8 +30,25 @@ ) (setup - (pad_to_mask_clearance 0.2) - (solder_mask_min_width 0.25) + (stackup + (layer "F.SilkS" (type "Top Silk Screen") (color "White")) + (layer "F.Paste" (type "Top Solder Paste")) + (layer "F.Mask" (type "Top Solder Mask") (color "Purple") (thickness 0.0127)) + (layer "F.Cu" (type "copper") (thickness 0.035)) + (layer "dielectric 1" (type "prepreg") (thickness 0.1) (material "JLC2313") (epsilon_r 4.05) (loss_tangent 0)) + (layer "In1.Cu" (type "copper") (thickness 0.0175)) + (layer "dielectric 2" (type "core") (thickness 1.265) (material "Core") (epsilon_r 4.6) (loss_tangent 0)) + (layer "In2.Cu" (type "copper") (thickness 0.0175)) + (layer "dielectric 3" (type "prepreg") (thickness 0.1) (material "JLC2313") (epsilon_r 4.05) (loss_tangent 0)) + (layer "B.Cu" (type "copper") (thickness 0.035)) + (layer "B.Mask" (type "Bottom Solder Mask") (color "Purple") (thickness 0.0127)) + (layer "B.Paste" (type "Bottom Solder Paste")) + (layer "B.SilkS" (type "Bottom Silk Screen") (color "White")) + (copper_finish "ENIG") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0.05) + (solder_mask_min_width 0.2) (grid_origin 171.1452 89.472) (pcbplotparams (layerselection 0x0000030_80000001) @@ -1744,51 +1763,6 @@ ) ) - (footprint "Resistor_SMD:R_0402_1005Metric" (layer "F.Cu") - (tedit 5F68FEEE) (tstamp 1d7bbbd0-21f0-4f2d-a69a-5e998c28ea6c) - (at 192.786 63.1068) - (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") - (tags "resistor") - (property "Description" "Resistor, 0402, 1%, 1/16W") - (property "Mnf." "Vishay") - (property "PartNumber" "CRCW04024K70FKEDC") - (property "Sheetfile" "sidloc-schematic/fpga.kicad_sch") - (property "Sheetname" "fpga") - (path "/3c19fda9-55de-469e-9693-2d8993bca106/f58f6b7a-5abe-42d5-92a7-6524c54ddb0f") - (attr smd) - (fp_text reference "R618" (at 0 -1.17) (layer "F.SilkS") - (effects (font (size 1 1) (thickness 0.15))) - (tstamp 0bc08b59-b477-45c7-ac6f-cd6ea5215553) - ) - (fp_text value "4.7k" (at 0 1.17) (layer "F.Fab") - (effects (font (size 1 1) (thickness 0.15))) - (tstamp afc5e55a-202b-4aa4-abae-064b0b0d7355) - ) - (fp_text user "${REFERENCE}" (at 0 0) (layer "F.Fab") - (effects (font (size 0.26 0.26) (thickness 0.04))) - (tstamp dc0ab57a-08c6-4903-a0bd-d9681b9897b7) - ) - (fp_line (start -0.153641 -0.38) (end 0.153641 -0.38) (layer "F.SilkS") (width 0.12) (tstamp 3c4c8720-f488-4de7-ad2e-ec7c55067fa0)) - (fp_line (start -0.153641 0.38) (end 0.153641 0.38) (layer "F.SilkS") (width 0.12) (tstamp a70f7ffb-c447-47cf-b156-d3abd10840ce)) - (fp_line (start -0.93 0.47) (end -0.93 -0.47) (layer "F.CrtYd") (width 0.05) (tstamp 3fb4210f-d6d6-48ba-a14d-4e5ecc3f9419)) - (fp_line (start -0.93 -0.47) (end 0.93 -0.47) (layer "F.CrtYd") (width 0.05) (tstamp 619d288f-0a6c-4168-bb71-6862242d2276)) - (fp_line (start 0.93 0.47) (end -0.93 0.47) (layer "F.CrtYd") (width 0.05) (tstamp 65e54678-07f1-4e1a-86c9-8998e7a87d45)) - (fp_line (start 0.93 -0.47) (end 0.93 0.47) (layer "F.CrtYd") (width 0.05) (tstamp fb1ec32c-a8bc-4c0d-bf25-5fbf4396f946)) - (fp_line (start -0.525 0.27) (end -0.525 -0.27) (layer "F.Fab") (width 0.1) (tstamp 0515fbac-612d-4152-abd1-233fcaf8b1c2)) - (fp_line (start 0.525 -0.27) (end 0.525 0.27) (layer "F.Fab") (width 0.1) (tstamp 352e48f4-c707-41d4-a86f-bf6a44c69082)) - (fp_line (start 0.525 0.27) (end -0.525 0.27) (layer "F.Fab") (width 0.1) (tstamp c1381113-d512-4768-829a-317a7c2858cc)) - (fp_line (start -0.525 -0.27) (end 0.525 -0.27) (layer "F.Fab") (width 0.1) (tstamp f9334a63-93bc-4354-b2f0-3e01cadf7efa)) - (pad "1" smd roundrect (at -0.51 0) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) - (net 1 "GND") (pintype "passive") (tstamp 22e4536a-1fee-4cb6-9d93-14572e6eff08)) - (pad "2" smd roundrect (at 0.51 0) (size 0.54 0.64) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25) - (net 51 "Net-(R618-Pad2)") (pintype "passive") (tstamp 4ed39af4-ba05-403e-bb79-86073a523712)) - (model "${KICAD6_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.wrl" - (offset (xyz 0 0 0)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 0)) - ) - ) - (footprint "Inductor_SMD:L_0603_1608Metric" (layer "F.Cu") (tedit 5F68FEF0) (tstamp 246942fb-cd9b-4027-975b-57e38b736fc3) (at 166.0906 109.7412 180) @@ -4382,51 +4356,6 @@ ) ) - (footprint "Resistor_SMD:R_0402_1005Metric" (layer "F.Cu") - (tedit 5F68FEEE) (tstamp 977fed18-97d8-4b0e-b387-958493e36fec) - (at 192.786 61.1256) - (descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator") - (tags "resistor") - (property "Description" "Resistor, 0402, 1%, 1/16W") - (property "Mnf." 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}, + { + "gap": 0.2, + "via_gap": 0.5, + "width": 0.12 + } + ], "drc_exclusions": [], "meta": { "filename": "board_design_settings.json", @@ -98,22 +109,37 @@ "allow_blind_buried_vias": false, "allow_microvias": false, "max_error": 0.005, - "min_clearance": 0.0, - "min_copper_edge_clearance": 0.075, - "min_hole_clearance": 0.25, + "min_clearance": 0.09999999999999999, + "min_copper_edge_clearance": 0.19999999999999998, + "min_hole_clearance": 0.19999999999999998, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.0, + "min_microvia_drill": 0.0, "min_silk_clearance": 0.0, - "min_through_hole_diameter": 0.3, - "min_track_width": 0.19999999999999998, - "min_via_annular_width": 0.049999999999999996, + "min_through_hole_diameter": 0.19999999999999998, + "min_track_width": 0.09999999999999999, + "min_via_annular_width": 0.13, "min_via_diameter": 0.39999999999999997, "use_height_for_length_calcs": true }, - "track_widths": [], - "via_dimensions": [], - "zones_allow_external_fillets": false, + "track_widths": [ + 0.0, + 0.14, + 0.2, + 0.6, + 1.0 + ], + "via_dimensions": [ + { + "diameter": 0.0, + "drill": 0.0 + }, + { + "diameter": 0.5, + "drill": 0.2 + } + ], + "zones_allow_external_fillets": true, "zones_use_no_outline": true }, "layer_presets": [] @@ -339,19 +365,43 @@ "classes": [ { "bus_width": 12.0, - "clearance": 0.2, - "diff_pair_gap": 0.25, + "clearance": 0.1, + "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, - "diff_pair_width": 0.2, + "diff_pair_width": 0.12, "line_style": 0, "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", "schematic_color": "rgba(0, 0, 0, 0.000)", - "track_width": 0.25, - "via_diameter": 0.6, - "via_drill": 0.4, + "track_width": 0.2, + "via_diameter": 0.5, + "via_drill": 0.2, + "wire_width": 6.0 + }, + { + "bus_width": 12.0, + "clearance": 0.1, + "diff_pair_gap": 0.1, + "diff_pair_via_gap": 0.25, + "diff_pair_width": 0.35, + "line_style": 0, + "microvia_diameter": 0.3, + "microvia_drill": 0.1, + "name": "50-Ohm", + "nets": [ + "/fpga/CFG_CLK", + "/transceiver/RF09CAP_N", + "/transceiver/RF09CAP_P", + "/transceiver/RF09N", + "/transceiver/RF09P" + ], + "pcb_color": "rgba(0, 0, 0, 0.000)", + "schematic_color": "rgba(0, 0, 0, 0.000)", + "track_width": 0.14, + "via_diameter": 0.5, + "via_drill": 0.2, "wire_width": 6.0 } ],