spacecruft
/
sidloc-transceiver
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
33 Commits
3 Branches
1 Tag
1.1 MiB
Commit Graph

33 Commits (spacecruft)

Author SHA1 Message Date
root 6ce0099984 Ignore kicad tmp files 2022-07-31 15:22:20 -06:00
Vasilis Tsiligiannis 8ba0aa0137 gitlab-ci: Introduce sign-off check 
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
 2022-07-27 14:42:05 +03:00
Agis Zisimatos 7dd800fd65 Fix net names, PN and add connector for FE 
Fixes #57, #56, #58, #59, #52, #65

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-07-19 18:49:46 +03:00
Agis Zisimatos df8add0c12 Add LSF logo and fix egde GND via 
Fixes #50, #51

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-07-19 13:36:43 +03:00
Agis Zisimatos 9efb3758c7 Fixes in power part, #54 and #64 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-07-19 13:08:57 +03:00
Agis Zisimatos bb1401747f Add missing via in core power supply 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-05-03 12:41:16 +03:00
Agis Zisimatos 6780198daf Update BOM and create iBOM 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-05-02 14:38:21 +03:00
Agis Zisimatos 5f59684ccc Fix mask leyer clearance 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 19:03:22 +03:00
Agis Zisimatos ca58d73eb6 Add more vias in power planes 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 18:41:48 +03:00
Agis Zisimatos 538108bb67 Fix TPS22950 footprint 
Add the correct one for LSF-KiCAD library

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 17:48:22 +03:00
Agis Zisimatos f97d888e83 Fix via in pad in JTAG connector 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 14:52:25 +03:00
Agis Zisimatos cc07c2347f Add in-series resistors in FPGA-SPI 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 14:29:44 +03:00
Agis Zisimatos 77dad4e17f Fix clock-in in FPGA pins 
Fixes #28

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 13:13:09 +03:00
Agis Zisimatos 5f79558cec Fix CLK test point 
Remove unterminated length to TP.

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-27 20:08:42 +03:00
Papadeas Pierros 077a05bce5 Fix small silkscreen clarity issues 
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
 2022-04-27 15:20:17 +03:00
Agis Zisimatos fa98f4d20a Add silkscreen 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-27 12:27:46 +03:00
Agis Zisimatos 8fc3b2df0d Update in PCB from sidloc schematic 
* Change SPI CLK of FPGA to L18
* Fixes #44 and #45

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-26 17:04:15 +03:00
Agis Zisimatos aa2a8d5806 Route power of FPGA and finalize I/Q connections 
* Fixes #29 and #31
* Add TP in VIN 3.3V from external

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-26 13:13:08 +03:00
Agis Zisimatos ecf17cc8eb Add debug LED for FPGA in PCB 
Fixes #42

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-19 19:57:11 +03:00
Agis Zisimatos 65c1553f29 Add SPI routing of FPGA 
* Route pull-up resistors of NOR flash
* Small fixes in AT86RF215, fixes #30
* Route pull-up and down resistors of JTAG

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-19 19:27:25 +03:00
Agis Zisimatos d22b3f5865 Route AT86RF215M, fixes #30 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-18 22:12:15 +03:00
Agis Zisimatos 961e955dbd Fix SPI_CLK connection 
It had connected to CS

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-18 21:10:33 +03:00
Agis Zisimatos 1230dde0f7 Place and route NOR flash 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-12 18:01:06 +03:00
Agis Zisimatos 12dd47cf35 Define stack-up and manufacturer rules 
* Define also net classes and pre-define traces and vias
* Fixes #2

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-12 16:31:58 +03:00
Agis Zisimatos bbb8da9459 Initial part placement 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-11 19:07:49 +03:00
Agis Zisimatos 0f946970ff Assign footprints 
Use PQ9ish template

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-08 22:09:47 +03:00
Agis Zisimatos c9c6807e57 Fix interface with MCU breadboard 
Fixes #19

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-07 19:01:15 +03:00
Agis Zisimatos b4a8816f07 Add PQ9ish template 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-07 13:42:06 +03:00
Agis Zisimatos 751f54fc0b Initialize schematics and define connectors 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-06 21:10:42 +03:00
Vasilis Tsiligiannis e14ddaa453 Add LSF contribution guide 
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
 2022-03-28 10:28:46 +03:00
Vasilis Tsiligiannis a097141eab Add SIDLOC schematic as a submodule 
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
 2022-03-15 18:37:42 +02:00
Vasilis Tsiligiannis 1f24b26fbe Initialize empty KiCad project 
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
 2022-03-15 18:35:16 +02:00
Vasilis Tsiligiannis 38b7e0ee2e Add license file 
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
 2022-03-15 18:30:30 +02:00