Inital commit of stm32f4xx framework.
Damien
parent
3ef4abb446
commit
ed65605edc
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build
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STMSRC=lib
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FATFSSRC=fatfs
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PYSRC=../py
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BUILD=build
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AS = arm-none-eabi-as
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CC = arm-none-eabi-gcc
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LD = arm-none-eabi-ld
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CFLAGS_CORTEX_M4 = -mthumb -mtune=cortex-m4 -mabi=aapcs-linux -mcpu=cortex-m4 -mfloat-abi=hard -DSTM32F40XX -DHSE_VALUE=8000000
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CFLAGS = -I. -I$(PYSRC) -I$(FATFSSRC) -I$(STMSRC) -Wall -ansi -std=gnu99 -Os -DNDEBUG $(CFLAGS_CORTEX_M4)
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CFLAGS_PY = -DEMIT_ENABLE_THUMB
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LDFLAGS = --nostdlib -T stm.ld
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SRC_C = \
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main.c \
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printf.c \
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system_stm32f4xx.c \
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flash.c \
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string0.c \
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malloc0.c \
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stm32fxxx_it.c \
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usb.c \
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# sd.c \
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SRC_S = \
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delay.s \
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startup_stm32f40xx.s \
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PY_O = \
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# malloc.o \
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qstr.o \
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misc.o \
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lexer.o \
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parse.o \
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scope.o \
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compile.o \
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emitcommon.o \
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emitpass1.o \
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emitbc.o \
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asmthumb.o \
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emitnthumb.o \
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emitinlinethumb.o \
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runtime.o \
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vm.o \
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SRC_FATFS = \
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ff.c \
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diskio.c \
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SRC_STM = \
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stm32f4xx_rcc.c \
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stm32f4xx_flash.c \
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stm32f4xx_dma.c \
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stm32f4xx_exti.c \
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stm32f4xx_gpio.c \
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stm_misc.c \
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usb_core.c \
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usb_dcd.c \
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usb_dcd_int.c \
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usb_bsp.c \
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usbd_core.c \
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usbd_ioreq.c \
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usbd_req.c \
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usbd_usr.c \
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usbd_desc.c \
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usbd_cdc_core.c \
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usbd_cdc_vcp.c \
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usbd_msc_bot.c \
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usbd_msc_core.c \
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usbd_msc_data.c \
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usbd_msc_scsi.c \
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usbd_storage_msd.c \
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# not needed
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# usb_otg.c \
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# usb_hcd.c \
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# usb_hcd_int.c \
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# for SD card
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# stm32f4xx_sdio.c \
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# stm324x7i_eval.c \
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# stm324x7i_eval_sdio_sd.c \
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OBJ = $(addprefix $(BUILD)/, $(SRC_C:.c=.o) $(SRC_S:.s=.o) $(PY_O) $(SRC_FATFS:.c=.o) $(SRC_STM:.c=.o))
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all: $(BUILD) $(BUILD)/flash.dfu
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$(BUILD)/flash.dfu: $(BUILD)/flash.bin
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python2 ~/stm/dfu/dfu.py -b 0x08000000:$< $@
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$(BUILD)/flash.bin: $(BUILD)/flash.elf
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arm-none-eabi-objcopy -O binary -j .isr_vector -j .text -j .data $^ $@
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$(BUILD)/flash.elf: $(OBJ)
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$(LD) $(LDFLAGS) -o $@ $(OBJ)
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arm-none-eabi-size $@
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$(BUILD):
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mkdir $@
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$(BUILD)/%.o: %.s
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$(AS) -o $@ $<
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$(BUILD)/%.o: %.c
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$(CC) $(CFLAGS) -c -o $@ $<
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$(BUILD)/%.o: $(FATFSSRC)/%.c
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$(CC) $(CFLAGS) -c -o $@ $<
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$(BUILD)/%.o: $(STMSRC)/%.c
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$(CC) $(CFLAGS) -c -o $@ $<
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$(BUILD)/%.o: $(PYSRC)/%.c mpyconfig.h
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$(CC) $(CFLAGS) $(CFLAGS_PY) -c -o $@ $<
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$(BUILD)/emitnthumb.o: $(PYSRC)/emitnative.c $(PYSRC)/emit.h
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$(CC) $(CFLAGS) $(CFLAGS_PY) -DN_THUMB -c -o $@ $<
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# optimising vm for speed, adds only a small amount to code size but makes a huge difference to speed (20% faster)
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$(BUILD)/vm.o: $(PYSRC)/vm.c
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$(CC) $(CFLAGS) $(CFLAGS_PY) -O3 -c -o $@ $<
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$(BUILD)/parse.o: $(PYSRC)/grammar.h
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$(BUILD)/compile.o: $(PYSRC)/grammar.h
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$(BUILD)/emitbc.o: $(PYSRC)/emit.h
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clean:
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/bin/rm -r $(BUILD)
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.PHONY: all clean
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@ -0,0 +1,28 @@
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.syntax unified
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.cpu cortex-m4
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.thumb
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.text
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.align 2
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.global delay_ms
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.thumb
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.thumb_func
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.type delay_ms, %function
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@ void delay_ms(int ms)
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delay_ms:
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@ r0 is argument, trashes r2, r3
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adds r3, r0, #0
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b .L2
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.L5:
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movw r2, #55999
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b .L3
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.L4:
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subs r2, r2, #1
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.L3:
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cmp r2, #0
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bgt .L4
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subs r3, r3, #1
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.L2:
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cmp r3, #0
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bgt .L5
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bx lr
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.size delay_ms, .-delay_ms
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@ -0,0 +1,272 @@
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/*-----------------------------------------------------------------------*/
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/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2013 */
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/*-----------------------------------------------------------------------*/
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/* If a working storage control module is available, it should be */
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/* attached to the FatFs via a glue function rather than modifying it. */
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/* This is an example of glue functions to attach various exsisting */
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/* storage control module to the FatFs module with a defined API. */
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/*-----------------------------------------------------------------------*/
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#include <stdint.h>
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#include <stdio.h>
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#include "ff.h" /* FatFs lower layer API */
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#include "diskio.h" /* FatFs lower layer API */
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PARTITION VolToPart[] = {
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{0, 1}, // Logical drive 0 ==> Physical drive 0, 1st partition
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/*
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{0, 2}, // Logical drive 1 ==> Physical drive 0, 2nd partition
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{0, 3}, // Logical drive 2 ==> Physical drive 0, 3rd partition
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{1, 0}, // Logical drive 3 ==> Physical drive 1 (auto detection)
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*/
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};
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#define PD_FLASH_SECTOR_SIZE (512)
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#define PD_FLASH_PART1_START_SECTOR (0x100)
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#define PD_FLASH_PART1_NUM_SECTORS (128) // 64k
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#define PD_FLASH_MEM_START_ADDR (0x08020000) // 128k above start, first 128k block
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#define PD_FLASH_RAM_BUF (0x10000000) // CCM data RAM, 64k
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static void pd_flash_init() {
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printf("IN\n");
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// fill RAM buffer
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uint32_t *src = (uint32_t*)PD_FLASH_MEM_START_ADDR;
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uint32_t *dest = (uint32_t*)PD_FLASH_RAM_BUF;
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for (int i = 0; i < PD_FLASH_PART1_NUM_SECTORS * PD_FLASH_SECTOR_SIZE / 4; i++) {
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*dest++ = *src++;
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}
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}
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extern void flash_write(uint32_t flash_dest, const uint32_t *src, uint32_t num_word32);
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static void pd_flash_flush() {
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printf("FL\n");
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// sync the RAM buffer by writing it to the flash page
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flash_write(PD_FLASH_MEM_START_ADDR, (const uint32_t*)PD_FLASH_RAM_BUF, PD_FLASH_PART1_NUM_SECTORS * PD_FLASH_SECTOR_SIZE / 4);
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}
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static void build_partition(uint8_t *buf, int boot, int type, uint32_t start_sector, uint32_t num_sectors) {
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buf[0] = boot;
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if (num_sectors == 0) {
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buf[1] = 0;
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buf[2] = 0;
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buf[3] = 0;
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} else {
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buf[1] = 0xff;
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buf[2] = 0xff;
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buf[3] = 0xff;
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}
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buf[4] = type;
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if (num_sectors == 0) {
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buf[5] = 0;
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buf[6] = 0;
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buf[7] = 0;
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} else {
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buf[5] = 0xff;
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buf[6] = 0xff;
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buf[7] = 0xff;
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}
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buf[8] = start_sector;
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buf[9] = start_sector >> 8;
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buf[10] = start_sector >> 16;
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buf[11] = start_sector >> 24;
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buf[12] = num_sectors;
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buf[13] = num_sectors >> 8;
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buf[14] = num_sectors >> 16;
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buf[15] = num_sectors >> 24;
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}
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static DRESULT pd_flash_read_sector(uint8_t *dest, uint32_t sector) {
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//printf("RD %u\n", sector);
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if (sector == 0) {
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// fake the MBR so we can decide on our own partition table
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for (int i = 0; i < 446; i++) {
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dest[i] = 0;
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}
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build_partition(dest + 446, 0, 0x01 /* FAT12 */, PD_FLASH_PART1_START_SECTOR, PD_FLASH_PART1_NUM_SECTORS);
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build_partition(dest + 462, 0, 0, 0, 0);
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build_partition(dest + 478, 0, 0, 0, 0);
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build_partition(dest + 494, 0, 0, 0, 0);
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dest[510] = 0x55;
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dest[511] = 0xaa;
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return RES_OK;
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} else if (PD_FLASH_PART1_START_SECTOR <= sector && sector < PD_FLASH_PART1_START_SECTOR + PD_FLASH_PART1_NUM_SECTORS) {
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// non-MBR sector(s), just copy straight from flash
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uint8_t *src = (uint8_t*)PD_FLASH_RAM_BUF + (sector - PD_FLASH_PART1_START_SECTOR) * PD_FLASH_SECTOR_SIZE;
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for (int i = PD_FLASH_SECTOR_SIZE; i > 0; i--) {
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*dest++ = *src++;
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}
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return RES_OK;
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} else {
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// bad sector number
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return RES_ERROR;
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}
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}
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static DRESULT pd_flash_write_sector(const uint8_t *src, uint32_t sector) {
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printf("WR %u\n", sector);
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if (sector == 0) {
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// can't write MBR, but pretend we did
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return RES_OK;
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} else if (PD_FLASH_PART1_START_SECTOR <= sector && sector < PD_FLASH_PART1_START_SECTOR + PD_FLASH_PART1_NUM_SECTORS) {
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// non-MBR sector(s), copy to RAM buffer
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uint8_t *dest = (uint8_t*)PD_FLASH_RAM_BUF + (sector - PD_FLASH_PART1_START_SECTOR) * PD_FLASH_SECTOR_SIZE;
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for (int i = PD_FLASH_SECTOR_SIZE; i > 0; i--) {
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*dest++ = *src++;
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}
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return RES_OK;
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} else {
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// bad sector number
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return RES_ERROR;
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}
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}
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/* Definitions of physical drive number for each media */
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#define PD_FLASH (0)
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#define PD_SD (1)
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/*-----------------------------------------------------------------------*/
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/* Initialize a Drive */
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/*-----------------------------------------------------------------------*/
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DSTATUS disk_initialize (
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BYTE pdrv /* Physical drive nmuber (0..) */
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)
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{
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switch (pdrv) {
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case PD_FLASH :
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pd_flash_init();
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return 0;
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}
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return STA_NOINIT;
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}
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/*-----------------------------------------------------------------------*/
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/* Get Disk Status */
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/*-----------------------------------------------------------------------*/
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DSTATUS disk_status (
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BYTE pdrv /* Physical drive nmuber (0..) */
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)
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{
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switch (pdrv) {
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case PD_FLASH :
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// flash is ready
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return 0;
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case PD_SD:
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return STA_NOINIT;
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}
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return STA_NOINIT;
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}
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/*-----------------------------------------------------------------------*/
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/* Read Sector(s) */
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/*-----------------------------------------------------------------------*/
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DRESULT disk_read (
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BYTE pdrv, /* Physical drive nmuber (0..) */
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BYTE *buff, /* Data buffer to store read data */
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DWORD sector, /* Sector address (LBA) */
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UINT count /* Number of sectors to read (1..128) */
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)
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{
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DRESULT res;
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switch (pdrv) {
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case PD_FLASH:
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for (int i = 0; i < count; i++) {
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if ((res = pd_flash_read_sector(buff + i * PD_FLASH_SECTOR_SIZE, sector + i)) != RES_OK) {
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return res;
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}
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}
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return RES_OK;
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}
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return RES_PARERR;
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}
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/*-----------------------------------------------------------------------*/
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/* Write Sector(s) */
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/*-----------------------------------------------------------------------*/
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#if _USE_WRITE
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DRESULT disk_write (
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BYTE pdrv, /* Physical drive nmuber (0..) */
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const BYTE *buff, /* Data to be written */
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DWORD sector, /* Sector address (LBA) */
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UINT count /* Number of sectors to write (1..128) */
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)
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{
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DRESULT res;
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switch (pdrv) {
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case PD_FLASH:
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for (int i = 0; i < count; i++) {
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if ((res = pd_flash_write_sector(buff + i * PD_FLASH_SECTOR_SIZE, sector + i)) != RES_OK) {
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return res;
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}
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}
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return RES_OK;
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}
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return RES_PARERR;
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}
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#endif
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/*-----------------------------------------------------------------------*/
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/* Miscellaneous Functions */
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/*-----------------------------------------------------------------------*/
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#if _USE_IOCTL
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DRESULT disk_ioctl (
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BYTE pdrv, /* Physical drive nmuber (0..) */
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BYTE cmd, /* Control code */
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void *buff /* Buffer to send/receive control data */
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)
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{
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switch (pdrv) {
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case PD_FLASH:
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switch (cmd) {
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case CTRL_SYNC:
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pd_flash_flush();
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return RES_OK;
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case GET_BLOCK_SIZE:
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*((DWORD*)buff) = 1; // block erase size in units of the sector size
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return RES_OK;
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}
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}
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return RES_PARERR;
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}
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#endif
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DWORD get_fattime (
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void
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)
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{
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int year = 2013;
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int month = 10;
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int day = 12;
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int hour = 21;
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int minute = 42;
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int second = 13;
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return ((year - 1980) << 25) | ((month) << 21) | ((day) << 16) | ((hour) << 11) | ((minute) << 5) | (second / 2);
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}
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@ -0,0 +1,89 @@
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/*-----------------------------------------------------------------------
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/ Low level disk interface modlue include file (C)ChaN, 2013
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/-----------------------------------------------------------------------*/
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#ifndef _DISKIO_DEFINED
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#define _DISKIO_DEFINED
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define _USE_WRITE 1 /* 1: Enable disk_write function */
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#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */
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#include "integer.h"
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/* Status of Disk Functions */
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typedef BYTE DSTATUS;
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/* Results of Disk Functions */
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typedef enum {
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RES_OK = 0, /* 0: Successful */
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RES_ERROR, /* 1: R/W Error */
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RES_WRPRT, /* 2: Write Protected */
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RES_NOTRDY, /* 3: Not Ready */
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RES_PARERR /* 4: Invalid Parameter */
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} DRESULT;
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/*---------------------------------------*/
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/* Prototypes for disk control functions */
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DSTATUS disk_initialize (BYTE pdrv);
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DSTATUS disk_status (BYTE pdrv);
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DRESULT disk_read (BYTE pdrv, BYTE*buff, DWORD sector, UINT count);
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DRESULT disk_write (BYTE pdrv, const BYTE* buff, DWORD sector, UINT count);
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DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
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DWORD get_fattime (void);
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/* Disk Status Bits (DSTATUS) */
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#define STA_NOINIT 0x01 /* Drive not initialized */
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#define STA_NODISK 0x02 /* No medium in the drive */
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#define STA_PROTECT 0x04 /* Write protected */
|
||||
|
||||
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||||
/* Command code for disk_ioctrl fucntion */
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/* Generic command (used by FatFs) */
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#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
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#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
|
||||
#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
|
||||
#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
|
||||
#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */
|
||||
|
||||
/* Generic command (not used by FatFs) */
|
||||
#define CTRL_POWER 5 /* Get/Set power status */
|
||||
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
|
||||
#define CTRL_EJECT 7 /* Eject media */
|
||||
#define CTRL_FORMAT 8 /* Create physical format on the media */
|
||||
|
||||
/* MMC/SDC specific ioctl command */
|
||||
#define MMC_GET_TYPE 10 /* Get card type */
|
||||
#define MMC_GET_CSD 11 /* Get CSD */
|
||||
#define MMC_GET_CID 12 /* Get CID */
|
||||
#define MMC_GET_OCR 13 /* Get OCR */
|
||||
#define MMC_GET_SDSTAT 14 /* Get SD status */
|
||||
|
||||
/* ATA/CF specific ioctl command */
|
||||
#define ATA_GET_REV 20 /* Get F/W revision */
|
||||
#define ATA_GET_MODEL 21 /* Get model name */
|
||||
#define ATA_GET_SN 22 /* Get serial number */
|
||||
|
||||
|
||||
/* MMC card type flags (MMC_GET_TYPE) */
|
||||
#define CT_MMC 0x01 /* MMC ver 3 */
|
||||
#define CT_SD1 0x02 /* SD ver 1 */
|
||||
#define CT_SD2 0x04 /* SD ver 2 */
|
||||
#define CT_SDC (CT_SD1|CT_SD2) /* SD */
|
||||
#define CT_BLOCK 0x08 /* Block addressing */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,342 @@
|
|||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs - FAT file system module include file R0.10 (C)ChaN, 2013
|
||||
/----------------------------------------------------------------------------/
|
||||
/ FatFs module is a generic FAT file system module for small embedded systems.
|
||||
/ This is a free software that opened for education, research and commercial
|
||||
/ developments under license policy of following terms.
|
||||
/
|
||||
/ Copyright (C) 2013, ChaN, all right reserved.
|
||||
/
|
||||
/ * The FatFs module is a free software and there is NO WARRANTY.
|
||||
/ * No restriction on use. You can use, modify and redistribute it for
|
||||
/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
|
||||
/ * Redistributions of source code must retain the above copyright notice.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _FATFS
|
||||
#define _FATFS 80960 /* Revision ID */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "integer.h" /* Basic integer types */
|
||||
#include "ffconf.h" /* FatFs configuration options */
|
||||
|
||||
#if _FATFS != _FFCONF
|
||||
#error Wrong configuration file (ffconf.h).
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Definitions of volume management */
|
||||
|
||||
#if _MULTI_PARTITION /* Multiple partition configuration */
|
||||
typedef struct {
|
||||
BYTE pd; /* Physical drive number */
|
||||
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
|
||||
} PARTITION;
|
||||
extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
|
||||
#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */
|
||||
#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */
|
||||
|
||||
#else /* Single partition configuration */
|
||||
#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */
|
||||
#define LD2PT(vol) 0 /* Find first valid partition or in SFD */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Type of path name strings on FatFs API */
|
||||
|
||||
#if _LFN_UNICODE /* Unicode string */
|
||||
#if !_USE_LFN
|
||||
#error _LFN_UNICODE must be 0 in non-LFN cfg.
|
||||
#endif
|
||||
#ifndef _INC_TCHAR
|
||||
typedef WCHAR TCHAR;
|
||||
#define _T(x) L ## x
|
||||
#define _TEXT(x) L ## x
|
||||
#endif
|
||||
|
||||
#else /* ANSI/OEM string */
|
||||
#ifndef _INC_TCHAR
|
||||
typedef char TCHAR;
|
||||
#define _T(x) x
|
||||
#define _TEXT(x) x
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* File system object structure (FATFS) */
|
||||
|
||||
typedef struct {
|
||||
BYTE fs_type; /* FAT sub-type (0:Not mounted) */
|
||||
BYTE drv; /* Physical drive number */
|
||||
BYTE csize; /* Sectors per cluster (1,2,4...128) */
|
||||
BYTE n_fats; /* Number of FAT copies (1 or 2) */
|
||||
BYTE wflag; /* win[] flag (b0:dirty) */
|
||||
BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
|
||||
WORD id; /* File system mount ID */
|
||||
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
|
||||
#if _MAX_SS != 512
|
||||
WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */
|
||||
#endif
|
||||
#if _FS_REENTRANT
|
||||
_SYNC_t sobj; /* Identifier of sync object */
|
||||
#endif
|
||||
#if !_FS_READONLY
|
||||
DWORD last_clust; /* Last allocated cluster */
|
||||
DWORD free_clust; /* Number of free clusters */
|
||||
#endif
|
||||
#if _FS_RPATH
|
||||
DWORD cdir; /* Current directory start cluster (0:root) */
|
||||
#endif
|
||||
DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */
|
||||
DWORD fsize; /* Sectors per FAT */
|
||||
DWORD volbase; /* Volume start sector */
|
||||
DWORD fatbase; /* FAT start sector */
|
||||
DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */
|
||||
DWORD database; /* Data start sector */
|
||||
DWORD winsect; /* Current sector appearing in the win[] */
|
||||
BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
|
||||
} FATFS;
|
||||
|
||||
|
||||
|
||||
/* File object structure (FIL) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the related file system object (**do not change order**) */
|
||||
WORD id; /* Owner file system mount ID (**do not change order**) */
|
||||
BYTE flag; /* File status flags */
|
||||
BYTE err; /* Abort flag (error code) */
|
||||
DWORD fptr; /* File read/write pointer (Zeroed on file open) */
|
||||
DWORD fsize; /* File size */
|
||||
DWORD sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */
|
||||
DWORD clust; /* Current cluster of fpter */
|
||||
DWORD dsect; /* Current data sector of fpter */
|
||||
#if !_FS_READONLY
|
||||
DWORD dir_sect; /* Sector containing the directory entry */
|
||||
BYTE* dir_ptr; /* Pointer to the directory entry in the window */
|
||||
#endif
|
||||
#if _USE_FASTSEEK
|
||||
DWORD* cltbl; /* Pointer to the cluster link map table (Nulled on file open) */
|
||||
#endif
|
||||
#if _FS_LOCK
|
||||
UINT lockid; /* File lock ID (index of file semaphore table Files[]) */
|
||||
#endif
|
||||
#if !_FS_TINY
|
||||
BYTE buf[_MAX_SS]; /* File data read/write buffer */
|
||||
#endif
|
||||
} FIL;
|
||||
|
||||
|
||||
|
||||
/* Directory object structure (DIR) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the owner file system object (**do not change order**) */
|
||||
WORD id; /* Owner file system mount ID (**do not change order**) */
|
||||
WORD index; /* Current read/write index number */
|
||||
DWORD sclust; /* Table start cluster (0:Root dir) */
|
||||
DWORD clust; /* Current cluster */
|
||||
DWORD sect; /* Current sector */
|
||||
BYTE* dir; /* Pointer to the current SFN entry in the win[] */
|
||||
BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
|
||||
#if _FS_LOCK
|
||||
UINT lockid; /* File lock ID (index of file semaphore table Files[]) */
|
||||
#endif
|
||||
#if _USE_LFN
|
||||
WCHAR* lfn; /* Pointer to the LFN working buffer */
|
||||
WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
|
||||
#endif
|
||||
} DIR;
|
||||
|
||||
|
||||
|
||||
/* File status structure (FILINFO) */
|
||||
|
||||
typedef struct {
|
||||
DWORD fsize; /* File size */
|
||||
WORD fdate; /* Last modified date */
|
||||
WORD ftime; /* Last modified time */
|
||||
BYTE fattrib; /* Attribute */
|
||||
TCHAR fname[13]; /* Short file name (8.3 format) */
|
||||
#if _USE_LFN
|
||||
TCHAR* lfname; /* Pointer to the LFN buffer */
|
||||
UINT lfsize; /* Size of LFN buffer in TCHAR */
|
||||
#endif
|
||||
} FILINFO;
|
||||
|
||||
|
||||
|
||||
/* File function return code (FRESULT) */
|
||||
|
||||
typedef enum {
|
||||
FR_OK = 0, /* (0) Succeeded */
|
||||
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
|
||||
FR_INT_ERR, /* (2) Assertion failed */
|
||||
FR_NOT_READY, /* (3) The physical drive cannot work */
|
||||
FR_NO_FILE, /* (4) Could not find the file */
|
||||
FR_NO_PATH, /* (5) Could not find the path */
|
||||
FR_INVALID_NAME, /* (6) The path name format is invalid */
|
||||
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
|
||||
FR_EXIST, /* (8) Access denied due to prohibited access */
|
||||
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
|
||||
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
|
||||
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
|
||||
FR_NOT_ENABLED, /* (12) The volume has no work area */
|
||||
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
|
||||
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
|
||||
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
|
||||
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
|
||||
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
|
||||
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */
|
||||
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
|
||||
} FRESULT;
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* FatFs module application interface */
|
||||
|
||||
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
|
||||
FRESULT f_close (FIL* fp); /* Close an open file object */
|
||||
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from a file */
|
||||
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to a file */
|
||||
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
|
||||
FRESULT f_lseek (FIL* fp, DWORD ofs); /* Move file pointer of a file object */
|
||||
FRESULT f_truncate (FIL* fp); /* Truncate file */
|
||||
FRESULT f_sync (FIL* fp); /* Flush cached data of a writing file */
|
||||
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
|
||||
FRESULT f_closedir (DIR* dp); /* Close an open directory */
|
||||
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
|
||||
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
|
||||
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
|
||||
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
|
||||
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
|
||||
FRESULT f_chmod (const TCHAR* path, BYTE value, BYTE mask); /* Change attribute of the file/dir */
|
||||
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change times-tamp of the file/dir */
|
||||
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
|
||||
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
|
||||
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
|
||||
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
|
||||
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* sn); /* Get volume label */
|
||||
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
|
||||
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
|
||||
FRESULT f_mkfs (const TCHAR* path, BYTE sfd, UINT au); /* Create a file system on the volume */
|
||||
FRESULT f_fdisk (BYTE pdrv, const DWORD szt[], void* work); /* Divide a physical drive into some partitions */
|
||||
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
|
||||
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
|
||||
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
|
||||
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
|
||||
|
||||
#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
|
||||
#define f_error(fp) ((fp)->err)
|
||||
#define f_tell(fp) ((fp)->fptr)
|
||||
#define f_size(fp) ((fp)->fsize)
|
||||
|
||||
#ifndef EOF
|
||||
#define EOF (-1)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Additional user defined functions */
|
||||
|
||||
/* RTC function */
|
||||
#if !_FS_READONLY
|
||||
DWORD get_fattime (void);
|
||||
#endif
|
||||
|
||||
/* Unicode support functions */
|
||||
#if _USE_LFN /* Unicode - OEM code conversion */
|
||||
WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */
|
||||
WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */
|
||||
#if _USE_LFN == 3 /* Memory functions */
|
||||
void* ff_memalloc (UINT msize); /* Allocate memory block */
|
||||
void ff_memfree (void* mblock); /* Free memory block */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Sync functions */
|
||||
#if _FS_REENTRANT
|
||||
int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */
|
||||
int ff_req_grant (_SYNC_t sobj); /* Lock sync object */
|
||||
void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */
|
||||
int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Flags and offset address */
|
||||
|
||||
|
||||
/* File access control and file status flags (FIL.flag) */
|
||||
|
||||
#define FA_READ 0x01
|
||||
#define FA_OPEN_EXISTING 0x00
|
||||
|
||||
#if !_FS_READONLY
|
||||
#define FA_WRITE 0x02
|
||||
#define FA_CREATE_NEW 0x04
|
||||
#define FA_CREATE_ALWAYS 0x08
|
||||
#define FA_OPEN_ALWAYS 0x10
|
||||
#define FA__WRITTEN 0x20
|
||||
#define FA__DIRTY 0x40
|
||||
#endif
|
||||
|
||||
|
||||
/* FAT sub type (FATFS.fs_type) */
|
||||
|
||||
#define FS_FAT12 1
|
||||
#define FS_FAT16 2
|
||||
#define FS_FAT32 3
|
||||
|
||||
|
||||
/* File attribute bits for directory entry */
|
||||
|
||||
#define AM_RDO 0x01 /* Read only */
|
||||
#define AM_HID 0x02 /* Hidden */
|
||||
#define AM_SYS 0x04 /* System */
|
||||
#define AM_VOL 0x08 /* Volume label */
|
||||
#define AM_LFN 0x0F /* LFN entry */
|
||||
#define AM_DIR 0x10 /* Directory */
|
||||
#define AM_ARC 0x20 /* Archive */
|
||||
#define AM_MASK 0x3F /* Mask of defined bits */
|
||||
|
||||
|
||||
/* Fast seek feature */
|
||||
#define CREATE_LINKMAP 0xFFFFFFFF
|
||||
|
||||
|
||||
|
||||
/*--------------------------------*/
|
||||
/* Multi-byte word access macros */
|
||||
|
||||
#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
|
||||
#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr))
|
||||
#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr))
|
||||
#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val)
|
||||
#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
|
||||
#else /* Use byte-by-byte access to the FAT structure */
|
||||
#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
|
||||
#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
|
||||
#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
|
||||
#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FATFS */
|
||||
|
|
@ -0,0 +1,212 @@
|
|||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs - FAT file system module configuration file R0.10 (C)ChaN, 2013
|
||||
/----------------------------------------------------------------------------/
|
||||
/
|
||||
/ CAUTION! Do not forget to make clean the project after any changes to
|
||||
/ the configuration options.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
#ifndef _FFCONF
|
||||
#define _FFCONF 80960 /* Revision ID */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Functions and Buffer Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _FS_TINY 1 /* 0:Normal or 1:Tiny */
|
||||
/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
|
||||
/ object instead of the sector buffer in the individual file object for file
|
||||
/ data transfer. This reduces memory consumption 512 bytes each file object. */
|
||||
|
||||
|
||||
#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
|
||||
/* Setting _FS_READONLY to 1 defines read only configuration. This removes
|
||||
/ writing functions, f_write(), f_sync(), f_unlink(), f_mkdir(), f_chmod(),
|
||||
/ f_rename(), f_truncate() and useless f_getfree(). */
|
||||
|
||||
|
||||
#define _FS_MINIMIZE 0 /* 0 to 3 */
|
||||
/* The _FS_MINIMIZE option defines minimization level to remove API functions.
|
||||
/
|
||||
/ 0: All basic functions are enabled.
|
||||
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(),
|
||||
/ f_truncate() and f_rename() function are removed.
|
||||
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
|
||||
/ 3: f_lseek() function is removed in addition to 2. */
|
||||
|
||||
|
||||
#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */
|
||||
/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
|
||||
|
||||
|
||||
#define _USE_MKFS 1 /* 0:Disable or 1:Enable */
|
||||
/* To enable f_mkfs() function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
|
||||
|
||||
|
||||
#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
|
||||
|
||||
|
||||
#define _USE_LABEL 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable volume label functions, set _USE_LAVEL to 1 */
|
||||
|
||||
|
||||
#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable f_forward() function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Locale and Namespace Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _CODE_PAGE 1
|
||||
/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
|
||||
/ Incorrect setting of the code page can cause a file open failure.
|
||||
/
|
||||
/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
|
||||
/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
|
||||
/ 949 - Korean (DBCS, OEM, Windows)
|
||||
/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
|
||||
/ 1250 - Central Europe (Windows)
|
||||
/ 1251 - Cyrillic (Windows)
|
||||
/ 1252 - Latin 1 (Windows)
|
||||
/ 1253 - Greek (Windows)
|
||||
/ 1254 - Turkish (Windows)
|
||||
/ 1255 - Hebrew (Windows)
|
||||
/ 1256 - Arabic (Windows)
|
||||
/ 1257 - Baltic (Windows)
|
||||
/ 1258 - Vietnam (OEM, Windows)
|
||||
/ 437 - U.S. (OEM)
|
||||
/ 720 - Arabic (OEM)
|
||||
/ 737 - Greek (OEM)
|
||||
/ 775 - Baltic (OEM)
|
||||
/ 850 - Multilingual Latin 1 (OEM)
|
||||
/ 858 - Multilingual Latin 1 + Euro (OEM)
|
||||
/ 852 - Latin 2 (OEM)
|
||||
/ 855 - Cyrillic (OEM)
|
||||
/ 866 - Russian (OEM)
|
||||
/ 857 - Turkish (OEM)
|
||||
/ 862 - Hebrew (OEM)
|
||||
/ 874 - Thai (OEM, Windows)
|
||||
/ 1 - ASCII (Valid for only non-LFN cfg.)
|
||||
*/
|
||||
|
||||
|
||||
#define _USE_LFN 0 /* 0 to 3 */
|
||||
#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
|
||||
/* The _USE_LFN option switches the LFN feature.
|
||||
/
|
||||
/ 0: Disable LFN feature. _MAX_LFN has no effect.
|
||||
/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
|
||||
/ 2: Enable LFN with dynamic working buffer on the STACK.
|
||||
/ 3: Enable LFN with dynamic working buffer on the HEAP.
|
||||
/
|
||||
/ To enable LFN feature, Unicode handling functions ff_convert() and ff_wtoupper()
|
||||
/ function must be added to the project.
|
||||
/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When use stack for the
|
||||
/ working buffer, take care on stack overflow. When use heap memory for the working
|
||||
/ buffer, memory management functions, ff_memalloc() and ff_memfree(), must be added
|
||||
/ to the project. */
|
||||
|
||||
|
||||
#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
|
||||
/* To switch the character encoding on the FatFs API to Unicode, enable LFN feature
|
||||
/ and set _LFN_UNICODE to 1. */
|
||||
|
||||
|
||||
#define _STRF_ENCODE 3 /* 0:ANSI/OEM, 1:UTF-16LE, 2:UTF-16BE, 3:UTF-8 */
|
||||
/* When Unicode API is enabled, character encoding on the all FatFs API is switched
|
||||
/ to Unicode. This option selects the character encoding on the file to be read/written
|
||||
/ via string functions, f_gets(), f_putc(), f_puts and f_printf().
|
||||
/ This option has no effect when _LFN_UNICODE is 0. */
|
||||
|
||||
|
||||
#define _FS_RPATH 0 /* 0 to 2 */
|
||||
/* The _FS_RPATH option configures relative path feature.
|
||||
/
|
||||
/ 0: Disable relative path feature and remove related functions.
|
||||
/ 1: Enable relative path. f_chdrive() and f_chdir() function are available.
|
||||
/ 2: f_getcwd() function is available in addition to 1.
|
||||
/
|
||||
/ Note that output of the f_readdir() fnction is affected by this option. */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Drive/Volume Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _VOLUMES 1
|
||||
/* Number of volumes (logical drives) to be used. */
|
||||
|
||||
|
||||
#define _MULTI_PARTITION 1 /* 0:Single partition, 1:Enable multiple partition */
|
||||
/* When set to 0, each volume is bound to the same physical drive number and
|
||||
/ it can mount only first primaly partition. When it is set to 1, each volume
|
||||
/ is tied to the partitions listed in VolToPart[]. */
|
||||
|
||||
|
||||
#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
|
||||
/* Maximum sector size to be handled.
|
||||
/ Always set 512 for memory card and hard disk but a larger value may be
|
||||
/ required for on-board flash memory, floppy disk and optical disk.
|
||||
/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size
|
||||
/ and GET_SECTOR_SIZE command must be implemented to the disk_ioctl() function. */
|
||||
|
||||
|
||||
#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable sector erase feature, set _USE_ERASE to 1. Also CTRL_ERASE_SECTOR command
|
||||
/ should be added to the disk_ioctl() function. */
|
||||
|
||||
|
||||
#define _FS_NOFSINFO 0 /* 0 or 1 */
|
||||
/* If you need to know the correct free space on the FAT32 volume, set this
|
||||
/ option to 1 and f_getfree() function at first time after volume mount will
|
||||
/ force a full FAT scan.
|
||||
/
|
||||
/ 0: Load all informations in the FSINFO if available.
|
||||
/ 1: Do not trust free cluster count in the FSINFO.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ System Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _WORD_ACCESS 0 /* 0 or 1 */
|
||||
/* The _WORD_ACCESS option is an only platform dependent option. It defines
|
||||
/ which access method is used to the word data on the FAT volume.
|
||||
/
|
||||
/ 0: Byte-by-byte access. Always compatible with all platforms.
|
||||
/ 1: Word access. Do not choose this unless under both the following conditions.
|
||||
/
|
||||
/ * Byte order on the memory is little-endian.
|
||||
/ * Address miss-aligned word access is always allowed for all instructions.
|
||||
/
|
||||
/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance
|
||||
/ and reduce code size.
|
||||
*/
|
||||
|
||||
|
||||
/* A header file that defines sync object types on the O/S, such as
|
||||
/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
|
||||
|
||||
#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
|
||||
#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
|
||||
#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
|
||||
|
||||
/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs module.
|
||||
/
|
||||
/ 0: Disable re-entrancy. _SYNC_t and _FS_TIMEOUT have no effect.
|
||||
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
|
||||
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
|
||||
/ function must be added to the project. */
|
||||
|
||||
|
||||
#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
|
||||
/* To enable file lock control feature, set _FS_LOCK to 1 or greater.
|
||||
The value defines how many files can be opened simultaneously. */
|
||||
|
||||
|
||||
#endif /* _FFCONFIG */
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*-------------------------------------------*/
|
||||
/* Integer type definitions for FatFs module */
|
||||
/*-------------------------------------------*/
|
||||
|
||||
#ifndef _FF_INTEGER
|
||||
#define _FF_INTEGER
|
||||
|
||||
#ifdef _WIN32 /* FatFs development platform */
|
||||
|
||||
#include <windows.h>
|
||||
#include <tchar.h>
|
||||
|
||||
#else /* Embedded platform */
|
||||
|
||||
/* This type MUST be 8 bit */
|
||||
typedef unsigned char BYTE;
|
||||
|
||||
/* These types MUST be 16 bit */
|
||||
typedef short SHORT;
|
||||
typedef unsigned short WORD;
|
||||
typedef unsigned short WCHAR;
|
||||
|
||||
/* These types MUST be 16 bit or 32 bit */
|
||||
typedef int INT;
|
||||
typedef unsigned int UINT;
|
||||
|
||||
/* These types MUST be 32 bit */
|
||||
typedef long LONG;
|
||||
typedef unsigned long DWORD;
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
#include <stm32f4xx.h>
|
||||
#include <stm32f4xx_flash.h>
|
||||
|
||||
/* Base address of the Flash sectors */
|
||||
#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */
|
||||
#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */
|
||||
|
||||
static uint32_t GetSector(uint32_t Address);
|
||||
|
||||
void flash_write(uint32_t flash_dest, const uint32_t *src, uint32_t num_word32) {
|
||||
// unlock
|
||||
FLASH_Unlock();
|
||||
|
||||
// Clear pending flags (if any)
|
||||
FLASH_ClearFlag(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |
|
||||
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR|FLASH_FLAG_PGSERR);
|
||||
|
||||
// Device voltage range supposed to be [2.7V to 3.6V], the operation will be done by word
|
||||
if (FLASH_EraseSector(GetSector(flash_dest), VoltageRange_3) != FLASH_COMPLETE) {
|
||||
/* Error occurred while sector erase.
|
||||
User can add here some code to deal with this error */
|
||||
return;
|
||||
}
|
||||
|
||||
/* Program the user Flash area word by word ********************************/
|
||||
|
||||
for (int i = 0; i < num_word32; i++) {
|
||||
if (FLASH_ProgramWord(flash_dest, *src) == FLASH_COMPLETE)
|
||||
{
|
||||
flash_dest += 4;
|
||||
src += 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Error occurred while writing data in Flash memory.
|
||||
User can add here some code to deal with this error */
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// lock
|
||||
FLASH_Lock();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the sector of a given address
|
||||
* @param None
|
||||
* @retval The sector of a given address
|
||||
*/
|
||||
static uint32_t GetSector(uint32_t Address)
|
||||
{
|
||||
uint32_t sector = 0;
|
||||
|
||||
if((Address < ADDR_FLASH_SECTOR_1) && (Address >= ADDR_FLASH_SECTOR_0))
|
||||
{
|
||||
sector = FLASH_Sector_0;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_2) && (Address >= ADDR_FLASH_SECTOR_1))
|
||||
{
|
||||
sector = FLASH_Sector_1;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_3) && (Address >= ADDR_FLASH_SECTOR_2))
|
||||
{
|
||||
sector = FLASH_Sector_2;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_4) && (Address >= ADDR_FLASH_SECTOR_3))
|
||||
{
|
||||
sector = FLASH_Sector_3;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_5) && (Address >= ADDR_FLASH_SECTOR_4))
|
||||
{
|
||||
sector = FLASH_Sector_4;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_6) && (Address >= ADDR_FLASH_SECTOR_5))
|
||||
{
|
||||
sector = FLASH_Sector_5;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_7) && (Address >= ADDR_FLASH_SECTOR_6))
|
||||
{
|
||||
sector = FLASH_Sector_6;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_8) && (Address >= ADDR_FLASH_SECTOR_7))
|
||||
{
|
||||
sector = FLASH_Sector_7;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_9) && (Address >= ADDR_FLASH_SECTOR_8))
|
||||
{
|
||||
sector = FLASH_Sector_8;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_10) && (Address >= ADDR_FLASH_SECTOR_9))
|
||||
{
|
||||
sector = FLASH_Sector_9;
|
||||
}
|
||||
else if((Address < ADDR_FLASH_SECTOR_11) && (Address >= ADDR_FLASH_SECTOR_10))
|
||||
{
|
||||
sector = FLASH_Sector_10;
|
||||
}
|
||||
return sector;
|
||||
}
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
const uint8_t font_petme128_8x8[] = {
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // 32=
|
||||
0x00,0x00,0x00,0x4f,0x4f,0x00,0x00,0x00, // 33=!
|
||||
0x00,0x07,0x07,0x00,0x00,0x07,0x07,0x00, // 34="
|
||||
0x14,0x7f,0x7f,0x14,0x14,0x7f,0x7f,0x14, // 35=#
|
||||
0x00,0x24,0x2e,0x6b,0x6b,0x3a,0x12,0x00, // 36=$
|
||||
0x00,0x63,0x33,0x18,0x0c,0x66,0x63,0x00, // 37=%
|
||||
0x00,0x32,0x7f,0x4d,0x4d,0x77,0x72,0x50, // 38=&
|
||||
0x00,0x00,0x00,0x04,0x06,0x03,0x01,0x00, // 39='
|
||||
0x00,0x00,0x1c,0x3e,0x63,0x41,0x00,0x00, // 40=(
|
||||
0x00,0x00,0x41,0x63,0x3e,0x1c,0x00,0x00, // 41=)
|
||||
0x08,0x2a,0x3e,0x1c,0x1c,0x3e,0x2a,0x08, // 42=*
|
||||
0x00,0x08,0x08,0x3e,0x3e,0x08,0x08,0x00, // 43=+
|
||||
0x00,0x00,0x80,0xe0,0x60,0x00,0x00,0x00, // 44=,
|
||||
0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x00, // 45=-
|
||||
0x00,0x00,0x00,0x60,0x60,0x00,0x00,0x00, // 46=.
|
||||
0x00,0x40,0x60,0x30,0x18,0x0c,0x06,0x02, // 47=/
|
||||
0x00,0x3e,0x7f,0x49,0x45,0x7f,0x3e,0x00, // 48=0
|
||||
0x00,0x40,0x44,0x7f,0x7f,0x40,0x40,0x00, // 49=1
|
||||
0x00,0x62,0x73,0x51,0x49,0x4f,0x46,0x00, // 50=2
|
||||
0x00,0x22,0x63,0x49,0x49,0x7f,0x36,0x00, // 51=3
|
||||
0x00,0x18,0x18,0x14,0x16,0x7f,0x7f,0x10, // 52=4
|
||||
0x00,0x27,0x67,0x45,0x45,0x7d,0x39,0x00, // 53=5
|
||||
0x00,0x3e,0x7f,0x49,0x49,0x7b,0x32,0x00, // 54=6
|
||||
0x00,0x03,0x03,0x79,0x7d,0x07,0x03,0x00, // 55=7
|
||||
0x00,0x36,0x7f,0x49,0x49,0x7f,0x36,0x00, // 56=8
|
||||
0x00,0x26,0x6f,0x49,0x49,0x7f,0x3e,0x00, // 57=9
|
||||
0x00,0x00,0x00,0x24,0x24,0x00,0x00,0x00, // 58=:
|
||||
0x00,0x00,0x80,0xe4,0x64,0x00,0x00,0x00, // 59=;
|
||||
0x00,0x08,0x1c,0x36,0x63,0x41,0x41,0x00, // 60=<
|
||||
0x00,0x14,0x14,0x14,0x14,0x14,0x14,0x00, // 61==
|
||||
0x00,0x41,0x41,0x63,0x36,0x1c,0x08,0x00, // 62=>
|
||||
0x00,0x02,0x03,0x51,0x59,0x0f,0x06,0x00, // 63=?
|
||||
0x00,0x3e,0x7f,0x41,0x4d,0x4f,0x2e,0x00, // 64=@
|
||||
0x00,0x7c,0x7e,0x0b,0x0b,0x7e,0x7c,0x00, // 65=A
|
||||
0x00,0x7f,0x7f,0x49,0x49,0x7f,0x36,0x00, // 66=B
|
||||
0x00,0x3e,0x7f,0x41,0x41,0x63,0x22,0x00, // 67=C
|
||||
0x00,0x7f,0x7f,0x41,0x63,0x3e,0x1c,0x00, // 68=D
|
||||
0x00,0x7f,0x7f,0x49,0x49,0x41,0x41,0x00, // 69=E
|
||||
0x00,0x7f,0x7f,0x09,0x09,0x01,0x01,0x00, // 70=F
|
||||
0x00,0x3e,0x7f,0x41,0x49,0x7b,0x3a,0x00, // 71=G
|
||||
0x00,0x7f,0x7f,0x08,0x08,0x7f,0x7f,0x00, // 72=H
|
||||
0x00,0x00,0x41,0x7f,0x7f,0x41,0x00,0x00, // 73=I
|
||||
0x00,0x20,0x60,0x41,0x7f,0x3f,0x01,0x00, // 74=J
|
||||
0x00,0x7f,0x7f,0x1c,0x36,0x63,0x41,0x00, // 75=K
|
||||
0x00,0x7f,0x7f,0x40,0x40,0x40,0x40,0x00, // 76=L
|
||||
0x00,0x7f,0x7f,0x06,0x0c,0x06,0x7f,0x7f, // 77=M
|
||||
0x00,0x7f,0x7f,0x0e,0x1c,0x7f,0x7f,0x00, // 78=N
|
||||
0x00,0x3e,0x7f,0x41,0x41,0x7f,0x3e,0x00, // 79=O
|
||||
0x00,0x7f,0x7f,0x09,0x09,0x0f,0x06,0x00, // 80=P
|
||||
0x00,0x1e,0x3f,0x21,0x61,0x7f,0x5e,0x00, // 81=Q
|
||||
0x00,0x7f,0x7f,0x19,0x39,0x6f,0x46,0x00, // 82=R
|
||||
0x00,0x26,0x6f,0x49,0x49,0x7b,0x32,0x00, // 83=S
|
||||
0x00,0x01,0x01,0x7f,0x7f,0x01,0x01,0x00, // 84=T
|
||||
0x00,0x3f,0x7f,0x40,0x40,0x7f,0x3f,0x00, // 85=U
|
||||
0x00,0x1f,0x3f,0x60,0x60,0x3f,0x1f,0x00, // 86=V
|
||||
0x00,0x7f,0x7f,0x30,0x18,0x30,0x7f,0x7f, // 87=W
|
||||
0x00,0x63,0x77,0x1c,0x1c,0x77,0x63,0x00, // 88=X
|
||||
0x00,0x07,0x0f,0x78,0x78,0x0f,0x07,0x00, // 89=Y
|
||||
0x00,0x61,0x71,0x59,0x4d,0x47,0x43,0x00, // 90=Z
|
||||
0x00,0x00,0x7f,0x7f,0x41,0x41,0x00,0x00, // 91=[
|
||||
0x00,0x02,0x06,0x0c,0x18,0x30,0x60,0x40, // 92='\'
|
||||
0x00,0x00,0x41,0x41,0x7f,0x7f,0x00,0x00, // 93=]
|
||||
0x00,0x08,0x0c,0x06,0x06,0x0c,0x08,0x00, // 94=^
|
||||
0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0,0xc0, // 95=_
|
||||
0x00,0x00,0x01,0x03,0x06,0x04,0x00,0x00, // 96=`
|
||||
0x00,0x20,0x74,0x54,0x54,0x7c,0x78,0x00, // 97=a
|
||||
0x00,0x7f,0x7f,0x44,0x44,0x7c,0x38,0x00, // 98=b
|
||||
0x00,0x38,0x7c,0x44,0x44,0x6c,0x28,0x00, // 99=c
|
||||
0x00,0x38,0x7c,0x44,0x44,0x7f,0x7f,0x00, // 100=d
|
||||
0x00,0x38,0x7c,0x54,0x54,0x5c,0x58,0x00, // 101=e
|
||||
0x00,0x08,0x7e,0x7f,0x09,0x03,0x02,0x00, // 102=f
|
||||
0x00,0x98,0xbc,0xa4,0xa4,0xfc,0x7c,0x00, // 103=g
|
||||
0x00,0x7f,0x7f,0x04,0x04,0x7c,0x78,0x00, // 104=h
|
||||
0x00,0x00,0x00,0x7d,0x7d,0x00,0x00,0x00, // 105=i
|
||||
0x00,0x40,0xc0,0x80,0x80,0xfd,0x7d,0x00, // 106=j
|
||||
0x00,0x7f,0x7f,0x30,0x38,0x6c,0x44,0x00, // 107=k
|
||||
0x00,0x00,0x41,0x7f,0x7f,0x40,0x00,0x00, // 108=l
|
||||
0x00,0x7c,0x7c,0x18,0x30,0x18,0x7c,0x7c, // 109=m
|
||||
0x00,0x7c,0x7c,0x04,0x04,0x7c,0x78,0x00, // 110=n
|
||||
0x00,0x38,0x7c,0x44,0x44,0x7c,0x38,0x00, // 111=o
|
||||
0x00,0xfc,0xfc,0x24,0x24,0x3c,0x18,0x00, // 112=p
|
||||
0x00,0x18,0x3c,0x24,0x24,0xfc,0xfc,0x00, // 113=q
|
||||
0x00,0x7c,0x7c,0x04,0x04,0x0c,0x08,0x00, // 114=r
|
||||
0x00,0x48,0x5c,0x54,0x54,0x74,0x20,0x00, // 115=s
|
||||
0x04,0x04,0x3f,0x7f,0x44,0x64,0x20,0x00, // 116=t
|
||||
0x00,0x3c,0x7c,0x40,0x40,0x7c,0x3c,0x00, // 117=u
|
||||
0x00,0x1c,0x3c,0x60,0x60,0x3c,0x1c,0x00, // 118=v
|
||||
0x00,0x1c,0x7c,0x30,0x18,0x30,0x7c,0x1c, // 119=w
|
||||
0x00,0x44,0x6c,0x38,0x38,0x6c,0x44,0x00, // 120=x
|
||||
0x00,0x9c,0xbc,0xa0,0xa0,0xfc,0x7c,0x00, // 121=y
|
||||
0x00,0x44,0x64,0x74,0x5c,0x4c,0x44,0x00, // 122=z
|
||||
0x00,0x08,0x08,0x3e,0x77,0x41,0x41,0x00, // 123={
|
||||
0x00,0x00,0x00,0xff,0xff,0x00,0x00,0x00, // 124=|
|
||||
0x00,0x41,0x41,0x77,0x3e,0x08,0x08,0x00, // 125=}
|
||||
0x00,0x02,0x03,0x01,0x03,0x02,0x03,0x01, // 126=~
|
||||
0xaa,0x55,0xaa,0x55,0xaa,0x55,0xaa,0x55, // 127
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,649 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm4_simd.h
|
||||
* @brief CMSIS Cortex-M4 SIMD Header File
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM4_SIMD_H
|
||||
#define __CORE_CM4_SIMD_H
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SMLALD(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
#define __SMLALDX(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SMLSLD(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
#define __SMLSLDX(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
|
||||
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
|
||||
(uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
|
||||
})
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
|
||||
/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
/* not yet supported */
|
||||
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CORE_CM4_SIMD_H */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,616 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xff);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -0,0 +1,618 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
|
||||
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
|
||||
return(op1);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint16_t result;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,94 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 18-January-2013
|
||||
* @brief Library configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_CONF_H
|
||||
#define __STM32F4xx_CONF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/* Uncomment the line below to enable peripheral header file inclusion */
|
||||
//#include "stm32f4xx_adc.h"
|
||||
//#include "stm32f4xx_can.h"
|
||||
//#include "stm32f4xx_crc.h"
|
||||
//#include "stm32f4xx_cryp.h"
|
||||
//#include "stm32f4xx_dac.h"
|
||||
//#include "stm32f4xx_dbgmcu.h"
|
||||
//#include "stm32f4xx_dcmi.h"
|
||||
//#include "stm32f4xx_dma.h"
|
||||
//#include "stm32f4xx_exti.h"
|
||||
//#include "stm32f4xx_flash.h"
|
||||
//#include "stm32f4xx_fsmc.h"
|
||||
//#include "stm32f4xx_hash.h"
|
||||
//#include "stm32f4xx_gpio.h"
|
||||
//#include "stm32f4xx_i2c.h"
|
||||
//#include "stm32f4xx_iwdg.h"
|
||||
//#include "stm32f4xx_pwr.h"
|
||||
//#include "stm32f4xx_rcc.h"
|
||||
//#include "stm32f4xx_rng.h"
|
||||
//#include "stm32f4xx_rtc.h"
|
||||
//#include "stm32f4xx_sdio.h"
|
||||
//#include "stm32f4xx_spi.h"
|
||||
//#include "stm32f4xx_syscfg.h"
|
||||
//#include "stm32f4xx_tim.h"
|
||||
//#include "stm32f4xx_usart.h"
|
||||
//#include "stm32f4xx_wwdg.h"
|
||||
//#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* If an external clock source is used, then the value of the following define
|
||||
should be set to the value of the external clock source, else, if no external
|
||||
clock is used, keep this define commented */
|
||||
/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
|
||||
|
||||
|
||||
/* Uncomment the line below to expanse the "assert_param" macro in the
|
||||
Standard Peripheral Library drivers code */
|
||||
/* #define USE_FULL_ASSERT 1 */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t* file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#endif /* __STM32F4xx_CONF_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,609 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_DMA_H
|
||||
#define __STM32F4xx_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_channel */
|
||||
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
|
||||
|
||||
uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx.
|
||||
This memory is the default memory used when double buffer mode is
|
||||
not enabled. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode
|
||||
@note The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Stream */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
|
||||
This parameter can be a value of @ref DMA_fifo_direct_mode
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected Stream */
|
||||
|
||||
uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_fifo_threshold_level */
|
||||
|
||||
uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptable
|
||||
transaction. This parameter can be a value of @ref DMA_memory_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
|
||||
uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptable
|
||||
transaction. This parameter can be a value of @ref DMA_peripheral_burst
|
||||
@note The burst mode is possible only if the address Increment mode is enabled. */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
|
||||
((PERIPH) == DMA1_Stream1) || \
|
||||
((PERIPH) == DMA1_Stream2) || \
|
||||
((PERIPH) == DMA1_Stream3) || \
|
||||
((PERIPH) == DMA1_Stream4) || \
|
||||
((PERIPH) == DMA1_Stream5) || \
|
||||
((PERIPH) == DMA1_Stream6) || \
|
||||
((PERIPH) == DMA1_Stream7) || \
|
||||
((PERIPH) == DMA2_Stream0) || \
|
||||
((PERIPH) == DMA2_Stream1) || \
|
||||
((PERIPH) == DMA2_Stream2) || \
|
||||
((PERIPH) == DMA2_Stream3) || \
|
||||
((PERIPH) == DMA2_Stream4) || \
|
||||
((PERIPH) == DMA2_Stream5) || \
|
||||
((PERIPH) == DMA2_Stream6) || \
|
||||
((PERIPH) == DMA2_Stream7))
|
||||
|
||||
#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
|
||||
((CONTROLLER) == DMA2))
|
||||
|
||||
/** @defgroup DMA_channel
|
||||
* @{
|
||||
*/
|
||||
#define DMA_Channel_0 ((uint32_t)0x00000000)
|
||||
#define DMA_Channel_1 ((uint32_t)0x02000000)
|
||||
#define DMA_Channel_2 ((uint32_t)0x04000000)
|
||||
#define DMA_Channel_3 ((uint32_t)0x06000000)
|
||||
#define DMA_Channel_4 ((uint32_t)0x08000000)
|
||||
#define DMA_Channel_5 ((uint32_t)0x0A000000)
|
||||
#define DMA_Channel_6 ((uint32_t)0x0C000000)
|
||||
#define DMA_Channel_7 ((uint32_t)0x0E000000)
|
||||
|
||||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
|
||||
((CHANNEL) == DMA_Channel_1) || \
|
||||
((CHANNEL) == DMA_Channel_2) || \
|
||||
((CHANNEL) == DMA_Channel_3) || \
|
||||
((CHANNEL) == DMA_Channel_4) || \
|
||||
((CHANNEL) == DMA_Channel_5) || \
|
||||
((CHANNEL) == DMA_Channel_6) || \
|
||||
((CHANNEL) == DMA_Channel_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
|
||||
#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
|
||||
#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
|
||||
((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \
|
||||
((DIRECTION) == DMA_DIR_MemoryToMemory))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_data_buffer_size
|
||||
* @{
|
||||
*/
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
|
||||
((STATE) == DMA_PeripheralInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
|
||||
((STATE) == DMA_MemoryInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word ))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000100)
|
||||
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
|
||||
((MODE) == DMA_Mode_Circular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00010000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00020000)
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00030000)
|
||||
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_VeryHigh))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_fifo_direct_mode
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOMode_Disable ((uint32_t)0x00000000)
|
||||
#define DMA_FIFOMode_Enable ((uint32_t)0x00000004)
|
||||
|
||||
#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
|
||||
((STATE) == DMA_FIFOMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_fifo_threshold_level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
|
||||
#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
|
||||
#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
|
||||
#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
|
||||
|
||||
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
|
||||
((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \
|
||||
((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
|
||||
((THRESHOLD) == DMA_FIFOThreshold_Full))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_memory_burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_MemoryBurst_Single ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000)
|
||||
#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000)
|
||||
#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000)
|
||||
|
||||
#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
|
||||
((BURST) == DMA_MemoryBurst_INC4) || \
|
||||
((BURST) == DMA_MemoryBurst_INC8) || \
|
||||
((BURST) == DMA_MemoryBurst_INC16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_burst
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000)
|
||||
#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000)
|
||||
#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000)
|
||||
|
||||
#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
|
||||
((BURST) == DMA_PeripheralBurst_INC4) || \
|
||||
((BURST) == DMA_PeripheralBurst_INC8) || \
|
||||
((BURST) == DMA_PeripheralBurst_INC16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_fifo_status_level
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3)
|
||||
#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3)
|
||||
#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3)
|
||||
#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3)
|
||||
#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3)
|
||||
#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3)
|
||||
|
||||
#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
|
||||
((STATUS) == DMA_FIFOStatus_HalfFull) || \
|
||||
((STATUS) == DMA_FIFOStatus_1QuarterFull) || \
|
||||
((STATUS) == DMA_FIFOStatus_3QuartersFull) || \
|
||||
((STATUS) == DMA_FIFOStatus_Full) || \
|
||||
((STATUS) == DMA_FIFOStatus_Empty))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001)
|
||||
#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004)
|
||||
#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008)
|
||||
#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010)
|
||||
#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020)
|
||||
#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040)
|
||||
#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100)
|
||||
#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200)
|
||||
#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400)
|
||||
#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800)
|
||||
#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000)
|
||||
#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000)
|
||||
#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000)
|
||||
#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000)
|
||||
#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000)
|
||||
#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000)
|
||||
#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000)
|
||||
#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000)
|
||||
#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000)
|
||||
#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000)
|
||||
#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001)
|
||||
#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004)
|
||||
#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008)
|
||||
#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010)
|
||||
#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020)
|
||||
#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040)
|
||||
#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100)
|
||||
#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200)
|
||||
#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400)
|
||||
#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800)
|
||||
#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000)
|
||||
#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000)
|
||||
#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000)
|
||||
#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000)
|
||||
#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000)
|
||||
#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000)
|
||||
#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000)
|
||||
#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000)
|
||||
#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000)
|
||||
#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
|
||||
(((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \
|
||||
((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \
|
||||
((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \
|
||||
((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \
|
||||
((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \
|
||||
((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \
|
||||
((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \
|
||||
((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \
|
||||
((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \
|
||||
((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \
|
||||
((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \
|
||||
((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \
|
||||
((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \
|
||||
((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \
|
||||
((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \
|
||||
((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \
|
||||
((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \
|
||||
((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \
|
||||
((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \
|
||||
((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupt_enable_definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_TC ((uint32_t)0x00000010)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000008)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000004)
|
||||
#define DMA_IT_DME ((uint32_t)0x00000002)
|
||||
#define DMA_IT_FE ((uint32_t)0x00000080)
|
||||
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_interrupts_definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_IT_FEIF0 ((uint32_t)0x90000001)
|
||||
#define DMA_IT_DMEIF0 ((uint32_t)0x10001004)
|
||||
#define DMA_IT_TEIF0 ((uint32_t)0x10002008)
|
||||
#define DMA_IT_HTIF0 ((uint32_t)0x10004010)
|
||||
#define DMA_IT_TCIF0 ((uint32_t)0x10008020)
|
||||
#define DMA_IT_FEIF1 ((uint32_t)0x90000040)
|
||||
#define DMA_IT_DMEIF1 ((uint32_t)0x10001100)
|
||||
#define DMA_IT_TEIF1 ((uint32_t)0x10002200)
|
||||
#define DMA_IT_HTIF1 ((uint32_t)0x10004400)
|
||||
#define DMA_IT_TCIF1 ((uint32_t)0x10008800)
|
||||
#define DMA_IT_FEIF2 ((uint32_t)0x90010000)
|
||||
#define DMA_IT_DMEIF2 ((uint32_t)0x10041000)
|
||||
#define DMA_IT_TEIF2 ((uint32_t)0x10082000)
|
||||
#define DMA_IT_HTIF2 ((uint32_t)0x10104000)
|
||||
#define DMA_IT_TCIF2 ((uint32_t)0x10208000)
|
||||
#define DMA_IT_FEIF3 ((uint32_t)0x90400000)
|
||||
#define DMA_IT_DMEIF3 ((uint32_t)0x11001000)
|
||||
#define DMA_IT_TEIF3 ((uint32_t)0x12002000)
|
||||
#define DMA_IT_HTIF3 ((uint32_t)0x14004000)
|
||||
#define DMA_IT_TCIF3 ((uint32_t)0x18008000)
|
||||
#define DMA_IT_FEIF4 ((uint32_t)0xA0000001)
|
||||
#define DMA_IT_DMEIF4 ((uint32_t)0x20001004)
|
||||
#define DMA_IT_TEIF4 ((uint32_t)0x20002008)
|
||||
#define DMA_IT_HTIF4 ((uint32_t)0x20004010)
|
||||
#define DMA_IT_TCIF4 ((uint32_t)0x20008020)
|
||||
#define DMA_IT_FEIF5 ((uint32_t)0xA0000040)
|
||||
#define DMA_IT_DMEIF5 ((uint32_t)0x20001100)
|
||||
#define DMA_IT_TEIF5 ((uint32_t)0x20002200)
|
||||
#define DMA_IT_HTIF5 ((uint32_t)0x20004400)
|
||||
#define DMA_IT_TCIF5 ((uint32_t)0x20008800)
|
||||
#define DMA_IT_FEIF6 ((uint32_t)0xA0010000)
|
||||
#define DMA_IT_DMEIF6 ((uint32_t)0x20041000)
|
||||
#define DMA_IT_TEIF6 ((uint32_t)0x20082000)
|
||||
#define DMA_IT_HTIF6 ((uint32_t)0x20104000)
|
||||
#define DMA_IT_TCIF6 ((uint32_t)0x20208000)
|
||||
#define DMA_IT_FEIF7 ((uint32_t)0xA0400000)
|
||||
#define DMA_IT_DMEIF7 ((uint32_t)0x21001000)
|
||||
#define DMA_IT_TEIF7 ((uint32_t)0x22002000)
|
||||
#define DMA_IT_HTIF7 ((uint32_t)0x24004000)
|
||||
#define DMA_IT_TCIF7 ((uint32_t)0x28008000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
|
||||
(((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
|
||||
(((IT) & 0x40820082) == 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \
|
||||
((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
|
||||
((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \
|
||||
((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \
|
||||
((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \
|
||||
((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \
|
||||
((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
|
||||
((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \
|
||||
((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \
|
||||
((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \
|
||||
((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \
|
||||
((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
|
||||
((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \
|
||||
((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \
|
||||
((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \
|
||||
((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \
|
||||
((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
|
||||
((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \
|
||||
((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \
|
||||
((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_peripheral_increment_offset
|
||||
* @{
|
||||
*/
|
||||
#define DMA_PINCOS_Psize ((uint32_t)0x00000000)
|
||||
#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000)
|
||||
|
||||
#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
|
||||
((SIZE) == DMA_PINCOS_WordAligned))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_flow_controller_definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000)
|
||||
#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020)
|
||||
|
||||
#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
|
||||
((CTRL) == DMA_FlowCtrl_Peripheral))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DMA_memory_targets_definitions
|
||||
* @{
|
||||
*/
|
||||
#define DMA_Memory_0 ((uint32_t)0x00000000)
|
||||
#define DMA_Memory_1 ((uint32_t)0x00080000)
|
||||
|
||||
#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the DMA configuration to the default reset state *****/
|
||||
void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
|
||||
|
||||
/* Optional Configuration functions *******************************************/
|
||||
void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
|
||||
void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
|
||||
|
||||
/* Data Counter functions *****************************************************/
|
||||
void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
|
||||
/* Double Buffer mode functions ***********************************************/
|
||||
void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
|
||||
uint32_t DMA_CurrentMemory);
|
||||
void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
|
||||
void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
|
||||
uint32_t DMA_MemoryTarget);
|
||||
uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
|
||||
FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
|
||||
void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
|
||||
void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
|
||||
void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_DMA_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,314 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the EXTI peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===================================================================
|
||||
##### EXTI features #####
|
||||
===================================================================
|
||||
|
||||
[..] External interrupt/event lines are mapped as following:
|
||||
(#) All available GPIO pins are connected to the 16 external
|
||||
interrupt/event lines from EXTI0 to EXTI15.
|
||||
(#) EXTI line 16 is connected to the PVD Output
|
||||
(#) EXTI line 17 is connected to the RTC Alarm event
|
||||
(#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
|
||||
(#) EXTI line 19 is connected to the Ethernet Wakeup event
|
||||
(#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
|
||||
(#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
|
||||
(#) EXTI line 22 is connected to the RTC Wakeup event
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
===================================================================
|
||||
|
||||
[..] In order to use an I/O pin as an external interrupt source, follow steps
|
||||
below:
|
||||
(#) Configure the I/O in input mode using GPIO_Init()
|
||||
(#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
|
||||
(#) Select the mode(interrupt, event) and configure the trigger
|
||||
selection (Rising, falling or both) using EXTI_Init()
|
||||
(#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
|
||||
|
||||
[..]
|
||||
(@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
|
||||
registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_conf.h"
|
||||
#include "stm32f4xx_exti.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMR = 0x00000000;
|
||||
EXTI->EMR = 0x00000000;
|
||||
EXTI->RTSR = 0x00000000;
|
||||
EXTI->FTSR = 0x00000000;
|
||||
EXTI->PR = 0x007FFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||
* that contains the configuration information for the EXTI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Select the trigger for the selected external interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
|
||||
* will be generated.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->SWIER |= EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group2 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||
* This parameter can be EXTI_Linex where x can be(0..22)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line: specifies the EXTI line to check.
|
||||
* This parameter can be EXTI_Linex where x can be(0..22)
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
enablestatus = EXTI->IMR & EXTI_Line;
|
||||
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..22)
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_EXTI_H
|
||||
#define __STM32F4xx_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination value of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTITrigger_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
|
||||
#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||
#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
|
||||
#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
|
||||
#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
|
||||
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
|
||||
((LINE) == EXTI_Line22))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the EXTI configuration to the default reset state *****/
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_EXTI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,390 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_FLASH_H
|
||||
#define __STM32F4xx_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_PGS,
|
||||
FLASH_ERROR_PGP,
|
||||
FLASH_ERROR_PGA,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_ERROR_PROGRAM,
|
||||
FLASH_ERROR_OPERATION,
|
||||
FLASH_COMPLETE
|
||||
}FLASH_Status;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Flash_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */
|
||||
#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */
|
||||
#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */
|
||||
#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */
|
||||
#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */
|
||||
#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1) || \
|
||||
((LATENCY) == FLASH_Latency_2) || \
|
||||
((LATENCY) == FLASH_Latency_3) || \
|
||||
((LATENCY) == FLASH_Latency_4) || \
|
||||
((LATENCY) == FLASH_Latency_5) || \
|
||||
((LATENCY) == FLASH_Latency_6) || \
|
||||
((LATENCY) == FLASH_Latency_7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Voltage_Range
|
||||
* @{
|
||||
*/
|
||||
#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
|
||||
#define VoltageRange_2 ((uint8_t)0x01) /*!<Device operating range: 2.1V to 2.7V */
|
||||
#define VoltageRange_3 ((uint8_t)0x02) /*!<Device operating range: 2.7V to 3.6V */
|
||||
#define VoltageRange_4 ((uint8_t)0x03) /*!<Device operating range: 2.7V to 3.6V + External Vpp */
|
||||
|
||||
#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
|
||||
((RANGE) == VoltageRange_2) || \
|
||||
((RANGE) == VoltageRange_3) || \
|
||||
((RANGE) == VoltageRange_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Sectors
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Sector_0 ((uint16_t)0x0000) /*!< Sector Number 0 */
|
||||
#define FLASH_Sector_1 ((uint16_t)0x0008) /*!< Sector Number 1 */
|
||||
#define FLASH_Sector_2 ((uint16_t)0x0010) /*!< Sector Number 2 */
|
||||
#define FLASH_Sector_3 ((uint16_t)0x0018) /*!< Sector Number 3 */
|
||||
#define FLASH_Sector_4 ((uint16_t)0x0020) /*!< Sector Number 4 */
|
||||
#define FLASH_Sector_5 ((uint16_t)0x0028) /*!< Sector Number 5 */
|
||||
#define FLASH_Sector_6 ((uint16_t)0x0030) /*!< Sector Number 6 */
|
||||
#define FLASH_Sector_7 ((uint16_t)0x0038) /*!< Sector Number 7 */
|
||||
#define FLASH_Sector_8 ((uint16_t)0x0040) /*!< Sector Number 8 */
|
||||
#define FLASH_Sector_9 ((uint16_t)0x0048) /*!< Sector Number 9 */
|
||||
#define FLASH_Sector_10 ((uint16_t)0x0050) /*!< Sector Number 10 */
|
||||
#define FLASH_Sector_11 ((uint16_t)0x0058) /*!< Sector Number 11 */
|
||||
#define FLASH_Sector_12 ((uint16_t)0x0080) /*!< Sector Number 12 */
|
||||
#define FLASH_Sector_13 ((uint16_t)0x0088) /*!< Sector Number 13 */
|
||||
#define FLASH_Sector_14 ((uint16_t)0x0090) /*!< Sector Number 14 */
|
||||
#define FLASH_Sector_15 ((uint16_t)0x0098) /*!< Sector Number 15 */
|
||||
#define FLASH_Sector_16 ((uint16_t)0x00A0) /*!< Sector Number 16 */
|
||||
#define FLASH_Sector_17 ((uint16_t)0x00A8) /*!< Sector Number 17 */
|
||||
#define FLASH_Sector_18 ((uint16_t)0x00B0) /*!< Sector Number 18 */
|
||||
#define FLASH_Sector_19 ((uint16_t)0x00B8) /*!< Sector Number 19 */
|
||||
#define FLASH_Sector_20 ((uint16_t)0x00C0) /*!< Sector Number 20 */
|
||||
#define FLASH_Sector_21 ((uint16_t)0x00C8) /*!< Sector Number 21 */
|
||||
#define FLASH_Sector_22 ((uint16_t)0x00D0) /*!< Sector Number 22 */
|
||||
#define FLASH_Sector_23 ((uint16_t)0x00D8) /*!< Sector Number 23 */
|
||||
|
||||
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) ||\
|
||||
((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) ||\
|
||||
((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) ||\
|
||||
((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) ||\
|
||||
((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) ||\
|
||||
((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11) ||\
|
||||
((SECTOR) == FLASH_Sector_12) || ((SECTOR) == FLASH_Sector_13) ||\
|
||||
((SECTOR) == FLASH_Sector_14) || ((SECTOR) == FLASH_Sector_15) ||\
|
||||
((SECTOR) == FLASH_Sector_16) || ((SECTOR) == FLASH_Sector_17) ||\
|
||||
((SECTOR) == FLASH_Sector_18) || ((SECTOR) == FLASH_Sector_19) ||\
|
||||
((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\
|
||||
((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23))
|
||||
|
||||
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\
|
||||
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
|
||||
#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
|
||||
#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
|
||||
#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
|
||||
#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
|
||||
#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
|
||||
#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
|
||||
#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
|
||||
#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
|
||||
#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
|
||||
#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
|
||||
#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
|
||||
#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */
|
||||
#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */
|
||||
#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */
|
||||
#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */
|
||||
#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */
|
||||
#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */
|
||||
#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */
|
||||
#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */
|
||||
#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */
|
||||
#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */
|
||||
#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */
|
||||
#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */
|
||||
#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_Level_1 ((uint8_t)0x55)
|
||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
||||
((LEVEL) == OB_RDP_Level_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup FLASH_Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_BOR_Reset_Level
|
||||
* @{
|
||||
*/
|
||||
#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
|
||||
#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
|
||||
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
|
||||
#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
|
||||
#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
|
||||
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */
|
||||
#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */
|
||||
#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */
|
||||
#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
|
||||
((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
|
||||
((FLAG) == FLASH_FLAG_BSY))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Program_Parallelism
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
|
||||
#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100)
|
||||
#define FLASH_PSIZE_WORD ((uint32_t)0x00000200)
|
||||
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300)
|
||||
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys
|
||||
* @{
|
||||
*/
|
||||
#define RDP_KEY ((uint16_t)0x00A5)
|
||||
#define FLASH_KEY1 ((uint32_t)0x45670123)
|
||||
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
|
||||
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
|
||||
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief ACR register byte 0 (Bits[7:0]) base address
|
||||
*/
|
||||
#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
|
||||
/**
|
||||
* @brief OPTCR register byte 0 (Bits[7:0]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14)
|
||||
/**
|
||||
* @brief OPTCR register byte 1 (Bits[15:8]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15)
|
||||
/**
|
||||
* @brief OPTCR register byte 2 (Bits[23:16]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16)
|
||||
/**
|
||||
* @brief OPTCR register byte 3 (Bits[31:24]) base address
|
||||
*/
|
||||
#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17)
|
||||
|
||||
/**
|
||||
* @brief OPTCR1 register byte 0 (Bits[7:0]) base address
|
||||
*/
|
||||
#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* FLASH Interface configuration functions ************************************/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
|
||||
void FLASH_InstructionCacheCmd(FunctionalState NewState);
|
||||
void FLASH_DataCacheCmd(FunctionalState NewState);
|
||||
void FLASH_InstructionCacheReset(void);
|
||||
void FLASH_DataCacheReset(void);
|
||||
|
||||
/* FLASH Memory Programming functions *****************************************/
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
|
||||
FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
|
||||
FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
|
||||
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
|
||||
|
||||
/* Option Bytes Programming functions *****************************************/
|
||||
void FLASH_OB_Unlock(void);
|
||||
void FLASH_OB_Lock(void);
|
||||
void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
|
||||
void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
|
||||
void FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
||||
void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
|
||||
void FLASH_OB_BORConfig(uint8_t OB_BOR);
|
||||
FLASH_Status FLASH_OB_Launch(void);
|
||||
uint8_t FLASH_OB_GetUser(void);
|
||||
uint16_t FLASH_OB_GetWRP(void);
|
||||
uint16_t FLASH_OB_GetWRP1(void);
|
||||
FlagStatus FLASH_OB_GetRDP(void);
|
||||
uint8_t FLASH_OB_GetBOR(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_FLASH_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,585 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + GPIO Read and Write
|
||||
* + GPIO Alternate functions configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
|
||||
|
||||
(#) Configure the GPIO pin(s) using GPIO_Init()
|
||||
Four possible configuration are available for each pin:
|
||||
(++) Input: Floating, Pull-up, Pull-down.
|
||||
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed
|
||||
is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz.
|
||||
(++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open
|
||||
Drain (Pull-up, Pull-down or no Pull).
|
||||
(++) Analog: required mode when a pin is to be used as ADC channel or DAC
|
||||
output.
|
||||
|
||||
(#) Peripherals alternate function:
|
||||
(++) For ADC and DAC, configure the desired pin in analog mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
|
||||
(+++) For other peripherals (TIM, USART...):
|
||||
(+++) Connect the pin to the desired peripherals' Alternate
|
||||
Function (AF) using GPIO_PinAFConfig() function
|
||||
(+++) Configure the desired pin in alternate function mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
(+++) Select the type, pull-up/pull-down and output speed via
|
||||
GPIO_PuPd, GPIO_OType and GPIO_Speed members
|
||||
(+++) Call GPIO_Init() function
|
||||
|
||||
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
GPIO_SetBits()/GPIO_ResetBits()
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_conf.h"
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group1 Initialization and Configuration
|
||||
* @brief Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if (GPIOx == GPIOA)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOB)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOC)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOD)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOE)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOF)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOG)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
|
||||
}
|
||||
else if (GPIOx == GPIOH)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (GPIOx == GPIOI)
|
||||
{
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
|
||||
RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
|
||||
|
||||
/* ------------------------- Configure the port pins ---------------- */
|
||||
/*-- GPIO Mode Configuration --*/
|
||||
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if (currentpin == pos)
|
||||
{
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
|
||||
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
|
||||
|
||||
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
|
||||
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
|
||||
|
||||
/* Check Output mode parameters */
|
||||
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
|
||||
|
||||
/* Output mode configuration*/
|
||||
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
|
||||
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
|
||||
}
|
||||
|
||||
/* Pull-up Pull down resistor configuration*/
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
|
||||
GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_Pin: specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group2 GPIO Read and Write
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Read and Write #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @retval GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRH = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enum values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRRH = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param PortVal: specifies the value to be written to the port output data register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins..
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_Pin: Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
|
||||
* @brief GPIO Alternate functions configuration function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Alternate functions configuration function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
|
||||
* STM32F40xx/41xx and STM32F427x/437x devices.
|
||||
* @param GPIO_PinSource: specifies the pin for the Alternate function.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @param GPIO_AFSelection: selects the pin to used as Alternate function.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset)
|
||||
* @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset)
|
||||
* @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
|
||||
* @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
|
||||
* @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
|
||||
* @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
|
||||
* @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
|
||||
* @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
|
||||
* @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
|
||||
* @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
|
||||
* @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
|
||||
* @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
|
||||
* @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
|
||||
* @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
|
||||
* @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
|
||||
* @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
|
||||
* @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5
|
||||
* @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5
|
||||
* @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5
|
||||
* @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
|
||||
* @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
|
||||
* @arg GPIO_AF_USART1: Connect USART1 pins to AF7
|
||||
* @arg GPIO_AF_USART2: Connect USART2 pins to AF7
|
||||
* @arg GPIO_AF_USART3: Connect USART3 pins to AF7
|
||||
* @arg GPIO_AF_UART4: Connect UART4 pins to AF8
|
||||
* @arg GPIO_AF_UART5: Connect UART5 pins to AF8
|
||||
* @arg GPIO_AF_USART6: Connect USART6 pins to AF8
|
||||
* @arg GPIO_AF_UART7: Connect UART7 pins to AF8
|
||||
* @arg GPIO_AF_UART8: Connect UART8 pins to AF8
|
||||
* @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
|
||||
* @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
|
||||
* @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
|
||||
* @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
|
||||
* @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
|
||||
* @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
|
||||
* @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
|
||||
* @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
|
||||
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
|
||||
* @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
|
||||
* @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
|
||||
* @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
|
||||
* @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
|
||||
{
|
||||
uint32_t temp = 0x00;
|
||||
uint32_t temp_2 = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
assert_param(IS_GPIO_AF(GPIO_AF));
|
||||
|
||||
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,423 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file contains all the functions prototypes for the GPIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_GPIO_H
|
||||
#define __STM32F4xx_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG) || \
|
||||
((PERIPH) == GPIOH) || \
|
||||
((PERIPH) == GPIOI))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration Mode enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
|
||||
/**
|
||||
* @brief GPIO Output type enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Output Maximum frequency enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_2MHz = 0x00, /*!< Low speed */
|
||||
GPIO_Speed_25MHz = 0x01, /*!< Medium speed */
|
||||
GPIO_Speed_50MHz = 0x02, /*!< Fast speed */
|
||||
GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
|
||||
}GPIOSpeed_TypeDef;
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
|
||||
((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz))
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration PullUp PullDown enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
|
||||
/**
|
||||
* @brief GPIO Bit SET and Bit RESET enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternat_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
|
||||
#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
|
||||
#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
|
||||
#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
|
||||
#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
|
||||
#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
|
||||
#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
|
||||
#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
|
||||
#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 9 selection
|
||||
*/
|
||||
#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
|
||||
#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
|
||||
|
||||
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
|
||||
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 13 selection
|
||||
*/
|
||||
#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \
|
||||
((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \
|
||||
((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \
|
||||
((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \
|
||||
((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \
|
||||
((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \
|
||||
((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \
|
||||
((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \
|
||||
((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \
|
||||
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \
|
||||
((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \
|
||||
((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \
|
||||
((AF) == GPIO_AF_FSMC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Mode_AIN GPIO_Mode_AN
|
||||
|
||||
#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS
|
||||
#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS
|
||||
#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the GPIO configuration to the default reset state ****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Alternate functions configuration function ****************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32F4xx_GPIO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,545 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f4xx_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file contains all the functions prototypes for the RCC firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32F4xx_RCC_H
|
||||
#define __STM32F4xx_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_HSE_ON ((uint8_t)0x01)
|
||||
#define RCC_HSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE))
|
||||
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
|
||||
#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
|
||||
#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
|
||||
|
||||
#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
|
||||
#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00001000)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00001400)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00001800)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00001C00)
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Interrupt_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
|
||||
((IT) == RCC_IT_PLLI2SRDY))
|
||||
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||
#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300)
|
||||
#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300)
|
||||
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300)
|
||||
#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300)
|
||||
#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300)
|
||||
#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300)
|
||||
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300)
|
||||
#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300)
|
||||
#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300)
|
||||
#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300)
|
||||
#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300)
|
||||
#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300)
|
||||
#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300)
|
||||
#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300)
|
||||
#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300)
|
||||
#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300)
|
||||
#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300)
|
||||
#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300)
|
||||
#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300)
|
||||
#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300)
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_I2S_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00)
|
||||
#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_TIM_PRescaler_Selection
|
||||
* @{
|
||||
*/
|
||||
#define RCC_TIMPrescDesactivated ((uint8_t)0x00)
|
||||
#define RCC_TIMPrescActivated ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001)
|
||||
#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002)
|
||||
#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004)
|
||||
#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008)
|
||||
#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010)
|
||||
#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020)
|
||||
#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040)
|
||||
#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080)
|
||||
#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100)
|
||||
#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000)
|
||||
#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000)
|
||||
#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000)
|
||||
#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000)
|
||||
#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000)
|
||||
#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000)
|
||||
#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000)
|
||||
#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
|
||||
#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
|
||||
#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000)
|
||||
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
|
||||
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
|
||||
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81906E00) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
|
||||
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
|
||||
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
|
||||
#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
|
||||
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
|
||||
#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB3_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
|
||||
|
||||
#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
|
||||
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
|
||||
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
|
||||
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020)
|
||||
#define RCC_APB2Periph_ADC ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400)
|
||||
#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
|
||||
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
|
||||
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
|
||||
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
|
||||
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC880CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFC886CC) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO1_Clock_Source_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO1Source_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1Source_LSE ((uint32_t)0x00200000)
|
||||
#define RCC_MCO1Source_HSE ((uint32_t)0x00400000)
|
||||
#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000)
|
||||
#define RCC_MCO1Div_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO1Div_2 ((uint32_t)0x04000000)
|
||||
#define RCC_MCO1Div_3 ((uint32_t)0x05000000)
|
||||
#define RCC_MCO1Div_4 ((uint32_t)0x06000000)
|
||||
#define RCC_MCO1Div_5 ((uint32_t)0x07000000)
|
||||
#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
|
||||
((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
|
||||
|
||||
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
|
||||
((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
|
||||
((DIV) == RCC_MCO1Div_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO2_Clock_Source_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000)
|
||||
#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000)
|
||||
#define RCC_MCO2Source_HSE ((uint32_t)0x80000000)
|
||||
#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000)
|
||||
#define RCC_MCO2Div_1 ((uint32_t)0x00000000)
|
||||
#define RCC_MCO2Div_2 ((uint32_t)0x20000000)
|
||||
#define RCC_MCO2Div_3 ((uint32_t)0x28000000)
|
||||
#define RCC_MCO2Div_4 ((uint32_t)0x30000000)
|
||||
#define RCC_MCO2Div_5 ((uint32_t)0x38000000)
|
||||
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
|
||||
((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
|
||||
|
||||
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
|
||||
((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
|
||||
((DIV) == RCC_MCO2Div_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_BORRST ((uint8_t)0x79)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
|
||||
((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
|
||||
((FLAG) == RCC_FLAG_PLLI2SRDY))
|
||||
|
||||
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
|
||||
void RCC_HSEConfig(uint8_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
|
||||
void RCC_PLLI2SCmd(FunctionalState NewState);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
|
||||
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||||
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
|
||||
|
||||
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
||||
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||||
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32F4xx_RCC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,250 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* How to configure Interrupts using driver
|
||||
* ===================================================================
|
||||
*
|
||||
* This section provide functions allowing to configure the NVIC interrupts (IRQ).
|
||||
* The Cortex-M4 exceptions are managed by CMSIS functions.
|
||||
*
|
||||
* 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
|
||||
* function according to the following table.
|
||||
|
||||
* The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
* to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
* ==========================================================================================================================
|
||||
* NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
* ==========================================================================================================================
|
||||
* NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
* | | | 4 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
* | | | 3 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
* | | | 2 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
* | | | 1 bits for subpriority
|
||||
* --------------------------------------------------------------------------------------------------------------------------
|
||||
* NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
* | | | 0 bits for subpriority
|
||||
* ==========================================================================================================================
|
||||
*
|
||||
* 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()
|
||||
*
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
*
|
||||
* @note IRQ priority order (sorted by highest to lowest priority):
|
||||
* - Lowest pre-emption priority
|
||||
* - Lowest subpriority
|
||||
* - Lowest hardware priority (IRQ number)
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_conf.h"
|
||||
#include "stm_misc.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: pre-emption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
|
||||
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
|
||||
* @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
|
||||
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
|
||||
* @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
|
||||
* @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
|
||||
* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MISC_H
|
||||
#define __MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/** @addtogroup STM32F4xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be an enumerator of @ref IRQn_Type
|
||||
enumeration (For the complete STM32 Devices IRQ Channels
|
||||
list, please refer to stm32f4xx.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
|
||||
A lower priority value indicates a higher priority */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F4XX_H
|
||||
#define __SYSTEM_STM32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F4XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_bsp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file is responsible to offer board support package and is
|
||||
* configurable by user.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx_gpio.h"
|
||||
#include "stm32f4xx_rcc.h"
|
||||
#include "stm_misc.h"
|
||||
#include "usb_bsp.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP
|
||||
* @brief This file is responsible to offer board support package
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBH_BSP_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBH_BSP_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_Init
|
||||
* Initilizes BSP configurations
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) {
|
||||
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
|
||||
|
||||
/* Configure DM DP Pins */
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource11, GPIO_AF_OTG1_FS);
|
||||
GPIO_PinAFConfig(GPIOA, GPIO_PinSource12, GPIO_AF_OTG1_FS);
|
||||
|
||||
/* Configure VBUS Pin (or disable VBUS_SENSING_ENABLED) */
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_EnableInterrupt
|
||||
* Enabele USB Global interrupt
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) {
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
|
||||
NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_uDelay
|
||||
* This function provides delay time in micro sec
|
||||
* @param usec : Value of delay required in micro sec
|
||||
* @retval None
|
||||
*/
|
||||
void USB_OTG_BSP_uDelay (const uint32_t usec)
|
||||
{
|
||||
uint32_t count = 0;
|
||||
const uint32_t utime = (160 * usec / 5);
|
||||
do
|
||||
{
|
||||
if ( ++count > utime )
|
||||
{
|
||||
return ;
|
||||
}
|
||||
}
|
||||
while (1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_BSP_mDelay
|
||||
* This function provides delay time in milli sec
|
||||
* @param msec : Value of delay required in milli sec
|
||||
* @retval None
|
||||
*/
|
||||
void USB_OTG_BSP_mDelay (const uint32_t msec)
|
||||
{
|
||||
USB_OTG_BSP_uDelay(msec * 1000);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_bsp.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Specific api's relative to the used hardware platform
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_BSP__H__
|
||||
#define __USB_BSP__H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_core.h"
|
||||
#include "usb_conf.h"
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_BSP_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_BSP_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
void BSP_Init(void);
|
||||
|
||||
void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_BSP_uDelay (const uint32_t usec);
|
||||
void USB_OTG_BSP_mDelay (const uint32_t msec);
|
||||
void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev);
|
||||
#ifdef USE_HOST_MODE
|
||||
void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif //__USB_BSP__H__
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,293 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief General low level driver configuration
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_CONF__H__
|
||||
#define __USB_CONF__H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f4xx.h"
|
||||
//#include "stm324xg_eval.h"
|
||||
//#include "stm324xg_eval_lcd.h"
|
||||
//#include "stm324xg_eval_ioe.h"
|
||||
//#include "stm324xg_eval_sdio_sd.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF
|
||||
* @brief USB low level driver configuration file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* USB Core and PHY interface configuration.
|
||||
Tip: To avoid modifying these defines each time you need to change the USB
|
||||
configuration, you can declare the needed define in your toolchain
|
||||
compiler preprocessor.
|
||||
*/
|
||||
/****************** USB OTG FS PHY CONFIGURATION *******************************
|
||||
* The USB OTG FS Core supports one on-chip Full Speed PHY.
|
||||
*
|
||||
* The USE_EMBEDDED_PHY symbol is defined in the project compiler preprocessor
|
||||
* when FS core is used.
|
||||
*******************************************************************************/
|
||||
#ifndef USE_USB_OTG_FS
|
||||
#define USE_USB_OTG_FS
|
||||
#endif /* USE_USB_OTG_FS */
|
||||
|
||||
#ifdef USE_USB_OTG_FS
|
||||
#define USB_OTG_FS_CORE
|
||||
#endif
|
||||
|
||||
/****************** USB OTG HS PHY CONFIGURATION *******************************
|
||||
* The USB OTG HS Core supports two PHY interfaces:
|
||||
* (i) An ULPI interface for the external High Speed PHY: the USB HS Core will
|
||||
* operate in High speed mode
|
||||
* (ii) An on-chip Full Speed PHY: the USB HS Core will operate in Full speed mode
|
||||
*
|
||||
* You can select the PHY to be used using one of these two defines:
|
||||
* (i) USE_ULPI_PHY: if the USB OTG HS Core is to be used in High speed mode
|
||||
* (ii) USE_EMBEDDED_PHY: if the USB OTG HS Core is to be used in Full speed mode
|
||||
*
|
||||
* Notes:
|
||||
* - The USE_ULPI_PHY symbol is defined in the project compiler preprocessor as
|
||||
* default PHY when HS core is used.
|
||||
* - On STM322xG-EVAL and STM324xG-EVAL boards, only configuration(i) is available.
|
||||
* Configuration (ii) need a different hardware, for more details refer to your
|
||||
* STM32 device datasheet.
|
||||
*******************************************************************************/
|
||||
#ifndef USE_USB_OTG_HS
|
||||
//#define USE_USB_OTG_HS
|
||||
#endif /* USE_USB_OTG_HS */
|
||||
|
||||
#ifndef USE_ULPI_PHY
|
||||
//#define USE_ULPI_PHY
|
||||
#endif /* USE_ULPI_PHY */
|
||||
|
||||
#ifndef USE_EMBEDDED_PHY
|
||||
//#define USE_EMBEDDED_PHY
|
||||
#endif /* USE_EMBEDDED_PHY */
|
||||
|
||||
#ifdef USE_USB_OTG_HS
|
||||
#define USB_OTG_HS_CORE
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* FIFO Size Configuration in Device mode
|
||||
*
|
||||
* (i) Receive data FIFO size = RAM for setup packets +
|
||||
* OUT endpoint control information +
|
||||
* data OUT packets + miscellaneous
|
||||
* Space = ONE 32-bits words
|
||||
* --> RAM for setup packets = 10 spaces
|
||||
* (n is the nbr of CTRL EPs the device core supports)
|
||||
* --> OUT EP CTRL info = 1 space
|
||||
* (one space for status information written to the FIFO along with each
|
||||
* received packet)
|
||||
* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces
|
||||
* (MINIMUM to receive packets)
|
||||
* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces
|
||||
* (if high-bandwidth EP is enabled or multiple isochronous EPs)
|
||||
* --> miscellaneous = 1 space per OUT EP
|
||||
* (one space for transfer complete status information also pushed to the
|
||||
* FIFO with each endpoint's last packet)
|
||||
*
|
||||
* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for
|
||||
* that particular IN EP. More space allocated in the IN EP Tx FIFO results
|
||||
* in a better performance on the USB and can hide latencies on the AHB.
|
||||
*
|
||||
* (iii) TXn min size = 16 words. (n : Transmit FIFO index)
|
||||
* (iv) When a TxFIFO is not used, the Configuration should be as follows:
|
||||
* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||
* --> Txm can use the space allocated for Txn.
|
||||
* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
|
||||
* --> Txn should be configured with the minimum space of 16 words
|
||||
* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top
|
||||
* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
|
||||
* (vi) In HS case 12 FIFO locations should be reserved for internal DMA registers
|
||||
* so total FIFO size should be 1012 Only instead of 1024
|
||||
*******************************************************************************/
|
||||
|
||||
/****************** USB OTG HS CONFIGURATION **********************************/
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
#define RX_FIFO_HS_SIZE 512
|
||||
#define TX0_FIFO_HS_SIZE 128
|
||||
#define TX1_FIFO_HS_SIZE 372
|
||||
#define TX2_FIFO_HS_SIZE 64
|
||||
#define TX3_FIFO_HS_SIZE 0
|
||||
#define TX4_FIFO_HS_SIZE 0
|
||||
#define TX5_FIFO_HS_SIZE 0
|
||||
|
||||
// #define USB_OTG_HS_SOF_OUTPUT_ENABLED
|
||||
|
||||
#ifdef USE_ULPI_PHY
|
||||
#define USB_OTG_ULPI_PHY_ENABLED
|
||||
#endif
|
||||
#ifdef USE_EMBEDDED_PHY
|
||||
#define USB_OTG_EMBEDDED_PHY_ENABLED
|
||||
/* wakeup is working only when HS core is configured in FS mode */
|
||||
#define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT
|
||||
#endif
|
||||
/* #define USB_OTG_HS_INTERNAL_DMA_ENABLED */ /* Be aware that enabling DMA mode will result in data being sent only by
|
||||
multiple of 4 packet sizes. This is due to the fact that USB DMA does
|
||||
not allow sending data from non word-aligned addresses.
|
||||
For this specific application, it is advised to not enable this option
|
||||
unless required. */
|
||||
#define USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
#endif
|
||||
|
||||
/****************** USB OTG FS CONFIGURATION **********************************/
|
||||
#ifdef USB_OTG_FS_CORE
|
||||
#define RX_FIFO_FS_SIZE 128
|
||||
#define TX0_FIFO_FS_SIZE 32
|
||||
#define TX1_FIFO_FS_SIZE 128
|
||||
#define TX2_FIFO_FS_SIZE 32
|
||||
#define TX3_FIFO_FS_SIZE 0
|
||||
|
||||
// #define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT
|
||||
// #define USB_OTG_FS_SOF_OUTPUT_ENABLED
|
||||
#endif
|
||||
|
||||
/****************** USB OTG MISC CONFIGURATION ********************************/
|
||||
#define VBUS_SENSING_ENABLED
|
||||
|
||||
/****************** USB OTG MODE CONFIGURATION ********************************/
|
||||
//#define USE_HOST_MODE
|
||||
#define USE_DEVICE_MODE
|
||||
//#define USE_OTG_MODE
|
||||
|
||||
#ifndef USB_OTG_FS_CORE
|
||||
#ifndef USB_OTG_HS_CORE
|
||||
#error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef USE_DEVICE_MODE
|
||||
#ifndef USE_HOST_MODE
|
||||
#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef USE_USB_OTG_HS
|
||||
#ifndef USE_USB_OTG_FS
|
||||
#error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined"
|
||||
#endif
|
||||
#else //USE_USB_OTG_HS
|
||||
#ifndef USE_ULPI_PHY
|
||||
#ifndef USE_EMBEDDED_PHY
|
||||
#error "USE_ULPI_PHY or USE_EMBEDDED_PHY should be defined"
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/****************** C Compilers dependant keywords ****************************/
|
||||
/* In HS mode and when the DMA is used, all variables and data structures dealing
|
||||
with the DMA during the transaction process should be 4-bytes aligned */
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined (__GNUC__) /* GNU Compiler */
|
||||
#define __ALIGN_END __attribute__ ((aligned (4)))
|
||||
#define __ALIGN_BEGIN
|
||||
#else
|
||||
#define __ALIGN_END
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __ALIGN_BEGIN
|
||||
#elif defined (__TASKING__) /* TASKING Compiler */
|
||||
#define __ALIGN_BEGIN __align(4)
|
||||
#endif /* __CC_ARM */
|
||||
#endif /* __GNUC__ */
|
||||
#else
|
||||
#define __ALIGN_BEGIN
|
||||
#define __ALIGN_END
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
|
||||
/* __packed keyword used to decrease the data type alignment to 1-byte */
|
||||
#if defined (__CC_ARM) /* ARM Compiler */
|
||||
#define __packed __packed
|
||||
#elif defined (__ICCARM__) /* IAR Compiler */
|
||||
#define __packed __packed
|
||||
#elif defined ( __GNUC__ ) /* GNU Compiler */
|
||||
#define __packed __attribute__ ((__packed__))
|
||||
#elif defined (__TASKING__) /* TASKING Compiler */
|
||||
#define __packed __unaligned
|
||||
#endif /* __CC_ARM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif //__USB_CONF__H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,417 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_core.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Header of the Core Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_CORE_H__
|
||||
#define __USB_CORE_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
#include "usb_regs.h"
|
||||
#include "usb_defines.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE
|
||||
* @brief usb otg driver core layer
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_OTG_EP0_IDLE 0
|
||||
#define USB_OTG_EP0_SETUP 1
|
||||
#define USB_OTG_EP0_DATA_IN 2
|
||||
#define USB_OTG_EP0_DATA_OUT 3
|
||||
#define USB_OTG_EP0_STATUS_IN 4
|
||||
#define USB_OTG_EP0_STATUS_OUT 5
|
||||
#define USB_OTG_EP0_STALL 6
|
||||
|
||||
#define USB_OTG_EP_TX_DIS 0x0000
|
||||
#define USB_OTG_EP_TX_STALL 0x0010
|
||||
#define USB_OTG_EP_TX_NAK 0x0020
|
||||
#define USB_OTG_EP_TX_VALID 0x0030
|
||||
|
||||
#define USB_OTG_EP_RX_DIS 0x0000
|
||||
#define USB_OTG_EP_RX_STALL 0x1000
|
||||
#define USB_OTG_EP_RX_NAK 0x2000
|
||||
#define USB_OTG_EP_RX_VALID 0x3000
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#define MAX_DATA_LENGTH 0x200
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
typedef enum {
|
||||
USB_OTG_OK = 0,
|
||||
USB_OTG_FAIL
|
||||
}USB_OTG_STS;
|
||||
|
||||
typedef enum {
|
||||
HC_IDLE = 0,
|
||||
HC_XFRC,
|
||||
HC_HALTED,
|
||||
HC_NAK,
|
||||
HC_NYET,
|
||||
HC_STALL,
|
||||
HC_XACTERR,
|
||||
HC_BBLERR,
|
||||
HC_DATATGLERR,
|
||||
}HC_STATUS;
|
||||
|
||||
typedef enum {
|
||||
URB_IDLE = 0,
|
||||
URB_DONE,
|
||||
URB_NOTREADY,
|
||||
URB_ERROR,
|
||||
URB_STALL
|
||||
}URB_STATE;
|
||||
|
||||
typedef enum {
|
||||
CTRL_START = 0,
|
||||
CTRL_XFRC,
|
||||
CTRL_HALTED,
|
||||
CTRL_NAK,
|
||||
CTRL_STALL,
|
||||
CTRL_XACTERR,
|
||||
CTRL_BBLERR,
|
||||
CTRL_DATATGLERR,
|
||||
CTRL_FAIL
|
||||
}CTRL_STATUS;
|
||||
|
||||
|
||||
typedef struct USB_OTG_hc
|
||||
{
|
||||
uint8_t dev_addr ;
|
||||
uint8_t ep_num;
|
||||
uint8_t ep_is_in;
|
||||
uint8_t speed;
|
||||
uint8_t do_ping;
|
||||
uint8_t ep_type;
|
||||
uint16_t max_packet;
|
||||
uint8_t data_pid;
|
||||
uint8_t *xfer_buff;
|
||||
uint32_t xfer_len;
|
||||
uint32_t xfer_count;
|
||||
uint8_t toggle_in;
|
||||
uint8_t toggle_out;
|
||||
uint32_t dma_addr;
|
||||
}
|
||||
USB_OTG_HC , *PUSB_OTG_HC;
|
||||
|
||||
typedef struct USB_OTG_ep
|
||||
{
|
||||
uint8_t num;
|
||||
uint8_t is_in;
|
||||
uint8_t is_stall;
|
||||
uint8_t type;
|
||||
uint8_t data_pid_start;
|
||||
uint8_t even_odd_frame;
|
||||
uint16_t tx_fifo_num;
|
||||
uint32_t maxpacket;
|
||||
/* transaction level variables*/
|
||||
uint8_t *xfer_buff;
|
||||
uint32_t dma_addr;
|
||||
uint32_t xfer_len;
|
||||
uint32_t xfer_count;
|
||||
/* Transfer level variables*/
|
||||
uint32_t rem_data_len;
|
||||
uint32_t total_data_len;
|
||||
uint32_t ctl_data_len;
|
||||
|
||||
}
|
||||
|
||||
USB_OTG_EP , *PUSB_OTG_EP;
|
||||
|
||||
|
||||
|
||||
typedef struct USB_OTG_core_cfg
|
||||
{
|
||||
uint8_t host_channels;
|
||||
uint8_t dev_endpoints;
|
||||
uint8_t speed;
|
||||
uint8_t dma_enable;
|
||||
uint16_t mps;
|
||||
uint16_t TotalFifoSize;
|
||||
uint8_t phy_itface;
|
||||
uint8_t Sof_output;
|
||||
uint8_t low_power;
|
||||
uint8_t coreID;
|
||||
|
||||
}
|
||||
USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS;
|
||||
|
||||
|
||||
|
||||
typedef struct usb_setup_req {
|
||||
|
||||
uint8_t bmRequest;
|
||||
uint8_t bRequest;
|
||||
uint16_t wValue;
|
||||
uint16_t wIndex;
|
||||
uint16_t wLength;
|
||||
} USB_SETUP_REQ;
|
||||
|
||||
typedef struct _Device_TypeDef
|
||||
{
|
||||
uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length);
|
||||
} USBD_DEVICE, *pUSBD_DEVICE;
|
||||
|
||||
//typedef struct USB_OTG_hPort
|
||||
//{
|
||||
// void (*Disconnect) (void *phost);
|
||||
// void (*Connect) (void *phost);
|
||||
// uint8_t ConnStatus;
|
||||
// uint8_t DisconnStatus;
|
||||
// uint8_t ConnHandled;
|
||||
// uint8_t DisconnHandled;
|
||||
//} USB_OTG_hPort_TypeDef;
|
||||
|
||||
typedef struct _Device_cb
|
||||
{
|
||||
uint8_t (*Init) (void *pdev , uint8_t cfgidx);
|
||||
uint8_t (*DeInit) (void *pdev , uint8_t cfgidx);
|
||||
/* Control Endpoints*/
|
||||
uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req);
|
||||
uint8_t (*EP0_TxSent) (void *pdev );
|
||||
uint8_t (*EP0_RxReady) (void *pdev );
|
||||
/* Class Specific Endpoints*/
|
||||
uint8_t (*DataIn) (void *pdev , uint8_t epnum);
|
||||
uint8_t (*DataOut) (void *pdev , uint8_t epnum);
|
||||
uint8_t (*SOF) (void *pdev);
|
||||
uint8_t (*IsoINIncomplete) (void *pdev);
|
||||
uint8_t (*IsoOUTIncomplete) (void *pdev);
|
||||
|
||||
uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length);
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length);
|
||||
#endif
|
||||
|
||||
#ifdef USB_SUPPORT_USER_STRING_DESC
|
||||
uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length);
|
||||
#endif
|
||||
|
||||
} USBD_Class_cb_TypeDef;
|
||||
|
||||
|
||||
|
||||
typedef struct _USBD_USR_PROP
|
||||
{
|
||||
void (*Init)(void);
|
||||
void (*DeviceReset)(uint8_t speed);
|
||||
void (*DeviceConfigured)(void);
|
||||
void (*DeviceSuspended)(void);
|
||||
void (*DeviceResumed)(void);
|
||||
|
||||
void (*DeviceConnected)(void);
|
||||
void (*DeviceDisconnected)(void);
|
||||
|
||||
}
|
||||
USBD_Usr_cb_TypeDef;
|
||||
|
||||
typedef struct _DCD
|
||||
{
|
||||
uint8_t device_config;
|
||||
uint8_t device_state;
|
||||
uint8_t device_status;
|
||||
uint8_t device_old_status;
|
||||
uint8_t device_address;
|
||||
uint8_t connection_status;
|
||||
uint8_t test_mode;
|
||||
uint32_t DevRemoteWakeup;
|
||||
USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS];
|
||||
USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS];
|
||||
uint8_t setup_packet [8*3];
|
||||
USBD_Class_cb_TypeDef *class_cb;
|
||||
USBD_Usr_cb_TypeDef *usr_cb;
|
||||
USBD_DEVICE *usr_device;
|
||||
uint8_t *pConfig_descriptor;
|
||||
}
|
||||
DCD_DEV , *DCD_PDEV;
|
||||
|
||||
|
||||
typedef struct _HCD
|
||||
{
|
||||
uint8_t Rx_Buffer [MAX_DATA_LENGTH];
|
||||
__IO uint32_t ConnSts;
|
||||
__IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS];
|
||||
__IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS];
|
||||
__IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS];
|
||||
__IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS];
|
||||
USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS];
|
||||
uint16_t channel [USB_OTG_MAX_TX_FIFOS];
|
||||
// USB_OTG_hPort_TypeDef *port_cb;
|
||||
}
|
||||
HCD_DEV , *USB_OTG_USBH_PDEV;
|
||||
|
||||
|
||||
typedef struct _OTG
|
||||
{
|
||||
uint8_t OTG_State;
|
||||
uint8_t OTG_PrevState;
|
||||
uint8_t OTG_Mode;
|
||||
}
|
||||
OTG_DEV , *USB_OTG_USBO_PDEV;
|
||||
|
||||
typedef struct USB_OTG_handle
|
||||
{
|
||||
USB_OTG_CORE_CFGS cfg;
|
||||
USB_OTG_CORE_REGS regs;
|
||||
#ifdef USE_DEVICE_MODE
|
||||
DCD_DEV dev;
|
||||
#endif
|
||||
#ifdef USE_HOST_MODE
|
||||
HCD_DEV host;
|
||||
#endif
|
||||
#ifdef USE_OTG_MODE
|
||||
OTG_DEV otg;
|
||||
#endif
|
||||
}
|
||||
USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_OTG_CORE_ID_TypeDef coreID);
|
||||
USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev);
|
||||
void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t *dest,
|
||||
uint16_t len);
|
||||
USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t *src,
|
||||
uint8_t ch_ep_num,
|
||||
uint16_t len);
|
||||
USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num);
|
||||
USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t mode);
|
||||
|
||||
/*********************** HOST APIs ********************************************/
|
||||
#ifdef USE_HOST_MODE
|
||||
USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
|
||||
USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
|
||||
USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num);
|
||||
USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num);
|
||||
uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state);
|
||||
void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq);
|
||||
uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ;
|
||||
void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev);
|
||||
#endif
|
||||
/********************* DEVICE APIs ********************************************/
|
||||
#ifdef USE_DEVICE_MODE
|
||||
USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
|
||||
enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev);
|
||||
USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep);
|
||||
uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
|
||||
uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed);
|
||||
uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev);
|
||||
void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status);
|
||||
uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USB_CORE_H__ */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,478 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_dcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Peripheral Device Interface Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_dcd.h"
|
||||
#include "usb_bsp.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD
|
||||
* @brief This file is the interface between EFSL ans Host mass-storage class
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
void DCD_Init(USB_OTG_CORE_HANDLE *pdev ,
|
||||
USB_OTG_CORE_ID_TypeDef coreID)
|
||||
{
|
||||
uint32_t i;
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
USB_OTG_SelectCore (pdev , coreID);
|
||||
|
||||
pdev->dev.device_status = USB_OTG_DEFAULT;
|
||||
pdev->dev.device_address = 0;
|
||||
|
||||
/* Init ep structure */
|
||||
for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[i];
|
||||
/* Init ep structure */
|
||||
ep->is_in = 1;
|
||||
ep->num = i;
|
||||
ep->tx_fifo_num = i;
|
||||
/* Control until ep is actvated */
|
||||
ep->type = EP_TYPE_CTRL;
|
||||
ep->maxpacket = USB_OTG_MAX_EP0_SIZE;
|
||||
ep->xfer_buff = 0;
|
||||
ep->xfer_len = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < pdev->cfg.dev_endpoints; i++)
|
||||
{
|
||||
ep = &pdev->dev.out_ep[i];
|
||||
/* Init ep structure */
|
||||
ep->is_in = 0;
|
||||
ep->num = i;
|
||||
ep->tx_fifo_num = i;
|
||||
/* Control until ep is activated */
|
||||
ep->type = EP_TYPE_CTRL;
|
||||
ep->maxpacket = USB_OTG_MAX_EP0_SIZE;
|
||||
ep->xfer_buff = 0;
|
||||
ep->xfer_len = 0;
|
||||
}
|
||||
|
||||
USB_OTG_DisableGlobalInt(pdev);
|
||||
|
||||
/*Init the Core (common init.) */
|
||||
USB_OTG_CoreInit(pdev);
|
||||
|
||||
|
||||
/* Force Device Mode*/
|
||||
USB_OTG_SetCurrentMode(pdev, DEVICE_MODE);
|
||||
|
||||
/* Init Device */
|
||||
USB_OTG_CoreInitDev(pdev);
|
||||
|
||||
|
||||
/* Enable USB Global interrupt */
|
||||
USB_OTG_EnableGlobalInt(pdev);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure an EP
|
||||
* @param pdev : Device instance
|
||||
* @param epdesc : Endpoint Descriptor
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t ep_addr,
|
||||
uint16_t ep_mps,
|
||||
uint8_t ep_type)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
if ((ep_addr & 0x80) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[ep_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[ep_addr & 0x7F];
|
||||
}
|
||||
ep->num = ep_addr & 0x7F;
|
||||
|
||||
ep->is_in = (0x80 & ep_addr) != 0;
|
||||
ep->maxpacket = ep_mps;
|
||||
ep->type = ep_type;
|
||||
if (ep->is_in)
|
||||
{
|
||||
/* Assign a Tx FIFO */
|
||||
ep->tx_fifo_num = ep->num;
|
||||
}
|
||||
/* Set initial data PID. */
|
||||
if (ep_type == USB_OTG_EP_BULK )
|
||||
{
|
||||
ep->data_pid_start = 0;
|
||||
}
|
||||
USB_OTG_EPActivate(pdev , ep );
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief called when an EP is disabled
|
||||
* @param pdev: device instance
|
||||
* @param ep_addr: endpoint address
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
if ((ep_addr&0x80) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[ep_addr & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[ep_addr & 0x7F];
|
||||
}
|
||||
ep->num = ep_addr & 0x7F;
|
||||
ep->is_in = (0x80 & ep_addr) != 0;
|
||||
USB_OTG_EPDeactivate(pdev , ep );
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DCD_EP_PrepareRx
|
||||
* @param pdev: device instance
|
||||
* @param ep_addr: endpoint address
|
||||
* @param pbuf: pointer to Rx buffer
|
||||
* @param buf_len: data length
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint16_t buf_len)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
ep = &pdev->dev.out_ep[ep_addr & 0x7F];
|
||||
|
||||
/*setup and start the Xfer */
|
||||
ep->xfer_buff = pbuf;
|
||||
ep->xfer_len = buf_len;
|
||||
ep->xfer_count = 0;
|
||||
ep->is_in = 0;
|
||||
ep->num = ep_addr & 0x7F;
|
||||
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
ep->dma_addr = (uint32_t)pbuf;
|
||||
}
|
||||
|
||||
if ( ep->num == 0 )
|
||||
{
|
||||
USB_OTG_EP0StartXfer(pdev , ep);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_OTG_EPStartXfer(pdev, ep );
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Transmit data over USB
|
||||
* @param pdev: device instance
|
||||
* @param ep_addr: endpoint address
|
||||
* @param pbuf: pointer to Tx buffer
|
||||
* @param buf_len: data length
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint32_t buf_len)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
ep = &pdev->dev.in_ep[ep_addr & 0x7F];
|
||||
|
||||
/* Setup and start the Transfer */
|
||||
ep->is_in = 1;
|
||||
ep->num = ep_addr & 0x7F;
|
||||
ep->xfer_buff = pbuf;
|
||||
ep->dma_addr = (uint32_t)pbuf;
|
||||
ep->xfer_count = 0;
|
||||
ep->xfer_len = buf_len;
|
||||
|
||||
if ( ep->num == 0 )
|
||||
{
|
||||
USB_OTG_EP0StartXfer(pdev , ep);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_OTG_EPStartXfer(pdev, ep );
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Stall an endpoint.
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint address
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
if ((0x80 & epnum) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[epnum & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[epnum];
|
||||
}
|
||||
|
||||
ep->is_stall = 1;
|
||||
ep->num = epnum & 0x7F;
|
||||
ep->is_in = ((epnum & 0x80) == 0x80);
|
||||
|
||||
USB_OTG_EPSetStall(pdev , ep);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear stall condition on endpoints.
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint address
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
if ((0x80 & epnum) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[epnum & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[epnum];
|
||||
}
|
||||
|
||||
ep->is_stall = 0;
|
||||
ep->num = epnum & 0x7F;
|
||||
ep->is_in = ((epnum & 0x80) == 0x80);
|
||||
|
||||
USB_OTG_EPClearStall(pdev , ep);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This Function flushes the FIFOs.
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint address
|
||||
* @retval : status
|
||||
*/
|
||||
uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
|
||||
{
|
||||
|
||||
if ((epnum & 0x80) == 0x80)
|
||||
{
|
||||
USB_OTG_FlushTxFifo(pdev, epnum & 0x7F);
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_OTG_FlushRxFifo(pdev);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This Function set USB device address
|
||||
* @param pdev: device instance
|
||||
* @param address: new device address
|
||||
* @retval : status
|
||||
*/
|
||||
void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address)
|
||||
{
|
||||
USB_OTG_DCFG_TypeDef dcfg;
|
||||
dcfg.d32 = 0;
|
||||
dcfg.b.devaddr = address;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Connect device (enable internal pull-up)
|
||||
* @param pdev: device instance
|
||||
* @retval : None
|
||||
*/
|
||||
void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
#ifndef USE_OTG_MODE
|
||||
USB_OTG_DCTL_TypeDef dctl;
|
||||
dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
|
||||
/* Connect device */
|
||||
dctl.b.sftdiscon = 0;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
|
||||
USB_OTG_BSP_mDelay(3);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disconnect device (disable internal pull-up)
|
||||
* @param pdev: device instance
|
||||
* @retval : None
|
||||
*/
|
||||
void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
#ifndef USE_OTG_MODE
|
||||
USB_OTG_DCTL_TypeDef dctl;
|
||||
dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
|
||||
/* Disconnect device for 3ms */
|
||||
dctl.b.sftdiscon = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32);
|
||||
USB_OTG_BSP_mDelay(3);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief returns the EP Status
|
||||
* @param pdev : Selected device
|
||||
* epnum : endpoint address
|
||||
* @retval : EP status
|
||||
*/
|
||||
|
||||
uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
uint32_t Status = 0;
|
||||
|
||||
if ((0x80 & epnum) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[epnum & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[epnum];
|
||||
}
|
||||
|
||||
Status = USB_OTG_GetEPStatus(pdev ,ep);
|
||||
|
||||
/* Return the current status */
|
||||
return Status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the EP Status
|
||||
* @param pdev : Selected device
|
||||
* Status : new Status
|
||||
* epnum : EP address
|
||||
* @retval : None
|
||||
*/
|
||||
void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
if ((0x80 & epnum) == 0x80)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[epnum & 0x7F];
|
||||
}
|
||||
else
|
||||
{
|
||||
ep = &pdev->dev.out_ep[epnum];
|
||||
}
|
||||
|
||||
USB_OTG_SetEPStatus(pdev ,ep , Status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,164 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_dcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Peripheral Driver Header file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __DCD_H__
|
||||
#define __DCD_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_core.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_EP_CONTROL 0
|
||||
#define USB_OTG_EP_ISOC 1
|
||||
#define USB_OTG_EP_BULK 2
|
||||
#define USB_OTG_EP_INT 3
|
||||
#define USB_OTG_EP_MASK 3
|
||||
|
||||
/* Device Status */
|
||||
#define USB_OTG_DEFAULT 1
|
||||
#define USB_OTG_ADDRESSED 2
|
||||
#define USB_OTG_CONFIGURED 3
|
||||
#define USB_OTG_SUSPENDED 4
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/********************************************************************************
|
||||
Data structure type
|
||||
********************************************************************************/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bEndpointAddress;
|
||||
uint8_t bmAttributes;
|
||||
uint16_t wMaxPacketSize;
|
||||
uint8_t bInterval;
|
||||
}
|
||||
EP_DESCRIPTOR , *PEP_DESCRIPTOR;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/********************************************************************************
|
||||
EXPORTED FUNCTION FROM THE USB-OTG LAYER
|
||||
********************************************************************************/
|
||||
void DCD_Init(USB_OTG_CORE_HANDLE *pdev ,
|
||||
USB_OTG_CORE_ID_TypeDef coreID);
|
||||
|
||||
void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev);
|
||||
void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev);
|
||||
void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t address);
|
||||
uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t ep_addr,
|
||||
uint16_t ep_mps,
|
||||
uint8_t ep_type);
|
||||
|
||||
uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr);
|
||||
|
||||
|
||||
uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint16_t buf_len);
|
||||
|
||||
uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t ep_addr,
|
||||
uint8_t *pbuf,
|
||||
uint32_t buf_len);
|
||||
uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t epnum);
|
||||
|
||||
void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t epnum ,
|
||||
uint32_t Status);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif //__DCD_H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,869 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_dcd_int.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Peripheral Device interrupt subroutines
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_dcd_int.h"
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT
|
||||
* @brief This file contains the interrupt subroutines for the Device mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/* static functions */
|
||||
static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum);
|
||||
|
||||
/* Interrupt Handlers */
|
||||
static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum);
|
||||
|
||||
static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
/**
|
||||
* @brief USBD_OTG_EP1OUT_ISR_Handler
|
||||
* handles all USB Interrupts
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
USB_OTG_DOEPINTn_TypeDef doepint;
|
||||
USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
|
||||
|
||||
doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT);
|
||||
doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK);
|
||||
|
||||
/* Transfer complete */
|
||||
if ( doepint.b.xfercompl )
|
||||
{
|
||||
/* Clear the bit in DOEPINTn for this interrupt */
|
||||
CLEAR_OUT_EP_INTR(1, xfercompl);
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ));
|
||||
/*ToDo : handle more than one single MPS size packet */
|
||||
pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \
|
||||
deptsiz.b.xfersize;
|
||||
}
|
||||
/* Inform upper layer: data ready */
|
||||
/* RX COMPLETE */
|
||||
USBD_DCD_INT_fops->DataOutStage(pdev , 1);
|
||||
|
||||
}
|
||||
|
||||
/* Endpoint disable */
|
||||
if ( doepint.b.epdisabled )
|
||||
{
|
||||
/* Clear the bit in DOEPINTn for this interrupt */
|
||||
CLEAR_OUT_EP_INTR(1, epdisabled);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_OTG_EP1IN_ISR_Handler
|
||||
* handles all USB Interrupts
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
USB_OTG_DIEPINTn_TypeDef diepint;
|
||||
uint32_t fifoemptymsk, msk, emp;
|
||||
|
||||
msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK);
|
||||
emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
|
||||
msk |= ((emp >> 1 ) & 0x1) << 7;
|
||||
diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk;
|
||||
|
||||
if ( diepint.b.xfercompl )
|
||||
{
|
||||
fifoemptymsk = 0x1 << 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
|
||||
CLEAR_IN_EP_INTR(1, xfercompl);
|
||||
/* TX COMPLETE */
|
||||
USBD_DCD_INT_fops->DataInStage(pdev , 1);
|
||||
}
|
||||
if ( diepint.b.epdisabled )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, epdisabled);
|
||||
}
|
||||
if ( diepint.b.timeout )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, timeout);
|
||||
}
|
||||
if (diepint.b.intktxfemp)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, intktxfemp);
|
||||
}
|
||||
if (diepint.b.inepnakeff)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(1, inepnakeff);
|
||||
}
|
||||
if (diepint.b.emptyintr)
|
||||
{
|
||||
DCD_WriteEmptyTxFifo(pdev , 1);
|
||||
CLEAR_IN_EP_INTR(1, emptyintr);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief STM32_USBF_OTG_ISR_Handler
|
||||
* handles all USB Interrupts
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintr_status;
|
||||
uint32_t retval = 0;
|
||||
|
||||
if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */
|
||||
{
|
||||
gintr_status.d32 = USB_OTG_ReadCoreItr(pdev);
|
||||
if (!gintr_status.d32) /* avoid spurious interrupt */
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (gintr_status.b.outepintr)
|
||||
{
|
||||
retval |= DCD_HandleOutEP_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.inepint)
|
||||
{
|
||||
retval |= DCD_HandleInEP_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.modemismatch)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.modemismatch = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
}
|
||||
|
||||
if (gintr_status.b.wkupintr)
|
||||
{
|
||||
retval |= DCD_HandleResume_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.usbsuspend)
|
||||
{
|
||||
retval |= DCD_HandleUSBSuspend_ISR(pdev);
|
||||
}
|
||||
if (gintr_status.b.sofintr)
|
||||
{
|
||||
retval |= DCD_HandleSof_ISR(pdev);
|
||||
|
||||
}
|
||||
|
||||
if (gintr_status.b.rxstsqlvl)
|
||||
{
|
||||
retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev);
|
||||
|
||||
}
|
||||
|
||||
if (gintr_status.b.usbreset)
|
||||
{
|
||||
retval |= DCD_HandleUsbReset_ISR(pdev);
|
||||
|
||||
}
|
||||
if (gintr_status.b.enumdone)
|
||||
{
|
||||
retval |= DCD_HandleEnumDone_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.incomplisoin)
|
||||
{
|
||||
retval |= DCD_IsoINIncomplete_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.incomplisoout)
|
||||
{
|
||||
retval |= DCD_IsoOUTIncomplete_ISR(pdev);
|
||||
}
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
if (gintr_status.b.sessreqintr)
|
||||
{
|
||||
retval |= DCD_SessionRequest_ISR(pdev);
|
||||
}
|
||||
|
||||
if (gintr_status.b.otgintr)
|
||||
{
|
||||
retval |= DCD_OTG_ISR(pdev);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
/**
|
||||
* @brief DCD_SessionRequest_ISR
|
||||
* Indicates that the USB_OTG controller has detected a connection
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USBD_DCD_INT_fops->DevConnected (pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.sessreqintr = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_OTG_ISR
|
||||
* Indicates that the USB_OTG controller has detected an OTG event:
|
||||
* used to detect the end of session i.e. disconnection
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
USB_OTG_GOTGINT_TypeDef gotgint;
|
||||
|
||||
gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
|
||||
|
||||
if (gotgint.b.sesenddet)
|
||||
{
|
||||
USBD_DCD_INT_fops->DevDisconnected (pdev);
|
||||
}
|
||||
/* Clear OTG interrupt */
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* @brief DCD_HandleResume_ISR
|
||||
* Indicates that the USB_OTG controller has detected a resume or
|
||||
* remote Wake-up sequence
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_DCTL_TypeDef devctl;
|
||||
USB_OTG_PCGCCTL_TypeDef power;
|
||||
|
||||
if(pdev->cfg.low_power)
|
||||
{
|
||||
/* un-gate USB Core clock */
|
||||
power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL);
|
||||
power.b.gatehclk = 0;
|
||||
power.b.stoppclk = 0;
|
||||
USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32);
|
||||
}
|
||||
|
||||
/* Clear the Remote Wake-up Signaling */
|
||||
devctl.d32 = 0;
|
||||
devctl.b.rmtwkupsig = 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0);
|
||||
|
||||
/* Inform upper layer by the Resume Event */
|
||||
USBD_DCD_INT_fops->Resume (pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.wkupintr = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_HandleUSBSuspend_ISR
|
||||
* Indicates that SUSPEND state has been detected on the USB
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_PCGCCTL_TypeDef power;
|
||||
USB_OTG_DSTS_TypeDef dsts;
|
||||
__IO uint8_t prev_status = 0;
|
||||
|
||||
prev_status = pdev->dev.device_status;
|
||||
USBD_DCD_INT_fops->Suspend (pdev);
|
||||
|
||||
dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.usbsuspend = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
if((pdev->cfg.low_power) && (dsts.b.suspsts == 1) &&
|
||||
(pdev->dev.connection_status == 1) &&
|
||||
(prev_status == USB_OTG_CONFIGURED))
|
||||
{
|
||||
/* switch-off the clocks */
|
||||
power.d32 = 0;
|
||||
power.b.stoppclk = 1;
|
||||
USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
|
||||
|
||||
power.b.gatehclk = 1;
|
||||
USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32);
|
||||
|
||||
/* Request to enter Sleep mode after exit from current ISR */
|
||||
SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk);
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleInEP_ISR
|
||||
* Indicates that an IN EP has a pending Interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_DIEPINTn_TypeDef diepint;
|
||||
|
||||
uint32_t ep_intr;
|
||||
uint32_t epnum = 0;
|
||||
uint32_t fifoemptymsk;
|
||||
diepint.d32 = 0;
|
||||
ep_intr = USB_OTG_ReadDevAllInEPItr(pdev);
|
||||
|
||||
while ( ep_intr )
|
||||
{
|
||||
if (ep_intr&0x1) /* In ITR */
|
||||
{
|
||||
diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */
|
||||
if ( diepint.b.xfercompl )
|
||||
{
|
||||
fifoemptymsk = 0x1 << epnum;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0);
|
||||
CLEAR_IN_EP_INTR(epnum, xfercompl);
|
||||
/* TX COMPLETE */
|
||||
USBD_DCD_INT_fops->DataInStage(pdev , epnum);
|
||||
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN))
|
||||
{
|
||||
/* prepare to rx more setup packets */
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
}
|
||||
}
|
||||
}
|
||||
if ( diepint.b.timeout )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, timeout);
|
||||
}
|
||||
if (diepint.b.intktxfemp)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, intktxfemp);
|
||||
}
|
||||
if (diepint.b.inepnakeff)
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, inepnakeff);
|
||||
}
|
||||
if ( diepint.b.epdisabled )
|
||||
{
|
||||
CLEAR_IN_EP_INTR(epnum, epdisabled);
|
||||
}
|
||||
if (diepint.b.emptyintr)
|
||||
{
|
||||
|
||||
DCD_WriteEmptyTxFifo(pdev , epnum);
|
||||
|
||||
CLEAR_IN_EP_INTR(epnum, emptyintr);
|
||||
}
|
||||
}
|
||||
epnum++;
|
||||
ep_intr >>= 1;
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleOutEP_ISR
|
||||
* Indicates that an OUT EP has a pending Interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
uint32_t ep_intr;
|
||||
USB_OTG_DOEPINTn_TypeDef doepint;
|
||||
USB_OTG_DEPXFRSIZ_TypeDef deptsiz;
|
||||
uint32_t epnum = 0;
|
||||
|
||||
doepint.d32 = 0;
|
||||
|
||||
/* Read in the device interrupt bits */
|
||||
ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev);
|
||||
|
||||
while ( ep_intr )
|
||||
{
|
||||
if (ep_intr&0x1)
|
||||
{
|
||||
|
||||
doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum);
|
||||
|
||||
/* Transfer complete */
|
||||
if ( doepint.b.xfercompl )
|
||||
{
|
||||
/* Clear the bit in DOEPINTn for this interrupt */
|
||||
CLEAR_OUT_EP_INTR(epnum, xfercompl);
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ));
|
||||
/*ToDo : handle more than one single MPS size packet */
|
||||
pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \
|
||||
deptsiz.b.xfersize;
|
||||
}
|
||||
/* Inform upper layer: data ready */
|
||||
/* RX COMPLETE */
|
||||
USBD_DCD_INT_fops->DataOutStage(pdev , epnum);
|
||||
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT))
|
||||
{
|
||||
/* prepare to rx more setup packets */
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Endpoint disable */
|
||||
if ( doepint.b.epdisabled )
|
||||
{
|
||||
/* Clear the bit in DOEPINTn for this interrupt */
|
||||
CLEAR_OUT_EP_INTR(epnum, epdisabled);
|
||||
}
|
||||
/* Setup Phase Done (control EPs) */
|
||||
if ( doepint.b.setup )
|
||||
{
|
||||
|
||||
/* inform the upper layer that a setup packet is available */
|
||||
/* SETUP COMPLETE */
|
||||
USBD_DCD_INT_fops->SetupStage(pdev);
|
||||
CLEAR_OUT_EP_INTR(epnum, setup);
|
||||
}
|
||||
}
|
||||
epnum++;
|
||||
ep_intr >>= 1;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleSof_ISR
|
||||
* Handles the SOF Interrupts
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef GINTSTS;
|
||||
|
||||
|
||||
USBD_DCD_INT_fops->SOF(pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
GINTSTS.d32 = 0;
|
||||
GINTSTS.b.sofintr = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleRxStatusQueueLevel_ISR
|
||||
* Handles the Rx Status Queue Level Interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTMSK_TypeDef int_mask;
|
||||
USB_OTG_DRXSTS_TypeDef status;
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
/* Disable the Rx Status Queue Level interrupt */
|
||||
int_mask.d32 = 0;
|
||||
int_mask.b.rxstsqlvl = 1;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0);
|
||||
|
||||
/* Get the Status from the top of the FIFO */
|
||||
status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP );
|
||||
|
||||
ep = &pdev->dev.out_ep[status.b.epnum];
|
||||
|
||||
switch (status.b.pktsts)
|
||||
{
|
||||
case STS_GOUT_NAK:
|
||||
break;
|
||||
case STS_DATA_UPDT:
|
||||
if (status.b.bcnt)
|
||||
{
|
||||
USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt);
|
||||
ep->xfer_buff += status.b.bcnt;
|
||||
ep->xfer_count += status.b.bcnt;
|
||||
}
|
||||
break;
|
||||
case STS_XFER_COMP:
|
||||
break;
|
||||
case STS_SETUP_COMP:
|
||||
break;
|
||||
case STS_SETUP_UPDT:
|
||||
/* Copy the setup packet received in FIFO into the setup buffer in RAM */
|
||||
USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8);
|
||||
ep->xfer_count += status.b.bcnt;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the Rx Status Queue Level interrupt */
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_WriteEmptyTxFifo
|
||||
* check FIFO for the next packet to be loaded
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum)
|
||||
{
|
||||
USB_OTG_DTXFSTSn_TypeDef txstatus;
|
||||
USB_OTG_EP *ep;
|
||||
uint32_t len = 0;
|
||||
uint32_t len32b;
|
||||
txstatus.d32 = 0;
|
||||
|
||||
ep = &pdev->dev.in_ep[epnum];
|
||||
|
||||
len = ep->xfer_len - ep->xfer_count;
|
||||
|
||||
if (len > ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
}
|
||||
|
||||
len32b = (len + 3) / 4;
|
||||
txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
||||
|
||||
|
||||
|
||||
while (txstatus.b.txfspcavail > len32b &&
|
||||
ep->xfer_count < ep->xfer_len &&
|
||||
ep->xfer_len != 0)
|
||||
{
|
||||
/* Write the FIFO */
|
||||
len = ep->xfer_len - ep->xfer_count;
|
||||
|
||||
if (len > ep->maxpacket)
|
||||
{
|
||||
len = ep->maxpacket;
|
||||
}
|
||||
len32b = (len + 3) / 4;
|
||||
|
||||
USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len);
|
||||
|
||||
ep->xfer_buff += len;
|
||||
ep->xfer_count += len;
|
||||
|
||||
txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleUsbReset_ISR
|
||||
* This interrupt occurs when a USB Reset is detected
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_DAINT_TypeDef daintmsk;
|
||||
USB_OTG_DOEPMSK_TypeDef doepmsk;
|
||||
USB_OTG_DIEPMSK_TypeDef diepmsk;
|
||||
USB_OTG_DCFG_TypeDef dcfg;
|
||||
USB_OTG_DCTL_TypeDef dctl;
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
uint32_t i;
|
||||
|
||||
dctl.d32 = 0;
|
||||
daintmsk.d32 = 0;
|
||||
doepmsk.d32 = 0;
|
||||
diepmsk.d32 = 0;
|
||||
dcfg.d32 = 0;
|
||||
gintsts.d32 = 0;
|
||||
|
||||
/* Clear the Remote Wake-up Signaling */
|
||||
dctl.b.rmtwkupsig = 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 );
|
||||
|
||||
/* Flush the Tx FIFO */
|
||||
USB_OTG_FlushTxFifo(pdev , 0 );
|
||||
|
||||
for (i = 0; i < pdev->cfg.dev_endpoints ; i++)
|
||||
{
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF);
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF);
|
||||
}
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF );
|
||||
|
||||
daintmsk.ep.in = 1;
|
||||
daintmsk.ep.out = 1;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 );
|
||||
|
||||
doepmsk.b.setup = 1;
|
||||
doepmsk.b.xfercompl = 1;
|
||||
doepmsk.b.epdisabled = 1;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 );
|
||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 );
|
||||
#endif
|
||||
diepmsk.b.xfercompl = 1;
|
||||
diepmsk.b.timeout = 1;
|
||||
diepmsk.b.epdisabled = 1;
|
||||
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 );
|
||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 );
|
||||
#endif
|
||||
/* Reset Device Address */
|
||||
dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG);
|
||||
dcfg.b.devaddr = 0;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32);
|
||||
|
||||
|
||||
/* setup EP0 to receive SETUP packets */
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.usbreset = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
/*Reset internal state machine */
|
||||
USBD_DCD_INT_fops->Reset(pdev);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_HandleEnumDone_ISR
|
||||
* Read the device status register and set the device speed
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_GUSBCFG_TypeDef gusbcfg;
|
||||
|
||||
USB_OTG_EP0Activate(pdev);
|
||||
|
||||
/* Set USB turn-around time based on device speed and PHY interface. */
|
||||
gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);
|
||||
|
||||
/* Full or High speed */
|
||||
if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH)
|
||||
{
|
||||
pdev->cfg.speed = USB_OTG_SPEED_HIGH;
|
||||
pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ;
|
||||
gusbcfg.b.usbtrdtim = 9;
|
||||
}
|
||||
else
|
||||
{
|
||||
pdev->cfg.speed = USB_OTG_SPEED_FULL;
|
||||
pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ;
|
||||
gusbcfg.b.usbtrdtim = 5;
|
||||
}
|
||||
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.enumdone = 1;
|
||||
USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 );
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DCD_IsoINIncomplete_ISR
|
||||
* handle the ISO IN incomplete interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
gintsts.d32 = 0;
|
||||
|
||||
USBD_DCD_INT_fops->IsoINIncomplete (pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.b.incomplisoin = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DCD_IsoOUTIncomplete_ISR
|
||||
* handle the ISO OUT incomplete interrupt
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
gintsts.d32 = 0;
|
||||
|
||||
USBD_DCD_INT_fops->IsoOUTIncomplete (pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.b.incomplisoout = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
return 1;
|
||||
}
|
||||
/**
|
||||
* @brief DCD_ReadDevInEP
|
||||
* Reads ep flags
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
||||
{
|
||||
uint32_t v, msk, emp;
|
||||
msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK);
|
||||
emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK);
|
||||
msk |= ((emp >> epnum) & 0x1) << 7;
|
||||
v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk;
|
||||
return v;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_dcd_int.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Peripheral Device Interface Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef USB_DCD_INT_H__
|
||||
#define USB_DCD_INT_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_dcd.h"
|
||||
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct _USBD_DCD_INT
|
||||
{
|
||||
uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
|
||||
uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
|
||||
uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
}USBD_DCD_INT_cb_TypeDef;
|
||||
|
||||
extern USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CLEAR_IN_EP_INTR(epnum,intr) \
|
||||
diepint.d32=0; \
|
||||
diepint.b.intr = 1; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32);
|
||||
|
||||
#define CLEAR_OUT_EP_INTR(epnum,intr) \
|
||||
doepint.d32=0; \
|
||||
doepint.b.intr = 1; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT,doepint.d32);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif // USB_DCD_INT_H__
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_defines.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Header of the Core Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_DEF_H__
|
||||
#define __USB_DEF_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DEFINES
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup _CORE_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_OTG_SPEED_PARAM_HIGH 0
|
||||
#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1
|
||||
#define USB_OTG_SPEED_PARAM_FULL 3
|
||||
|
||||
#define USB_OTG_SPEED_HIGH 0
|
||||
#define USB_OTG_SPEED_FULL 1
|
||||
|
||||
#define USB_OTG_ULPI_PHY 1
|
||||
#define USB_OTG_EMBEDDED_PHY 2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup _GLOBAL_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
|
||||
#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
|
||||
#define GAHBCFG_GLBINT_ENABLE 1
|
||||
#define GAHBCFG_INT_DMA_BURST_SINGLE 0
|
||||
#define GAHBCFG_INT_DMA_BURST_INCR 1
|
||||
#define GAHBCFG_INT_DMA_BURST_INCR4 3
|
||||
#define GAHBCFG_INT_DMA_BURST_INCR8 5
|
||||
#define GAHBCFG_INT_DMA_BURST_INCR16 7
|
||||
#define GAHBCFG_DMAENABLE 1
|
||||
#define GAHBCFG_TXFEMPTYLVL_EMPTY 1
|
||||
#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
|
||||
#define GRXSTS_PKTSTS_IN 2
|
||||
#define GRXSTS_PKTSTS_IN_XFER_COMP 3
|
||||
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5
|
||||
#define GRXSTS_PKTSTS_CH_HALTED 7
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup _OnTheGo_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
#define MODE_HNP_SRP_CAPABLE 0
|
||||
#define MODE_SRP_ONLY_CAPABLE 1
|
||||
#define MODE_NO_HNP_SRP_CAPABLE 2
|
||||
#define MODE_SRP_CAPABLE_DEVICE 3
|
||||
#define MODE_NO_SRP_CAPABLE_DEVICE 4
|
||||
#define MODE_SRP_CAPABLE_HOST 5
|
||||
#define MODE_NO_SRP_CAPABLE_HOST 6
|
||||
#define A_HOST 1
|
||||
#define A_SUSPEND 2
|
||||
#define A_PERIPHERAL 3
|
||||
#define B_PERIPHERAL 4
|
||||
#define B_HOST 5
|
||||
#define DEVICE_MODE 0
|
||||
#define HOST_MODE 1
|
||||
#define OTG_MODE 2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup __DEVICE_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
|
||||
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
|
||||
#define DSTS_ENUMSPD_LS_PHY_6MHZ 2
|
||||
#define DSTS_ENUMSPD_FS_PHY_48MHZ 3
|
||||
|
||||
#define DCFG_FRAME_INTERVAL_80 0
|
||||
#define DCFG_FRAME_INTERVAL_85 1
|
||||
#define DCFG_FRAME_INTERVAL_90 2
|
||||
#define DCFG_FRAME_INTERVAL_95 3
|
||||
|
||||
#define DEP0CTL_MPS_64 0
|
||||
#define DEP0CTL_MPS_32 1
|
||||
#define DEP0CTL_MPS_16 2
|
||||
#define DEP0CTL_MPS_8 3
|
||||
|
||||
#define EP_SPEED_LOW 0
|
||||
#define EP_SPEED_FULL 1
|
||||
#define EP_SPEED_HIGH 2
|
||||
|
||||
#define EP_TYPE_CTRL 0
|
||||
#define EP_TYPE_ISOC 1
|
||||
#define EP_TYPE_BULK 2
|
||||
#define EP_TYPE_INTR 3
|
||||
#define EP_TYPE_MSK 3
|
||||
|
||||
#define STS_GOUT_NAK 1
|
||||
#define STS_DATA_UPDT 2
|
||||
#define STS_XFER_COMP 3
|
||||
#define STS_SETUP_COMP 4
|
||||
#define STS_SETUP_UPDT 6
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup __HOST_DEFINES_
|
||||
* @{
|
||||
*/
|
||||
#define HC_PID_DATA0 0
|
||||
#define HC_PID_DATA2 1
|
||||
#define HC_PID_DATA1 2
|
||||
#define HC_PID_SETUP 3
|
||||
|
||||
#define HPRT0_PRTSPD_HIGH_SPEED 0
|
||||
#define HPRT0_PRTSPD_FULL_SPEED 1
|
||||
#define HPRT0_PRTSPD_LOW_SPEED 2
|
||||
|
||||
#define HCFG_30_60_MHZ 0
|
||||
#define HCFG_48_MHZ 1
|
||||
#define HCFG_6_MHZ 2
|
||||
|
||||
#define HCCHAR_CTRL 0
|
||||
#define HCCHAR_ISOC 1
|
||||
#define HCCHAR_BULK 2
|
||||
#define HCCHAR_INTR 3
|
||||
|
||||
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
USB_OTG_HS_CORE_ID = 0,
|
||||
USB_OTG_FS_CORE_ID = 1
|
||||
}USB_OTG_CORE_ID_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DEFINES_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup Internal_Macro's
|
||||
* @{
|
||||
*/
|
||||
#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)reg)
|
||||
#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value)
|
||||
#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \
|
||||
USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) )
|
||||
|
||||
/********************************************************************************
|
||||
ENUMERATION TYPE
|
||||
********************************************************************************/
|
||||
enum USB_OTG_SPEED {
|
||||
USB_SPEED_UNKNOWN = 0,
|
||||
USB_SPEED_LOW,
|
||||
USB_SPEED_FULL,
|
||||
USB_SPEED_HIGH
|
||||
};
|
||||
|
||||
#endif //__USB_DEFINES__H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,262 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_hcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Host Interface Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_core.h"
|
||||
#include "usb_hcd.h"
|
||||
#include "usb_conf.h"
|
||||
#include "usb_bsp.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD
|
||||
* @brief This file is the interface between EFSL ans Host mass-storage class
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HCD_Init
|
||||
* Initialize the HOST portion of the driver.
|
||||
* @param pdev: Selected device
|
||||
* @param base_address: OTG base address
|
||||
* @retval Status
|
||||
*/
|
||||
uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev ,
|
||||
USB_OTG_CORE_ID_TypeDef coreID)
|
||||
{
|
||||
uint8_t i = 0;
|
||||
pdev->host.ConnSts = 0;
|
||||
|
||||
for (i= 0; i< USB_OTG_MAX_TX_FIFOS; i++)
|
||||
{
|
||||
pdev->host.ErrCnt[i] = 0;
|
||||
pdev->host.XferCnt[i] = 0;
|
||||
pdev->host.HC_Status[i] = HC_IDLE;
|
||||
}
|
||||
pdev->host.hc[0].max_packet = 8;
|
||||
|
||||
USB_OTG_SelectCore(pdev, coreID);
|
||||
#ifndef DUAL_ROLE_MODE_ENABLED
|
||||
USB_OTG_DisableGlobalInt(pdev);
|
||||
USB_OTG_CoreInit(pdev);
|
||||
|
||||
/* Force Host Mode*/
|
||||
USB_OTG_SetCurrentMode(pdev , HOST_MODE);
|
||||
USB_OTG_CoreInitHost(pdev);
|
||||
USB_OTG_EnableGlobalInt(pdev);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief HCD_GetCurrentSpeed
|
||||
* Get Current device Speed.
|
||||
* @param pdev : Selected device
|
||||
* @retval Status
|
||||
*/
|
||||
|
||||
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_HPRT0_TypeDef HPRT0;
|
||||
HPRT0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
|
||||
|
||||
return HPRT0.b.prtspd;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_ResetPort
|
||||
* Issues the reset command to device
|
||||
* @param pdev : Selected device
|
||||
* @retval Status
|
||||
*/
|
||||
uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
/*
|
||||
Before starting to drive a USB reset, the application waits for the OTG
|
||||
interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT),
|
||||
which indicates that the bus is stable again after the electrical debounce
|
||||
caused by the attachment of a pull-up resistor on DP (FS) or DM (LS).
|
||||
*/
|
||||
|
||||
USB_OTG_ResetPort(pdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_IsDeviceConnected
|
||||
* Check if the device is connected.
|
||||
* @param pdev : Selected device
|
||||
* @retval Device connection status. 1 -> connected and 0 -> disconnected
|
||||
*
|
||||
*/
|
||||
uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
return (pdev->host.ConnSts);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_GetCurrentFrame
|
||||
* This function returns the frame number for sof packet
|
||||
* @param pdev : Selected device
|
||||
* @retval Frame number
|
||||
*
|
||||
*/
|
||||
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
return (USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0xFFFF) ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_GetURB_State
|
||||
* This function returns the last URBstate
|
||||
* @param pdev: Selected device
|
||||
* @retval URB_STATE
|
||||
*
|
||||
*/
|
||||
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num)
|
||||
{
|
||||
return pdev->host.URB_State[ch_num] ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_GetXferCnt
|
||||
* This function returns the last URBstate
|
||||
* @param pdev: Selected device
|
||||
* @retval No. of data bytes transferred
|
||||
*
|
||||
*/
|
||||
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num)
|
||||
{
|
||||
return pdev->host.XferCnt[ch_num] ;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief HCD_GetHCState
|
||||
* This function returns the HC Status
|
||||
* @param pdev: Selected device
|
||||
* @retval HC_STATUS
|
||||
*
|
||||
*/
|
||||
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num)
|
||||
{
|
||||
return pdev->host.HC_Status[ch_num] ;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_HC_Init
|
||||
* This function prepare a HC and start a transfer
|
||||
* @param pdev: Selected device
|
||||
* @param hc_num: Channel number
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
|
||||
{
|
||||
return USB_OTG_HC_Init(pdev, hc_num);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief HCD_SubmitRequest
|
||||
* This function prepare a HC and start a transfer
|
||||
* @param pdev: Selected device
|
||||
* @param hc_num: Channel number
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num)
|
||||
{
|
||||
|
||||
pdev->host.URB_State[hc_num] = URB_IDLE;
|
||||
pdev->host.hc[hc_num].xfer_count = 0 ;
|
||||
return USB_OTG_HC_StartXfer(pdev, hc_num);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_hcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Host layer Header file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_HCD_H__
|
||||
#define __USB_HCD_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_regs.h"
|
||||
#include "usb_core.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev ,
|
||||
USB_OTG_CORE_ID_TypeDef coreID);
|
||||
uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t hc_num);
|
||||
uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t hc_num) ;
|
||||
uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ;
|
||||
URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
|
||||
uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num);
|
||||
HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif //__USB_HCD_H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,858 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_hcd_int.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Host driver interrupt subroutines
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_core.h"
|
||||
#include "usb_defines.h"
|
||||
#include "usb_hcd_int.h"
|
||||
|
||||
#if defined (__CC_ARM) /*!< ARM Compiler */
|
||||
#pragma O0
|
||||
#elif defined (__GNUC__) /*!< GNU Compiler */
|
||||
#pragma GCC optimize ("O0")
|
||||
#elif defined (__TASKING__) /*!< TASKING Compiler */
|
||||
#pragma optimize=0
|
||||
|
||||
#endif /* __CC_ARM */
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_INT
|
||||
* @brief This file contains the interrupt subroutines for the Host mode.
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint32_t num);
|
||||
static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint32_t num);
|
||||
static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief HOST_Handle_ISR
|
||||
* This function handles all USB Host Interrupts
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
uint32_t retval = 0;
|
||||
|
||||
gintsts.d32 = 0;
|
||||
|
||||
/* Check if HOST Mode */
|
||||
if (USB_OTG_IsHostMode(pdev))
|
||||
{
|
||||
gintsts.d32 = USB_OTG_ReadCoreItr(pdev);
|
||||
if (!gintsts.d32)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (gintsts.b.sofintr)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_sof_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.rxstsqlvl)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.nptxfempty)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.ptxfempty)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.hcintr)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_hc_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.portintr)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_port_ISR (pdev);
|
||||
}
|
||||
|
||||
if (gintsts.b.disconnect)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev);
|
||||
|
||||
}
|
||||
|
||||
if (gintsts.b.incomplisoout)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (pdev);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_hc_ISR
|
||||
* This function indicates that one or more host channels has a pending
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_HAINT_TypeDef haint;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
uint32_t i = 0;
|
||||
uint32_t retval = 0;
|
||||
|
||||
/* Clear appropriate bits in HCINTn to clear the interrupt bit in
|
||||
* GINTSTS */
|
||||
|
||||
haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev);
|
||||
|
||||
for (i = 0; i < pdev->cfg.host_channels ; i++)
|
||||
{
|
||||
if (haint.b.chint & (1 << i))
|
||||
{
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR);
|
||||
|
||||
if (hcchar.b.epdir)
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i);
|
||||
}
|
||||
else
|
||||
{
|
||||
retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_otg_hcd_handle_sof_intr
|
||||
* Handles the start-of-frame interrupt in host mode.
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
gintsts.d32 = 0;
|
||||
|
||||
USBH_HCD_INT_fops->SOF(pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.b.sofintr = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_Disconnect_ISR
|
||||
* Handles disconnect event.
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
gintsts.d32 = 0;
|
||||
|
||||
USBH_HCD_INT_fops->DevDisconnected(pdev);
|
||||
|
||||
/* Clear interrupt */
|
||||
gintsts.b.disconnect = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma optimize = none
|
||||
#endif /* __CC_ARM */
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_nptxfempty_ISR
|
||||
* Handles non periodic tx fifo empty.
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTMSK_TypeDef intmsk;
|
||||
USB_OTG_HNPTXSTS_TypeDef hnptxsts;
|
||||
uint16_t len_words , len;
|
||||
|
||||
hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
|
||||
|
||||
len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4;
|
||||
|
||||
while ((hnptxsts.b.nptxfspcavail > len_words)&&
|
||||
(pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len != 0))
|
||||
{
|
||||
|
||||
len = hnptxsts.b.nptxfspcavail * 4;
|
||||
|
||||
if (len > pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len)
|
||||
{
|
||||
/* Last packet */
|
||||
len = pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len;
|
||||
|
||||
intmsk.d32 = 0;
|
||||
intmsk.b.nptxfempty = 1;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
|
||||
}
|
||||
|
||||
len_words = (pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len + 3) / 4;
|
||||
|
||||
USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff, hnptxsts.b.nptxqtop.chnum, len);
|
||||
|
||||
pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_buff += len;
|
||||
pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_len -= len;
|
||||
pdev->host.hc[hnptxsts.b.nptxqtop.chnum].xfer_count += len;
|
||||
|
||||
hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma optimize = none
|
||||
#endif /* __CC_ARM */
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_ptxfempty_ISR
|
||||
* Handles periodic tx fifo empty
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTMSK_TypeDef intmsk;
|
||||
USB_OTG_HPTXSTS_TypeDef hptxsts;
|
||||
uint16_t len_words , len;
|
||||
|
||||
hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
|
||||
|
||||
len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4;
|
||||
|
||||
while ((hptxsts.b.ptxfspcavail > len_words)&&
|
||||
(pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len != 0))
|
||||
{
|
||||
|
||||
len = hptxsts.b.ptxfspcavail * 4;
|
||||
|
||||
if (len > pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len)
|
||||
{
|
||||
len = pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len;
|
||||
/* Last packet */
|
||||
intmsk.d32 = 0;
|
||||
intmsk.b.ptxfempty = 1;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
|
||||
}
|
||||
|
||||
len_words = (pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len + 3) / 4;
|
||||
|
||||
USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff, hptxsts.b.ptxqtop.chnum, len);
|
||||
|
||||
pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_buff += len;
|
||||
pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_len -= len;
|
||||
pdev->host.hc[hptxsts.b.ptxqtop.chnum].xfer_count += len;
|
||||
|
||||
hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS);
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_port_ISR
|
||||
* This function determines which interrupt conditions have occurred
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma optimize = none
|
||||
#endif /* __CC_ARM */
|
||||
static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_HPRT0_TypeDef hprt0;
|
||||
USB_OTG_HPRT0_TypeDef hprt0_dup;
|
||||
USB_OTG_HCFG_TypeDef hcfg;
|
||||
uint32_t do_reset = 0;
|
||||
uint32_t retval = 0;
|
||||
|
||||
hcfg.d32 = 0;
|
||||
hprt0.d32 = 0;
|
||||
hprt0_dup.d32 = 0;
|
||||
|
||||
hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
|
||||
hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0);
|
||||
|
||||
/* Clear the interrupt bits in GINTSTS */
|
||||
|
||||
hprt0_dup.b.prtena = 0;
|
||||
hprt0_dup.b.prtconndet = 0;
|
||||
hprt0_dup.b.prtenchng = 0;
|
||||
hprt0_dup.b.prtovrcurrchng = 0;
|
||||
|
||||
/* Port Connect Detected */
|
||||
if (hprt0.b.prtconndet)
|
||||
{
|
||||
|
||||
hprt0_dup.b.prtconndet = 1;
|
||||
USBH_HCD_INT_fops->DevConnected(pdev);
|
||||
retval |= 1;
|
||||
}
|
||||
|
||||
/* Port Enable Changed */
|
||||
if (hprt0.b.prtenchng)
|
||||
{
|
||||
hprt0_dup.b.prtenchng = 1;
|
||||
|
||||
if (hprt0.b.prtena == 1)
|
||||
{
|
||||
|
||||
USBH_HCD_INT_fops->DevConnected(pdev);
|
||||
|
||||
if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) ||
|
||||
(hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED))
|
||||
{
|
||||
|
||||
hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG);
|
||||
|
||||
if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED)
|
||||
{
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 );
|
||||
if (hcfg.b.fslspclksel != HCFG_6_MHZ)
|
||||
{
|
||||
if(pdev->cfg.phy_itface == USB_OTG_EMBEDDED_PHY)
|
||||
{
|
||||
USB_OTG_InitFSLSPClkSel(pdev ,HCFG_6_MHZ );
|
||||
}
|
||||
do_reset = 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 );
|
||||
if (hcfg.b.fslspclksel != HCFG_48_MHZ)
|
||||
{
|
||||
USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ );
|
||||
do_reset = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
do_reset = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Overcurrent Change Interrupt */
|
||||
if (hprt0.b.prtovrcurrchng)
|
||||
{
|
||||
hprt0_dup.b.prtovrcurrchng = 1;
|
||||
retval |= 1;
|
||||
}
|
||||
if (do_reset)
|
||||
{
|
||||
USB_OTG_ResetPort(pdev);
|
||||
}
|
||||
/* Clear Port Interrupts */
|
||||
USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32);
|
||||
|
||||
return retval;
|
||||
}
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma optimize = none
|
||||
#endif /* __CC_ARM */
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_hc_n_Out_ISR
|
||||
* Handles interrupt for a specific Host Channel
|
||||
* @param pdev: Selected device
|
||||
* @param hc_num: Channel number
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
|
||||
{
|
||||
|
||||
USB_OTG_HCINTn_TypeDef hcint;
|
||||
USB_OTG_HCINTMSK_TypeDef hcintmsk;
|
||||
USB_OTG_HC_REGS *hcreg;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
|
||||
hcreg = pdev->regs.HC_REGS[num];
|
||||
hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
|
||||
hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK);
|
||||
hcint.d32 = hcint.d32 & hcintmsk.d32;
|
||||
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
|
||||
|
||||
if (hcint.b.ahberr)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg ,ahberr);
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
}
|
||||
else if (hcint.b.ack)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg , ack);
|
||||
}
|
||||
else if (hcint.b.frmovrun)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg ,frmovrun);
|
||||
}
|
||||
else if (hcint.b.xfercompl)
|
||||
{
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , xfercompl);
|
||||
pdev->host.HC_Status[num] = HC_XFRC;
|
||||
}
|
||||
|
||||
else if (hcint.b.stall)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg , stall);
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
pdev->host.HC_Status[num] = HC_STALL;
|
||||
}
|
||||
|
||||
else if (hcint.b.nak)
|
||||
{
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
pdev->host.HC_Status[num] = HC_NAK;
|
||||
}
|
||||
|
||||
else if (hcint.b.xacterr)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
pdev->host.ErrCnt[num] ++;
|
||||
pdev->host.HC_Status[num] = HC_XACTERR;
|
||||
CLEAR_HC_INT(hcreg , xacterr);
|
||||
}
|
||||
else if (hcint.b.nyet)
|
||||
{
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nyet);
|
||||
pdev->host.HC_Status[num] = HC_NYET;
|
||||
}
|
||||
else if (hcint.b.datatglerr)
|
||||
{
|
||||
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
pdev->host.HC_Status[num] = HC_DATATGLERR;
|
||||
|
||||
CLEAR_HC_INT(hcreg , datatglerr);
|
||||
}
|
||||
else if (hcint.b.chhltd)
|
||||
{
|
||||
MASK_HOST_INT_CHH (num);
|
||||
|
||||
if(pdev->host.HC_Status[num] == HC_XFRC)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_DONE;
|
||||
|
||||
if (hcchar.b.eptype == EP_TYPE_BULK)
|
||||
{
|
||||
pdev->host.hc[num].toggle_out ^= 1;
|
||||
}
|
||||
}
|
||||
else if(pdev->host.HC_Status[num] == HC_NAK)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_NOTREADY;
|
||||
}
|
||||
else if(pdev->host.HC_Status[num] == HC_NYET)
|
||||
{
|
||||
if(pdev->host.hc[num].do_ping == 1)
|
||||
{
|
||||
USB_OTG_HC_DoPing(pdev, num);
|
||||
}
|
||||
pdev->host.URB_State[num] = URB_NOTREADY;
|
||||
}
|
||||
else if(pdev->host.HC_Status[num] == HC_STALL)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_STALL;
|
||||
}
|
||||
else if(pdev->host.HC_Status[num] == HC_XACTERR)
|
||||
{
|
||||
if (pdev->host.ErrCnt[num] == 3)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_ERROR;
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
}
|
||||
}
|
||||
CLEAR_HC_INT(hcreg , chhltd);
|
||||
}
|
||||
|
||||
|
||||
return 1;
|
||||
}
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma optimize = none
|
||||
#endif /* __CC_ARM */
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_hc_n_In_ISR
|
||||
* Handles interrupt for a specific Host Channel
|
||||
* @param pdev: Selected device
|
||||
* @param hc_num: Channel number
|
||||
* @retval status
|
||||
*/
|
||||
uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num)
|
||||
{
|
||||
USB_OTG_HCINTn_TypeDef hcint;
|
||||
USB_OTG_HCINTMSK_TypeDef hcintmsk;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
USB_OTG_HCTSIZn_TypeDef hctsiz;
|
||||
USB_OTG_HC_REGS *hcreg;
|
||||
|
||||
|
||||
hcreg = pdev->regs.HC_REGS[num];
|
||||
hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT);
|
||||
hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCINTMSK);
|
||||
hcint.d32 = hcint.d32 & hcintmsk.d32;
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR);
|
||||
hcintmsk.d32 = 0;
|
||||
|
||||
|
||||
if (hcint.b.ahberr)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg ,ahberr);
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
}
|
||||
else if (hcint.b.ack)
|
||||
{
|
||||
CLEAR_HC_INT(hcreg ,ack);
|
||||
}
|
||||
|
||||
else if (hcint.b.stall)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
pdev->host.HC_Status[num] = HC_STALL;
|
||||
CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */
|
||||
CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */
|
||||
hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak,
|
||||
else, the pdev->host.HC_Status = HC_STALL
|
||||
will be overwritten by 'nak' in code below */
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
}
|
||||
else if (hcint.b.datatglerr)
|
||||
{
|
||||
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
pdev->host.HC_Status[num] = HC_DATATGLERR;
|
||||
CLEAR_HC_INT(hcreg , datatglerr);
|
||||
}
|
||||
|
||||
if (hcint.b.frmovrun)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg ,frmovrun);
|
||||
}
|
||||
|
||||
else if (hcint.b.xfercompl)
|
||||
{
|
||||
|
||||
if (pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ);
|
||||
pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize;
|
||||
}
|
||||
|
||||
pdev->host.HC_Status[num] = HC_XFRC;
|
||||
pdev->host.ErrCnt [num]= 0;
|
||||
CLEAR_HC_INT(hcreg , xfercompl);
|
||||
|
||||
if ((hcchar.b.eptype == EP_TYPE_CTRL)||
|
||||
(hcchar.b.eptype == EP_TYPE_BULK))
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
pdev->host.hc[num].toggle_in ^= 1;
|
||||
|
||||
}
|
||||
else if(hcchar.b.eptype == EP_TYPE_INTR)
|
||||
{
|
||||
hcchar.b.oddfrm = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
|
||||
pdev->host.URB_State[num] = URB_DONE;
|
||||
}
|
||||
|
||||
}
|
||||
else if (hcint.b.chhltd)
|
||||
{
|
||||
MASK_HOST_INT_CHH (num);
|
||||
|
||||
if(pdev->host.HC_Status[num] == HC_XFRC)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_DONE;
|
||||
}
|
||||
|
||||
else if (pdev->host.HC_Status[num] == HC_STALL)
|
||||
{
|
||||
pdev->host.URB_State[num] = URB_STALL;
|
||||
}
|
||||
|
||||
else if((pdev->host.HC_Status[num] == HC_XACTERR) ||
|
||||
(pdev->host.HC_Status[num] == HC_DATATGLERR))
|
||||
{
|
||||
pdev->host.ErrCnt[num] = 0;
|
||||
pdev->host.URB_State[num] = URB_ERROR;
|
||||
|
||||
}
|
||||
else if(hcchar.b.eptype == EP_TYPE_INTR)
|
||||
{
|
||||
pdev->host.hc[num].toggle_in ^= 1;
|
||||
}
|
||||
|
||||
CLEAR_HC_INT(hcreg , chhltd);
|
||||
|
||||
}
|
||||
else if (hcint.b.xacterr)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
pdev->host.ErrCnt[num] ++;
|
||||
pdev->host.HC_Status[num] = HC_XACTERR;
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
CLEAR_HC_INT(hcreg , xacterr);
|
||||
|
||||
}
|
||||
else if (hcint.b.nak)
|
||||
{
|
||||
if(hcchar.b.eptype == EP_TYPE_INTR)
|
||||
{
|
||||
UNMASK_HOST_INT_CHH (num);
|
||||
USB_OTG_HC_Halt(pdev, num);
|
||||
}
|
||||
else if ((hcchar.b.eptype == EP_TYPE_CTRL)||
|
||||
(hcchar.b.eptype == EP_TYPE_BULK))
|
||||
{
|
||||
/* re-activate the channel */
|
||||
hcchar.b.chen = 1;
|
||||
hcchar.b.chdis = 0;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32);
|
||||
}
|
||||
pdev->host.HC_Status[num] = HC_NAK;
|
||||
CLEAR_HC_INT(hcreg , nak);
|
||||
}
|
||||
|
||||
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_rx_qlvl_ISR
|
||||
* Handles the Rx Status Queue Level Interrupt
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma optimize = none
|
||||
#endif /* __CC_ARM */
|
||||
static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GRXFSTS_TypeDef grxsts;
|
||||
USB_OTG_GINTMSK_TypeDef intmsk;
|
||||
USB_OTG_HCTSIZn_TypeDef hctsiz;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
__IO uint8_t channelnum =0;
|
||||
uint32_t count;
|
||||
|
||||
/* Disable the Rx Status Queue Level interrupt */
|
||||
intmsk.d32 = 0;
|
||||
intmsk.b.rxstsqlvl = 1;
|
||||
USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0);
|
||||
|
||||
grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP);
|
||||
channelnum = grxsts.b.chnum;
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR);
|
||||
|
||||
switch (grxsts.b.pktsts)
|
||||
{
|
||||
case GRXSTS_PKTSTS_IN:
|
||||
/* Read the data into the host buffer. */
|
||||
if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0))
|
||||
{
|
||||
|
||||
USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt);
|
||||
/*manage multiple Xfer */
|
||||
pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt;
|
||||
pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt;
|
||||
|
||||
|
||||
count = pdev->host.hc[channelnum].xfer_count;
|
||||
pdev->host.XferCnt[channelnum] = count;
|
||||
|
||||
hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ);
|
||||
if(hctsiz.b.pktcnt > 0)
|
||||
{
|
||||
/* re-activate the channel when more packets are expected */
|
||||
hcchar.b.chen = 1;
|
||||
hcchar.b.chdis = 0;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case GRXSTS_PKTSTS_IN_XFER_COMP:
|
||||
|
||||
case GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
|
||||
case GRXSTS_PKTSTS_CH_HALTED:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enable the Rx Status Queue Level interrupt */
|
||||
intmsk.b.rxstsqlvl = 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR
|
||||
* Handles the incomplete Periodic transfer Interrupt
|
||||
* @param pdev: Selected device
|
||||
* @retval status
|
||||
*/
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma optimize = none
|
||||
#endif /* __CC_ARM */
|
||||
static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_HCCHAR_TypeDef hcchar;
|
||||
|
||||
|
||||
|
||||
|
||||
hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR);
|
||||
hcchar.b.chen = 1;
|
||||
hcchar.b.chdis = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32);
|
||||
|
||||
gintsts.d32 = 0;
|
||||
/* Clear interrupt */
|
||||
gintsts.b.incomplisoout = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_hcd_int.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Peripheral Device Interface Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __HCD_INT_H__
|
||||
#define __HCD_INT_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_hcd.h"
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_INT
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct _USBH_HCD_INT
|
||||
{
|
||||
uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev);
|
||||
uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
}USBH_HCD_INT_cb_TypeDef;
|
||||
|
||||
extern USBH_HCD_INT_cb_TypeDef *USBH_HCD_INT_fops;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CLEAR_HC_INT(HC_REGS, intr) \
|
||||
{\
|
||||
USB_OTG_HCINTn_TypeDef hcint_clear; \
|
||||
hcint_clear.d32 = 0; \
|
||||
hcint_clear.b.intr = 1; \
|
||||
USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\
|
||||
}\
|
||||
|
||||
#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
|
||||
INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
|
||||
INTMSK.b.chhltd = 0; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
|
||||
|
||||
#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
|
||||
INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
|
||||
INTMSK.b.chhltd = 1; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
|
||||
|
||||
#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCINTMSK_TypeDef INTMSK; \
|
||||
INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
|
||||
INTMSK.b.ack = 0; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, GINTMSK.d32);}
|
||||
|
||||
#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef INTMSK; \
|
||||
INTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK); \
|
||||
INTMSK.b.ack = 1; \
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINTMSK, INTMSK.d32);}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_HCD_INT_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/* Callbacks handler */
|
||||
void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev);
|
||||
void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
|
||||
void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev);
|
||||
uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#endif //__HCD_INT_H__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_otg.c
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief OTG Core Layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_defines.h"
|
||||
#include "usb_regs.h"
|
||||
#include "usb_core.h"
|
||||
#include "usb_otg.h"
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_OTG
|
||||
* @brief This file is the interface between EFSL ans Host mass-storage class
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* OTG Interrupt Handler */
|
||||
|
||||
|
||||
/**
|
||||
* @brief STM32_USBO_OTG_ISR_Handler
|
||||
*
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
uint32_t retval = 0;
|
||||
USB_OTG_GINTSTS_TypeDef gintsts ;
|
||||
gintsts.d32 = 0;
|
||||
|
||||
gintsts.d32 = USB_OTG_Read_itr(pdev);
|
||||
if (gintsts.d32 == 0)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
if (gintsts.b.otgintr)
|
||||
{
|
||||
retval |= USB_OTG_HandleOTG_ISR(pdev);
|
||||
}
|
||||
if (gintsts.b.conidstschng)
|
||||
{
|
||||
retval |= USB_OTG_HandleConnectorIDStatusChange_ISR(pdev);
|
||||
}
|
||||
if (gintsts.b.sessreqintr)
|
||||
{
|
||||
retval |= USB_OTG_HandleSessionRequest_ISR(pdev);
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_Read_itr
|
||||
* returns the Core Interrupt register
|
||||
* @param None
|
||||
* @retval : status
|
||||
*/
|
||||
static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_GINTMSK_TypeDef gintmsk;
|
||||
USB_OTG_GINTMSK_TypeDef gintmsk_common;
|
||||
|
||||
|
||||
gintsts.d32 = 0;
|
||||
gintmsk.d32 = 0;
|
||||
gintmsk_common.d32 = 0;
|
||||
|
||||
/* OTG interrupts */
|
||||
gintmsk_common.b.sessreqintr = 1;
|
||||
gintmsk_common.b.conidstschng = 1;
|
||||
gintmsk_common.b.otgintr = 1;
|
||||
|
||||
gintsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS);
|
||||
gintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK);
|
||||
return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_HandleOTG_ISR
|
||||
* handles the OTG Interrupts
|
||||
* @param None
|
||||
* @retval : status
|
||||
*/
|
||||
static uint32_t USB_OTG_HandleOTG_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GOTGINT_TypeDef gotgint;
|
||||
USB_OTG_GOTGCTL_TypeDef gotgctl;
|
||||
|
||||
|
||||
gotgint.d32 = 0;
|
||||
gotgctl.d32 = 0;
|
||||
|
||||
gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT);
|
||||
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
|
||||
|
||||
if (gotgint.b.sesenddet)
|
||||
{
|
||||
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
|
||||
|
||||
|
||||
if (USB_OTG_IsDeviceMode(pdev))
|
||||
{
|
||||
|
||||
}
|
||||
else if (USB_OTG_IsHostMode(pdev))
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
/* ----> SRP SUCCESS or FAILURE INTERRUPT <---- */
|
||||
if (gotgint.b.sesreqsucstschng)
|
||||
{
|
||||
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
|
||||
if (gotgctl.b.sesreqscs) /* Session request success */
|
||||
{
|
||||
if (USB_OTG_IsDeviceMode(pdev))
|
||||
{
|
||||
|
||||
}
|
||||
/* Clear Session Request */
|
||||
gotgctl.d32 = 0;
|
||||
gotgctl.b.sesreq = 1;
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0);
|
||||
}
|
||||
else /* Session request failure */
|
||||
{
|
||||
if (USB_OTG_IsDeviceMode(pdev))
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
/* ----> HNP SUCCESS or FAILURE INTERRUPT <---- */
|
||||
if (gotgint.b.hstnegsucstschng)
|
||||
{
|
||||
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
|
||||
|
||||
if (gotgctl.b.hstnegscs) /* Host negotiation success */
|
||||
{
|
||||
if (USB_OTG_IsHostMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
else /* Host negotiation failure */
|
||||
{
|
||||
|
||||
}
|
||||
gotgint.b.hstnegsucstschng = 1; /* Ack "Host Negotiation Success Status Change" interrupt. */
|
||||
}
|
||||
/* ----> HOST NEGOTIATION DETECTED INTERRUPT <---- */
|
||||
if (gotgint.b.hstnegdet)
|
||||
{
|
||||
if (USB_OTG_IsDeviceMode(pdev)) /* The core AUTOMATICALLY sets the Host mode */
|
||||
{
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
if (gotgint.b.adevtoutchng)
|
||||
{}
|
||||
if (gotgint.b.debdone)
|
||||
{
|
||||
USB_OTG_ResetPort(pdev);
|
||||
}
|
||||
/* Clear OTG INT */
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_HandleConnectorIDStatusChange_ISR
|
||||
* handles the Connector ID Status Change Interrupt
|
||||
* @param None
|
||||
* @retval : status
|
||||
*/
|
||||
static uint32_t USB_OTG_HandleConnectorIDStatusChange_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTMSK_TypeDef gintmsk;
|
||||
USB_OTG_GOTGCTL_TypeDef gotgctl;
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
|
||||
gintsts.d32 = 0 ;
|
||||
gintmsk.d32 = 0 ;
|
||||
gotgctl.d32 = 0 ;
|
||||
gintmsk.b.sofintr = 1;
|
||||
|
||||
USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, gintmsk.d32, 0);
|
||||
gotgctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGCTL);
|
||||
|
||||
/* B-Device connector (Device Mode) */
|
||||
if (gotgctl.b.conidsts)
|
||||
{
|
||||
USB_OTG_DisableGlobalInt(pdev);
|
||||
USB_OTG_CoreInitDev(pdev);
|
||||
USB_OTG_EnableGlobalInt(pdev);
|
||||
pdev->otg.OTG_State = B_PERIPHERAL;
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_OTG_DisableGlobalInt(pdev);
|
||||
USB_OTG_CoreInitHost(pdev);
|
||||
USB_OTG_EnableGlobalInt(pdev);
|
||||
pdev->otg.OTG_State = A_HOST;
|
||||
}
|
||||
/* Set flag and clear interrupt */
|
||||
gintsts.b.conidstschng = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_HandleSessionRequest_ISR
|
||||
* Initiating the Session Request Protocol
|
||||
* @param None
|
||||
* @retval : status
|
||||
*/
|
||||
static uint32_t USB_OTG_HandleSessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GINTSTS_TypeDef gintsts;
|
||||
USB_OTG_GOTGCTL_TypeDef gotgctl;
|
||||
|
||||
|
||||
gotgctl.d32 = 0;
|
||||
gintsts.d32 = 0;
|
||||
|
||||
gotgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
|
||||
if (USB_OTG_IsDeviceMode(pdev) && (gotgctl.b.bsesvld))
|
||||
{
|
||||
|
||||
}
|
||||
else if (gotgctl.b.asesvld)
|
||||
{
|
||||
}
|
||||
/* Clear interrupt */
|
||||
gintsts.d32 = 0;
|
||||
gintsts.b.sessreqintr = 1;
|
||||
USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_InitiateSRP
|
||||
* Initiate an srp session
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
void USB_OTG_InitiateSRP(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_GOTGCTL_TypeDef otgctl;
|
||||
|
||||
otgctl.d32 = 0;
|
||||
|
||||
otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
|
||||
if (otgctl.b.sesreq)
|
||||
{
|
||||
return; /* SRP in progress */
|
||||
}
|
||||
otgctl.b.sesreq = 1;
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_InitiateHNP
|
||||
* Initiate HNP
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
void USB_OTG_InitiateHNP(USB_OTG_CORE_HANDLE *pdev , uint8_t state, uint8_t mode)
|
||||
{
|
||||
USB_OTG_GOTGCTL_TypeDef otgctl;
|
||||
USB_OTG_HPRT0_TypeDef hprt0;
|
||||
|
||||
otgctl.d32 = 0;
|
||||
hprt0.d32 = 0;
|
||||
|
||||
otgctl.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GOTGCTL );
|
||||
if (mode)
|
||||
{ /* Device mode */
|
||||
if (state)
|
||||
{
|
||||
|
||||
otgctl.b.devhnpen = 1; /* B-Dev has been enabled to perform HNP */
|
||||
otgctl.b.hnpreq = 1; /* Initiate an HNP req. to the connected USB host*/
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* Host mode */
|
||||
if (state)
|
||||
{
|
||||
otgctl.b.hstsethnpen = 1; /* A-Dev has enabled B-device for HNP */
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGCTL, otgctl.d32);
|
||||
/* Suspend the bus so that B-dev will disconnect indicating the initial condition for HNP to DWC_Core */
|
||||
hprt0.d32 = USB_OTG_ReadHPRT0(pdev);
|
||||
hprt0.b.prtsusp = 1; /* The core clear this bit when disconnect interrupt generated (GINTSTS.DisconnInt = '1') */
|
||||
USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USB_OTG_GetCurrentState
|
||||
* Return current OTG State
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
return pdev->otg.OTG_State;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usb_otg.h
|
||||
* @author MCD Application Team
|
||||
* @version V2.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief OTG Core Header
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USB_OTG__
|
||||
#define __USB_OTG__
|
||||
|
||||
|
||||
/** @addtogroup USB_OTG_DRIVER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_OTG
|
||||
* @brief This file is the
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
void USB_OTG_InitiateSRP(void);
|
||||
void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode);
|
||||
void USB_OTG_Switchback (USB_OTG_CORE_DEVICE *pdev);
|
||||
uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_DEVICE *pdev);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_OTG_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_OTG_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_OTG_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif //__USB_OTG__
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,105 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief USB Device configuration file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_VCP_CONF__H__
|
||||
#define __USBD_VCP_CONF__H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
//#define USBD_CFG_MAX_NUM 1
|
||||
//#define USBD_ITF_MAX_NUM 1
|
||||
|
||||
//#define USBD_SELF_POWERED
|
||||
|
||||
/** @defgroup USB_VCP_Class_Layer_Parameter
|
||||
* @{
|
||||
*/
|
||||
#define CDC_IN_EP 0x81 /* EP1 for data IN */
|
||||
#define CDC_OUT_EP 0x01 /* EP1 for data OUT */
|
||||
#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */
|
||||
|
||||
/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */
|
||||
#ifdef USE_USB_OTG_HS
|
||||
#define CDC_DATA_MAX_PACKET_SIZE 512 /* Endpoint IN & OUT Packet size */
|
||||
#define CDC_CMD_PACKET_SZE 8 /* Control Endpoint Packet size */
|
||||
|
||||
#define CDC_IN_FRAME_INTERVAL 40 /* Number of micro-frames between IN transfers */
|
||||
#define APP_RX_DATA_SIZE 2048 /* Total size of IN buffer:
|
||||
APP_RX_DATA_SIZE*8/MAX_BAUDARATE*1000 should be > CDC_IN_FRAME_INTERVAL*8 */
|
||||
#else
|
||||
#define CDC_DATA_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */
|
||||
#define CDC_CMD_PACKET_SZE 8 /* Control Endpoint Packet size */
|
||||
|
||||
#define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */
|
||||
#define APP_RX_DATA_SIZE 2048 /* Total size of IN buffer:
|
||||
APP_RX_DATA_SIZE*8/MAX_BAUDARATE*1000 should be > CDC_IN_FRAME_INTERVAL */
|
||||
#endif /* USE_USB_OTG_HS */
|
||||
|
||||
#define APP_FOPS VCP_fops
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif //__USBD_VCP_CONF__H__
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,818 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_cdc_core.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides the high layer firmware functions to manage the
|
||||
* following functionalities of the USB CDC Class:
|
||||
* - Initialization and Configuration of high and low layer
|
||||
* - Enumeration as CDC Device (and enumeration for each implemented memory interface)
|
||||
* - OUT/IN data transfer
|
||||
* - Command IN transfer (class requests management)
|
||||
* - Error management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* CDC Class Driver Description
|
||||
* ===================================================================
|
||||
* This driver manages the "Universal Serial Bus Class Definitions for Communications Devices
|
||||
* Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus
|
||||
* Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007"
|
||||
* This driver implements the following aspects of the specification:
|
||||
* - Device descriptor management
|
||||
* - Configuration descriptor management
|
||||
* - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)
|
||||
* - Requests management (as described in section 6.2 in specification)
|
||||
* - Abstract Control Model compliant
|
||||
* - Union Functional collection (using 1 IN endpoint for control)
|
||||
* - Data interface class
|
||||
|
||||
* @note
|
||||
* For the Abstract Control Model, this core allows only transmitting the requests to
|
||||
* lower layer dispatcher (ie. usbd_cdc_vcp.c/.h) which should manage each request and
|
||||
* perform relative actions.
|
||||
*
|
||||
* These aspects may be enriched or modified for a specific user application.
|
||||
*
|
||||
* This driver doesn't implement the following aspects of the specification
|
||||
* (but it is possible to manage these features with some modifications on this driver):
|
||||
* - Any class-specific aspect relative to communication classes should be managed by user application.
|
||||
* - All communication classes other than PSTN are not managed
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_cdc_core.h"
|
||||
#include "usbd_desc.h"
|
||||
#include "usbd_req.h"
|
||||
#include "usbd_cdc_conf.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup usbd_cdc
|
||||
* @brief usbd core module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup usbd_cdc_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup usbd_cdc_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup usbd_cdc_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup usbd_cdc_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*********************************************
|
||||
CDC Device library callbacks
|
||||
*********************************************/
|
||||
static uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx);
|
||||
static uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx);
|
||||
static uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req);
|
||||
static uint8_t usbd_cdc_EP0_RxReady (void *pdev);
|
||||
static uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum);
|
||||
static uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum);
|
||||
static uint8_t usbd_cdc_SOF (void *pdev);
|
||||
|
||||
/*********************************************
|
||||
CDC specific management functions
|
||||
*********************************************/
|
||||
static void Handle_USBAsynchXfer (void *pdev);
|
||||
static uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length);
|
||||
#ifdef USE_USB_OTG_HS
|
||||
static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length);
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup usbd_cdc_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
extern CDC_IF_Prop_TypeDef APP_FOPS;
|
||||
extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC];
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t usbd_cdc_CfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t usbd_cdc_OtherCfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN static __IO uint32_t usbd_cdc_AltSet __ALIGN_END = 0;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END ;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END ;
|
||||
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t CmdBuff[CDC_CMD_PACKET_SZE] __ALIGN_END ;
|
||||
|
||||
uint32_t APP_Rx_ptr_in = 0;
|
||||
uint32_t APP_Rx_ptr_out = 0;
|
||||
uint32_t APP_Rx_length = 0;
|
||||
|
||||
uint8_t USB_Tx_State = 0;
|
||||
|
||||
static uint32_t cdcCmd = 0xFF;
|
||||
static uint32_t cdcLen = 0;
|
||||
|
||||
/* CDC interface class callbacks structure */
|
||||
USBD_Class_cb_TypeDef USBD_CDC_cb =
|
||||
{
|
||||
usbd_cdc_Init,
|
||||
usbd_cdc_DeInit,
|
||||
usbd_cdc_Setup,
|
||||
NULL, /* EP0_TxSent, */
|
||||
usbd_cdc_EP0_RxReady,
|
||||
usbd_cdc_DataIn,
|
||||
usbd_cdc_DataOut,
|
||||
usbd_cdc_SOF,
|
||||
NULL,
|
||||
NULL,
|
||||
USBD_cdc_GetCfgDesc,
|
||||
#ifdef USE_USB_OTG_HS
|
||||
USBD_cdc_GetOtherCfgDesc, /* use same cobfig as per FS */
|
||||
#endif /* USE_USB_OTG_HS */
|
||||
};
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
/* USB CDC device Configuration Descriptor */
|
||||
__ALIGN_BEGIN uint8_t usbd_cdc_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =
|
||||
{
|
||||
/*Configuration Descriptor*/
|
||||
0x09, /* bLength: Configuration Descriptor size */
|
||||
USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
|
||||
USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */
|
||||
0x00,
|
||||
0x02, /* bNumInterfaces: 2 interface */
|
||||
0x01, /* bConfigurationValue: Configuration value */
|
||||
0x00, /* iConfiguration: Index of string descriptor describing the configuration */
|
||||
0xC0, /* bmAttributes: self powered */
|
||||
0x32, /* MaxPower 0 mA */
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
/*Interface Descriptor */
|
||||
0x09, /* bLength: Interface Descriptor size */
|
||||
USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */
|
||||
/* Interface descriptor type */
|
||||
0x00, /* bInterfaceNumber: Number of Interface */
|
||||
0x00, /* bAlternateSetting: Alternate setting */
|
||||
0x01, /* bNumEndpoints: One endpoints used */
|
||||
0x02, /* bInterfaceClass: Communication Interface Class */
|
||||
0x02, /* bInterfaceSubClass: Abstract Control Model */
|
||||
0x01, /* bInterfaceProtocol: Common AT commands */
|
||||
0x00, /* iInterface: */
|
||||
|
||||
/*Header Functional Descriptor*/
|
||||
0x05, /* bLength: Endpoint Descriptor size */
|
||||
0x24, /* bDescriptorType: CS_INTERFACE */
|
||||
0x00, /* bDescriptorSubtype: Header Func Desc */
|
||||
0x10, /* bcdCDC: spec release number */
|
||||
0x01,
|
||||
|
||||
/*Call Management Functional Descriptor*/
|
||||
0x05, /* bFunctionLength */
|
||||
0x24, /* bDescriptorType: CS_INTERFACE */
|
||||
0x01, /* bDescriptorSubtype: Call Management Func Desc */
|
||||
0x00, /* bmCapabilities: D0+D1 */
|
||||
0x01, /* bDataInterface: 1 */
|
||||
|
||||
/*ACM Functional Descriptor*/
|
||||
0x04, /* bFunctionLength */
|
||||
0x24, /* bDescriptorType: CS_INTERFACE */
|
||||
0x02, /* bDescriptorSubtype: Abstract Control Management desc */
|
||||
0x02, /* bmCapabilities */
|
||||
|
||||
/*Union Functional Descriptor*/
|
||||
0x05, /* bFunctionLength */
|
||||
0x24, /* bDescriptorType: CS_INTERFACE */
|
||||
0x06, /* bDescriptorSubtype: Union func desc */
|
||||
0x00, /* bMasterInterface: Communication class interface */
|
||||
0x01, /* bSlaveInterface0: Data Class Interface */
|
||||
|
||||
/*Endpoint 2 Descriptor*/
|
||||
0x07, /* bLength: Endpoint Descriptor size */
|
||||
USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
|
||||
CDC_CMD_EP, /* bEndpointAddress */
|
||||
0x03, /* bmAttributes: Interrupt */
|
||||
LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */
|
||||
HIBYTE(CDC_CMD_PACKET_SZE),
|
||||
#ifdef USE_USB_OTG_HS
|
||||
0x10, /* bInterval: */
|
||||
#else
|
||||
0xFF, /* bInterval: */
|
||||
#endif /* USE_USB_OTG_HS */
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
/*Data class interface descriptor*/
|
||||
0x09, /* bLength: Endpoint Descriptor size */
|
||||
USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */
|
||||
0x01, /* bInterfaceNumber: Number of Interface */
|
||||
0x00, /* bAlternateSetting: Alternate setting */
|
||||
0x02, /* bNumEndpoints: Two endpoints used */
|
||||
0x0A, /* bInterfaceClass: CDC */
|
||||
0x00, /* bInterfaceSubClass: */
|
||||
0x00, /* bInterfaceProtocol: */
|
||||
0x00, /* iInterface: */
|
||||
|
||||
/*Endpoint OUT Descriptor*/
|
||||
0x07, /* bLength: Endpoint Descriptor size */
|
||||
USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
|
||||
CDC_OUT_EP, /* bEndpointAddress */
|
||||
0x02, /* bmAttributes: Bulk */
|
||||
LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */
|
||||
HIBYTE(CDC_DATA_MAX_PACKET_SIZE),
|
||||
0x00, /* bInterval: ignore for Bulk transfer */
|
||||
|
||||
/*Endpoint IN Descriptor*/
|
||||
0x07, /* bLength: Endpoint Descriptor size */
|
||||
USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
|
||||
CDC_IN_EP, /* bEndpointAddress */
|
||||
0x02, /* bmAttributes: Bulk */
|
||||
LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */
|
||||
HIBYTE(CDC_DATA_MAX_PACKET_SIZE),
|
||||
0x00 /* bInterval: ignore for Bulk transfer */
|
||||
} ;
|
||||
|
||||
#ifdef USE_USB_OTG_HS
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t usbd_cdc_OtherCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =
|
||||
{
|
||||
0x09, /* bLength: Configuation Descriptor size */
|
||||
USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,
|
||||
USB_CDC_CONFIG_DESC_SIZ,
|
||||
0x00,
|
||||
0x02, /* bNumInterfaces: 2 interfaces */
|
||||
0x01, /* bConfigurationValue: */
|
||||
0x04, /* iConfiguration: */
|
||||
0xC0, /* bmAttributes: */
|
||||
0x32, /* MaxPower 100 mA */
|
||||
|
||||
/*Interface Descriptor */
|
||||
0x09, /* bLength: Interface Descriptor size */
|
||||
USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */
|
||||
/* Interface descriptor type */
|
||||
0x00, /* bInterfaceNumber: Number of Interface */
|
||||
0x00, /* bAlternateSetting: Alternate setting */
|
||||
0x01, /* bNumEndpoints: One endpoints used */
|
||||
0x02, /* bInterfaceClass: Communication Interface Class */
|
||||
0x02, /* bInterfaceSubClass: Abstract Control Model */
|
||||
0x01, /* bInterfaceProtocol: Common AT commands */
|
||||
0x00, /* iInterface: */
|
||||
|
||||
/*Header Functional Descriptor*/
|
||||
0x05, /* bLength: Endpoint Descriptor size */
|
||||
0x24, /* bDescriptorType: CS_INTERFACE */
|
||||
0x00, /* bDescriptorSubtype: Header Func Desc */
|
||||
0x10, /* bcdCDC: spec release number */
|
||||
0x01,
|
||||
|
||||
/*Call Management Functional Descriptor*/
|
||||
0x05, /* bFunctionLength */
|
||||
0x24, /* bDescriptorType: CS_INTERFACE */
|
||||
0x01, /* bDescriptorSubtype: Call Management Func Desc */
|
||||
0x00, /* bmCapabilities: D0+D1 */
|
||||
0x01, /* bDataInterface: 1 */
|
||||
|
||||
/*ACM Functional Descriptor*/
|
||||
0x04, /* bFunctionLength */
|
||||
0x24, /* bDescriptorType: CS_INTERFACE */
|
||||
0x02, /* bDescriptorSubtype: Abstract Control Management desc */
|
||||
0x02, /* bmCapabilities */
|
||||
|
||||
/*Union Functional Descriptor*/
|
||||
0x05, /* bFunctionLength */
|
||||
0x24, /* bDescriptorType: CS_INTERFACE */
|
||||
0x06, /* bDescriptorSubtype: Union func desc */
|
||||
0x00, /* bMasterInterface: Communication class interface */
|
||||
0x01, /* bSlaveInterface0: Data Class Interface */
|
||||
|
||||
/*Endpoint 2 Descriptor*/
|
||||
0x07, /* bLength: Endpoint Descriptor size */
|
||||
USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
|
||||
CDC_CMD_EP, /* bEndpointAddress */
|
||||
0x03, /* bmAttributes: Interrupt */
|
||||
LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */
|
||||
HIBYTE(CDC_CMD_PACKET_SZE),
|
||||
0xFF, /* bInterval: */
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
/*Data class interface descriptor*/
|
||||
0x09, /* bLength: Endpoint Descriptor size */
|
||||
USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */
|
||||
0x01, /* bInterfaceNumber: Number of Interface */
|
||||
0x00, /* bAlternateSetting: Alternate setting */
|
||||
0x02, /* bNumEndpoints: Two endpoints used */
|
||||
0x0A, /* bInterfaceClass: CDC */
|
||||
0x00, /* bInterfaceSubClass: */
|
||||
0x00, /* bInterfaceProtocol: */
|
||||
0x00, /* iInterface: */
|
||||
|
||||
/*Endpoint OUT Descriptor*/
|
||||
0x07, /* bLength: Endpoint Descriptor size */
|
||||
USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
|
||||
CDC_OUT_EP, /* bEndpointAddress */
|
||||
0x02, /* bmAttributes: Bulk */
|
||||
0x40, /* wMaxPacketSize: */
|
||||
0x00,
|
||||
0x00, /* bInterval: ignore for Bulk transfer */
|
||||
|
||||
/*Endpoint IN Descriptor*/
|
||||
0x07, /* bLength: Endpoint Descriptor size */
|
||||
USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
|
||||
CDC_IN_EP, /* bEndpointAddress */
|
||||
0x02, /* bmAttributes: Bulk */
|
||||
0x40, /* wMaxPacketSize: */
|
||||
0x00,
|
||||
0x00 /* bInterval */
|
||||
};
|
||||
#endif /* USE_USB_OTG_HS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup usbd_cdc_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usbd_cdc_Init
|
||||
* Initilaize the CDC interface
|
||||
* @param pdev: device instance
|
||||
* @param cfgidx: Configuration index
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t usbd_cdc_Init (void *pdev,
|
||||
uint8_t cfgidx)
|
||||
{
|
||||
uint8_t *pbuf;
|
||||
|
||||
/* Open EP IN */
|
||||
DCD_EP_Open(pdev,
|
||||
CDC_IN_EP,
|
||||
CDC_DATA_IN_PACKET_SIZE,
|
||||
USB_OTG_EP_BULK);
|
||||
|
||||
/* Open EP OUT */
|
||||
DCD_EP_Open(pdev,
|
||||
CDC_OUT_EP,
|
||||
CDC_DATA_OUT_PACKET_SIZE,
|
||||
USB_OTG_EP_BULK);
|
||||
|
||||
/* Open Command IN EP */
|
||||
DCD_EP_Open(pdev,
|
||||
CDC_CMD_EP,
|
||||
CDC_CMD_PACKET_SZE,
|
||||
USB_OTG_EP_INT);
|
||||
|
||||
pbuf = (uint8_t *)USBD_DeviceDesc;
|
||||
pbuf[4] = DEVICE_CLASS_CDC;
|
||||
pbuf[5] = DEVICE_SUBCLASS_CDC;
|
||||
|
||||
/* Initialize the Interface physical components */
|
||||
APP_FOPS.pIf_Init();
|
||||
|
||||
/* Prepare Out endpoint to receive next packet */
|
||||
DCD_EP_PrepareRx(pdev,
|
||||
CDC_OUT_EP,
|
||||
(uint8_t*)(USB_Rx_Buffer),
|
||||
CDC_DATA_OUT_PACKET_SIZE);
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usbd_cdc_Init
|
||||
* DeInitialize the CDC layer
|
||||
* @param pdev: device instance
|
||||
* @param cfgidx: Configuration index
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t usbd_cdc_DeInit (void *pdev,
|
||||
uint8_t cfgidx)
|
||||
{
|
||||
/* Open EP IN */
|
||||
DCD_EP_Close(pdev,
|
||||
CDC_IN_EP);
|
||||
|
||||
/* Open EP OUT */
|
||||
DCD_EP_Close(pdev,
|
||||
CDC_OUT_EP);
|
||||
|
||||
/* Open Command IN EP */
|
||||
DCD_EP_Close(pdev,
|
||||
CDC_CMD_EP);
|
||||
|
||||
/* Restore default state of the Interface physical components */
|
||||
APP_FOPS.pIf_DeInit();
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usbd_cdc_Setup
|
||||
* Handle the CDC specific requests
|
||||
* @param pdev: instance
|
||||
* @param req: usb requests
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t usbd_cdc_Setup (void *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
uint16_t len=USB_CDC_DESC_SIZ;
|
||||
uint8_t *pbuf=usbd_cdc_CfgDesc + 9;
|
||||
|
||||
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
||||
{
|
||||
/* CDC Class Requests -------------------------------*/
|
||||
case USB_REQ_TYPE_CLASS :
|
||||
/* Check if the request is a data setup packet */
|
||||
if (req->wLength)
|
||||
{
|
||||
/* Check if the request is Device-to-Host */
|
||||
if (req->bmRequest & 0x80)
|
||||
{
|
||||
/* Get the data to be sent to Host from interface layer */
|
||||
APP_FOPS.pIf_Ctrl(req->bRequest, CmdBuff, req->wLength);
|
||||
|
||||
/* Send the data to the host */
|
||||
USBD_CtlSendData (pdev,
|
||||
CmdBuff,
|
||||
req->wLength);
|
||||
}
|
||||
else /* Host-to-Device requeset */
|
||||
{
|
||||
/* Set the value of the current command to be processed */
|
||||
cdcCmd = req->bRequest;
|
||||
cdcLen = req->wLength;
|
||||
|
||||
/* Prepare the reception of the buffer over EP0
|
||||
Next step: the received data will be managed in usbd_cdc_EP0_TxSent()
|
||||
function. */
|
||||
USBD_CtlPrepareRx (pdev,
|
||||
CmdBuff,
|
||||
req->wLength);
|
||||
}
|
||||
}
|
||||
else /* No Data request */
|
||||
{
|
||||
/* Transfer the command to the interface layer */
|
||||
APP_FOPS.pIf_Ctrl(req->bRequest, NULL, 0);
|
||||
}
|
||||
|
||||
return USBD_OK;
|
||||
|
||||
default:
|
||||
USBD_CtlError (pdev, req);
|
||||
return USBD_FAIL;
|
||||
|
||||
|
||||
|
||||
/* Standard Requests -------------------------------*/
|
||||
case USB_REQ_TYPE_STANDARD:
|
||||
switch (req->bRequest)
|
||||
{
|
||||
case USB_REQ_GET_DESCRIPTOR:
|
||||
if( (req->wValue >> 8) == CDC_DESCRIPTOR_TYPE)
|
||||
{
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
pbuf = usbd_cdc_Desc;
|
||||
#else
|
||||
pbuf = usbd_cdc_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM);
|
||||
#endif
|
||||
len = MIN(USB_CDC_DESC_SIZ , req->wLength);
|
||||
}
|
||||
|
||||
USBD_CtlSendData (pdev,
|
||||
pbuf,
|
||||
len);
|
||||
break;
|
||||
|
||||
case USB_REQ_GET_INTERFACE :
|
||||
USBD_CtlSendData (pdev,
|
||||
(uint8_t *)&usbd_cdc_AltSet,
|
||||
1);
|
||||
break;
|
||||
|
||||
case USB_REQ_SET_INTERFACE :
|
||||
if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM)
|
||||
{
|
||||
usbd_cdc_AltSet = (uint8_t)(req->wValue);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Call the error management function (command will be nacked */
|
||||
USBD_CtlError (pdev, req);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usbd_cdc_EP0_RxReady
|
||||
* Data received on control endpoint
|
||||
* @param pdev: device device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t usbd_cdc_EP0_RxReady (void *pdev)
|
||||
{
|
||||
if (cdcCmd != NO_CMD)
|
||||
{
|
||||
/* Process the data */
|
||||
APP_FOPS.pIf_Ctrl(cdcCmd, CmdBuff, cdcLen);
|
||||
|
||||
/* Reset the command variable to default value */
|
||||
cdcCmd = NO_CMD;
|
||||
}
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usbd_audio_DataIn
|
||||
* Data sent on non-control IN endpoint
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint number
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum)
|
||||
{
|
||||
uint16_t USB_Tx_ptr;
|
||||
uint16_t USB_Tx_length;
|
||||
|
||||
if (USB_Tx_State == 1)
|
||||
{
|
||||
if (APP_Rx_length == 0)
|
||||
{
|
||||
USB_Tx_State = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE){
|
||||
USB_Tx_ptr = APP_Rx_ptr_out;
|
||||
USB_Tx_length = CDC_DATA_IN_PACKET_SIZE;
|
||||
|
||||
APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE;
|
||||
APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_Tx_ptr = APP_Rx_ptr_out;
|
||||
USB_Tx_length = APP_Rx_length;
|
||||
|
||||
APP_Rx_ptr_out += APP_Rx_length;
|
||||
APP_Rx_length = 0;
|
||||
}
|
||||
|
||||
/* Prepare the available data buffer to be sent on IN endpoint */
|
||||
DCD_EP_Tx (pdev,
|
||||
CDC_IN_EP,
|
||||
(uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr],
|
||||
USB_Tx_length);
|
||||
}
|
||||
}
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usbd_cdc_DataOut
|
||||
* Data received on non-control Out endpoint
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint number
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum)
|
||||
{
|
||||
uint16_t USB_Rx_Cnt;
|
||||
|
||||
/* Get the received data buffer and update the counter */
|
||||
USB_Rx_Cnt = ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].xfer_count;
|
||||
|
||||
/* USB data will be immediately processed, this allow next USB traffic being
|
||||
NAKed till the end of the application Xfer */
|
||||
APP_FOPS.pIf_DataRx(USB_Rx_Buffer, USB_Rx_Cnt);
|
||||
|
||||
/* Prepare Out endpoint to receive next packet */
|
||||
DCD_EP_PrepareRx(pdev,
|
||||
CDC_OUT_EP,
|
||||
(uint8_t*)(USB_Rx_Buffer),
|
||||
CDC_DATA_OUT_PACKET_SIZE);
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief usbd_audio_SOF
|
||||
* Start Of Frame event management
|
||||
* @param pdev: instance
|
||||
* @param epnum: endpoint number
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t usbd_cdc_SOF (void *pdev)
|
||||
{
|
||||
static uint32_t FrameCount = 0;
|
||||
|
||||
if (FrameCount++ == CDC_IN_FRAME_INTERVAL)
|
||||
{
|
||||
/* Reset the frame counter */
|
||||
FrameCount = 0;
|
||||
|
||||
/* Check the data to be sent through IN pipe */
|
||||
Handle_USBAsynchXfer(pdev);
|
||||
}
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle_USBAsynchXfer
|
||||
* Send data to USB
|
||||
* @param pdev: instance
|
||||
* @retval None
|
||||
*/
|
||||
static void Handle_USBAsynchXfer (void *pdev)
|
||||
{
|
||||
uint16_t USB_Tx_ptr;
|
||||
uint16_t USB_Tx_length;
|
||||
|
||||
if(USB_Tx_State != 1)
|
||||
{
|
||||
if (APP_Rx_ptr_out == APP_RX_DATA_SIZE)
|
||||
{
|
||||
APP_Rx_ptr_out = 0;
|
||||
}
|
||||
|
||||
if(APP_Rx_ptr_out == APP_Rx_ptr_in)
|
||||
{
|
||||
USB_Tx_State = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
if(APP_Rx_ptr_out > APP_Rx_ptr_in) /* rollback */
|
||||
{
|
||||
APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out;
|
||||
|
||||
}
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
APP_Rx_length &= ~0x03;
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
|
||||
if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE)
|
||||
{
|
||||
USB_Tx_ptr = APP_Rx_ptr_out;
|
||||
USB_Tx_length = CDC_DATA_IN_PACKET_SIZE;
|
||||
|
||||
APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE;
|
||||
APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE;
|
||||
}
|
||||
else
|
||||
{
|
||||
USB_Tx_ptr = APP_Rx_ptr_out;
|
||||
USB_Tx_length = APP_Rx_length;
|
||||
|
||||
APP_Rx_ptr_out += APP_Rx_length;
|
||||
APP_Rx_length = 0;
|
||||
}
|
||||
USB_Tx_State = 1;
|
||||
|
||||
DCD_EP_Tx (pdev,
|
||||
CDC_IN_EP,
|
||||
(uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr],
|
||||
USB_Tx_length);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_cdc_GetCfgDesc
|
||||
* Return configuration descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer data length
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
static uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length)
|
||||
{
|
||||
*length = sizeof (usbd_cdc_CfgDesc);
|
||||
return usbd_cdc_CfgDesc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_cdc_GetCfgDesc
|
||||
* Return configuration descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer data length
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
#ifdef USE_USB_OTG_HS
|
||||
static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length)
|
||||
{
|
||||
*length = sizeof (usbd_cdc_OtherCfgDesc);
|
||||
return usbd_cdc_OtherCfgDesc;
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_cdc_core.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header file for the usbd_cdc_core.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
#ifndef __USB_CDC_CORE_H_
|
||||
#define __USB_CDC_CORE_H_
|
||||
|
||||
#include "usbd_ioreq.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup usbd_cdc
|
||||
* @brief This file is the Header file for USBD_cdc.c
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup usbd_cdc_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
#define USB_CDC_CONFIG_DESC_SIZ (67)
|
||||
#define USB_CDC_DESC_SIZ (67-9)
|
||||
|
||||
#define CDC_DESCRIPTOR_TYPE 0x21
|
||||
|
||||
#define DEVICE_CLASS_CDC 0x02
|
||||
#define DEVICE_SUBCLASS_CDC 0x00
|
||||
|
||||
|
||||
#define USB_DEVICE_DESCRIPTOR_TYPE 0x01
|
||||
#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02
|
||||
#define USB_STRING_DESCRIPTOR_TYPE 0x03
|
||||
#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04
|
||||
#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05
|
||||
|
||||
#define STANDARD_ENDPOINT_DESC_SIZE 0x09
|
||||
|
||||
#define CDC_DATA_IN_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE
|
||||
|
||||
#define CDC_DATA_OUT_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE
|
||||
|
||||
/*---------------------------------------------------------------------*/
|
||||
/* CDC definitions */
|
||||
/*---------------------------------------------------------------------*/
|
||||
|
||||
/**************************************************/
|
||||
/* CDC Requests */
|
||||
/**************************************************/
|
||||
#define SEND_ENCAPSULATED_COMMAND 0x00
|
||||
#define GET_ENCAPSULATED_RESPONSE 0x01
|
||||
#define SET_COMM_FEATURE 0x02
|
||||
#define GET_COMM_FEATURE 0x03
|
||||
#define CLEAR_COMM_FEATURE 0x04
|
||||
#define SET_LINE_CODING 0x20
|
||||
#define GET_LINE_CODING 0x21
|
||||
#define SET_CONTROL_LINE_STATE 0x22
|
||||
#define SEND_BREAK 0x23
|
||||
#define NO_CMD 0xFF
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
typedef struct _CDC_IF_PROP
|
||||
{
|
||||
uint16_t (*pIf_Init) (void);
|
||||
uint16_t (*pIf_DeInit) (void);
|
||||
uint16_t (*pIf_Ctrl) (uint32_t Cmd, uint8_t* Buf, uint32_t Len);
|
||||
uint16_t (*pIf_DataTx) (uint8_t* Buf, uint32_t Len);
|
||||
uint16_t (*pIf_DataRx) (uint8_t* Buf, uint32_t Len);
|
||||
}
|
||||
CDC_IF_Prop_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern USBD_Class_cb_TypeDef USBD_CDC_cb;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif // __USB_CDC_CORE_H_
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_cdc_vcp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Generic media access Layer.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#pragma data_alignment = 4
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_cdc_vcp.h"
|
||||
#include "usbd_cdc_conf.h"
|
||||
#include "std.h"
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
LINE_CODING linecoding =
|
||||
{
|
||||
115200, /* baud rate*/
|
||||
0x00, /* stop bits-1*/
|
||||
0x00, /* parity - none*/
|
||||
0x08 /* nb. of bits 8*/
|
||||
};
|
||||
|
||||
|
||||
/* These are external variables imported from CDC core to be used for IN
|
||||
transfer management. */
|
||||
extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer.
|
||||
These data will be sent over USB IN endpoint
|
||||
in the CDC core functions. */
|
||||
extern uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to
|
||||
start address when writing received data
|
||||
in the buffer APP_Rx_Buffer. */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static uint16_t VCP_Init (void);
|
||||
static uint16_t VCP_DeInit (void);
|
||||
static uint16_t VCP_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len);
|
||||
static uint16_t VCP_DataTx (uint8_t* Buf, uint32_t Len);
|
||||
static uint16_t VCP_DataRx (uint8_t* Buf, uint32_t Len);
|
||||
|
||||
CDC_IF_Prop_TypeDef VCP_fops =
|
||||
{
|
||||
VCP_Init,
|
||||
VCP_DeInit,
|
||||
VCP_Ctrl,
|
||||
VCP_DataTx,
|
||||
VCP_DataRx
|
||||
};
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
/**
|
||||
* @brief VCP_Init
|
||||
* Initializes the Media on the STM32
|
||||
* @param None
|
||||
* @retval Result of the opeartion (USBD_OK in all cases)
|
||||
*/
|
||||
static uint16_t VCP_Init(void) {
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VCP_DeInit
|
||||
* DeInitializes the Media on the STM32
|
||||
* @param None
|
||||
* @retval Result of the opeartion (USBD_OK in all cases)
|
||||
*/
|
||||
static uint16_t VCP_DeInit(void)
|
||||
{
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief VCP_Ctrl
|
||||
* Manage the CDC class requests
|
||||
* @param Cmd: Command code
|
||||
* @param Buf: Buffer containing command data (request parameters)
|
||||
* @param Len: Number of data to be sent (in bytes)
|
||||
* @retval Result of the opeartion (USBD_OK in all cases)
|
||||
*/
|
||||
static uint16_t VCP_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len)
|
||||
{
|
||||
switch (Cmd)
|
||||
{
|
||||
case SEND_ENCAPSULATED_COMMAND:
|
||||
/* Not needed for this driver */
|
||||
break;
|
||||
|
||||
case GET_ENCAPSULATED_RESPONSE:
|
||||
/* Not needed for this driver */
|
||||
break;
|
||||
|
||||
case SET_COMM_FEATURE:
|
||||
/* Not needed for this driver */
|
||||
break;
|
||||
|
||||
case GET_COMM_FEATURE:
|
||||
/* Not needed for this driver */
|
||||
break;
|
||||
|
||||
case CLEAR_COMM_FEATURE:
|
||||
/* Not needed for this driver */
|
||||
break;
|
||||
|
||||
case SET_LINE_CODING:
|
||||
/*
|
||||
linecoding.bitrate = (uint32_t)(Buf[0] | (Buf[1] << 8) | (Buf[2] << 16) | (Buf[3] << 24));
|
||||
linecoding.format = Buf[4];
|
||||
linecoding.paritytype = Buf[5];
|
||||
linecoding.datatype = Buf[6];
|
||||
// Set the new configuration
|
||||
VCP_COMConfig(OTHER_CONFIG);
|
||||
*/
|
||||
break;
|
||||
|
||||
case GET_LINE_CODING:
|
||||
/*
|
||||
Buf[0] = (uint8_t)(linecoding.bitrate);
|
||||
Buf[1] = (uint8_t)(linecoding.bitrate >> 8);
|
||||
Buf[2] = (uint8_t)(linecoding.bitrate >> 16);
|
||||
Buf[3] = (uint8_t)(linecoding.bitrate >> 24);
|
||||
Buf[4] = linecoding.format;
|
||||
Buf[5] = linecoding.paritytype;
|
||||
Buf[6] = linecoding.datatype;
|
||||
*/
|
||||
Buf[0] = 0;
|
||||
Buf[1] = 0;
|
||||
Buf[2] = 0;
|
||||
Buf[3] = 0;
|
||||
Buf[4] = 0;
|
||||
Buf[5] = 0;
|
||||
Buf[6] = 0;
|
||||
break;
|
||||
|
||||
case SET_CONTROL_LINE_STATE:
|
||||
/* Not needed for this driver */
|
||||
break;
|
||||
|
||||
case SEND_BREAK:
|
||||
/* Not needed for this driver */
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VCP_DataTx
|
||||
* CDC received data to be send over USB IN endpoint are managed in
|
||||
* this function.
|
||||
* @param Buf: Buffer of data to be sent
|
||||
* @param Len: Number of data to be sent (in bytes)
|
||||
* @retval Result of the opeartion: USBD_OK if all operations are OK else VCP_FAIL
|
||||
*/
|
||||
static uint16_t VCP_DataTx (uint8_t* Buf, uint32_t Len)
|
||||
{
|
||||
for (int i = 0; i < Len; i++) {
|
||||
APP_Rx_Buffer[APP_Rx_ptr_in] = Buf[i];
|
||||
APP_Rx_ptr_in++;
|
||||
|
||||
/* To avoid buffer overflow */
|
||||
if(APP_Rx_ptr_in == APP_RX_DATA_SIZE) {
|
||||
APP_Rx_ptr_in = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief VCP_DataRx
|
||||
* Data received over USB OUT endpoint are sent over CDC interface
|
||||
* through this function.
|
||||
*
|
||||
* @note
|
||||
* This function will block any OUT packet reception on USB endpoint
|
||||
* untill exiting this function. If you exit this function before transfer
|
||||
* is complete on CDC interface (ie. using DMA controller) it will result
|
||||
* in receiving more data while previous ones are still not sent.
|
||||
*
|
||||
* @param Buf: Buffer of data to be received
|
||||
* @param Len: Number of data received (in bytes)
|
||||
* @retval Result of the opeartion: USBD_OK if all operations are OK else VCP_FAIL
|
||||
*/
|
||||
static uint16_t VCP_DataRx (uint8_t* Buf, uint32_t Len) {
|
||||
printf("%.*s", (int)Len, Buf);
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_cdc_vcp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Header for usbd_cdc_vcp.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_CDC_VCP_H
|
||||
#define __USBD_CDC_VCP_H
|
||||
|
||||
#include "usbd_cdc_core.h"
|
||||
#include "usbd_conf.h"
|
||||
|
||||
/* Exported typef ------------------------------------------------------------*/
|
||||
/* The following structures groups all needed parameters to be configured for the
|
||||
ComPort. These parameters can modified on the fly by the host through CDC class
|
||||
command class requests. */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t bitrate;
|
||||
uint8_t format;
|
||||
uint8_t paritytype;
|
||||
uint8_t datatype;
|
||||
} LINE_CODING;
|
||||
|
||||
#define DEFAULT_CONFIG 0
|
||||
#define OTHER_CONFIG 1
|
||||
|
||||
#endif /* __USBD_CDC_VCP_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#ifndef __USBD_CONF__H__
|
||||
#define __USBD_CONF__H__
|
||||
|
||||
#define USBD_CFG_MAX_NUM 1 // TODO need more than 1?
|
||||
#define USBD_ITF_MAX_NUM 1 // TODO need more than 1?
|
||||
|
||||
#endif //__USBD_CONF__H__
|
||||
|
|
@ -0,0 +1,506 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_core.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides all the USBD core functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_core.h"
|
||||
#include "usbd_req.h"
|
||||
#include "usbd_ioreq.h"
|
||||
#include "usb_dcd_int.h"
|
||||
#include "usb_bsp.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE
|
||||
* @brief usbd core module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_CORE_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
|
||||
static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum);
|
||||
static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev);
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev);
|
||||
#endif
|
||||
static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev);
|
||||
static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev) ;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_CORE_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
__IO USB_OTG_DCTL_TypeDef SET_TEST_MODE;
|
||||
|
||||
USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb =
|
||||
{
|
||||
USBD_DataOutStage,
|
||||
USBD_DataInStage,
|
||||
USBD_SetupStage,
|
||||
USBD_SOF,
|
||||
USBD_Reset,
|
||||
USBD_Suspend,
|
||||
USBD_Resume,
|
||||
USBD_IsoINIncomplete,
|
||||
USBD_IsoOUTIncomplete,
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
USBD_DevConnected,
|
||||
USBD_DevDisconnected,
|
||||
#endif
|
||||
};
|
||||
|
||||
USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops = &USBD_DCD_INT_cb;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_CORE_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USBD_Init
|
||||
* Initailizes the device stack and load the class driver
|
||||
* @param pdev: device instance
|
||||
* @param core_address: USB OTG core ID
|
||||
* @param class_cb: Class callback structure address
|
||||
* @param usr_cb: User callback structure address
|
||||
* @retval None
|
||||
*/
|
||||
void USBD_Init(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_OTG_CORE_ID_TypeDef coreID,
|
||||
USBD_DEVICE *pDevice,
|
||||
USBD_Class_cb_TypeDef *class_cb,
|
||||
USBD_Usr_cb_TypeDef *usr_cb)
|
||||
{
|
||||
/* Hardware Init */
|
||||
USB_OTG_BSP_Init(pdev);
|
||||
|
||||
USBD_DeInit(pdev);
|
||||
|
||||
/*Register class and user callbacks */
|
||||
pdev->dev.class_cb = class_cb;
|
||||
pdev->dev.usr_cb = usr_cb;
|
||||
pdev->dev.usr_device = pDevice;
|
||||
|
||||
/* set USB OTG core params */
|
||||
DCD_Init(pdev , coreID);
|
||||
|
||||
/* Upon Init call usr callback */
|
||||
pdev->dev.usr_cb->Init();
|
||||
|
||||
/* Enable Interrupts */
|
||||
USB_OTG_BSP_EnableInterrupt(pdev);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_DeInit
|
||||
* Re-Initialize th device library
|
||||
* @param pdev: device instance
|
||||
* @retval status: status
|
||||
*/
|
||||
USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
/* Software Init */
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_SetupStage
|
||||
* Handle the setup stage
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_SETUP_REQ req;
|
||||
|
||||
USBD_ParseSetupRequest(pdev , &req);
|
||||
|
||||
switch (req.bmRequest & 0x1F)
|
||||
{
|
||||
case USB_REQ_RECIPIENT_DEVICE:
|
||||
USBD_StdDevReq (pdev, &req);
|
||||
break;
|
||||
|
||||
case USB_REQ_RECIPIENT_INTERFACE:
|
||||
USBD_StdItfReq(pdev, &req);
|
||||
break;
|
||||
|
||||
case USB_REQ_RECIPIENT_ENDPOINT:
|
||||
USBD_StdEPReq(pdev, &req);
|
||||
break;
|
||||
|
||||
default:
|
||||
DCD_EP_Stall(pdev , req.bmRequest & 0x80);
|
||||
break;
|
||||
}
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_DataOutStage
|
||||
* Handle data out stage
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint index
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
if(epnum == 0)
|
||||
{
|
||||
ep = &pdev->dev.out_ep[0];
|
||||
if ( pdev->dev.device_state == USB_OTG_EP0_DATA_OUT)
|
||||
{
|
||||
if(ep->rem_data_len > ep->maxpacket)
|
||||
{
|
||||
ep->rem_data_len -= ep->maxpacket;
|
||||
|
||||
if(pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
/* in slave mode this, is handled by the RxSTSQLvl ISR */
|
||||
ep->xfer_buff += ep->maxpacket;
|
||||
}
|
||||
USBD_CtlContinueRx (pdev,
|
||||
ep->xfer_buff,
|
||||
MIN(ep->rem_data_len ,ep->maxpacket));
|
||||
}
|
||||
else
|
||||
{
|
||||
if((pdev->dev.class_cb->EP0_RxReady != NULL)&&
|
||||
(pdev->dev.device_status == USB_OTG_CONFIGURED))
|
||||
{
|
||||
pdev->dev.class_cb->EP0_RxReady(pdev);
|
||||
}
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
}
|
||||
}
|
||||
else if((pdev->dev.class_cb->DataOut != NULL)&&
|
||||
(pdev->dev.device_status == USB_OTG_CONFIGURED))
|
||||
{
|
||||
pdev->dev.class_cb->DataOut(pdev, epnum);
|
||||
}
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_DataInStage
|
||||
* Handle data in stage
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint index
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
|
||||
{
|
||||
USB_OTG_EP *ep;
|
||||
|
||||
if(epnum == 0)
|
||||
{
|
||||
ep = &pdev->dev.in_ep[0];
|
||||
if ( pdev->dev.device_state == USB_OTG_EP0_DATA_IN)
|
||||
{
|
||||
if(ep->rem_data_len > ep->maxpacket)
|
||||
{
|
||||
ep->rem_data_len -= ep->maxpacket;
|
||||
if(pdev->cfg.dma_enable == 1)
|
||||
{
|
||||
/* in slave mode this, is handled by the TxFifoEmpty ISR */
|
||||
ep->xfer_buff += ep->maxpacket;
|
||||
}
|
||||
USBD_CtlContinueSendData (pdev,
|
||||
ep->xfer_buff,
|
||||
ep->rem_data_len);
|
||||
}
|
||||
else
|
||||
{ /* last packet is MPS multiple, so send ZLP packet */
|
||||
if((ep->total_data_len % ep->maxpacket == 0) &&
|
||||
(ep->total_data_len >= ep->maxpacket) &&
|
||||
(ep->total_data_len < ep->ctl_data_len ))
|
||||
{
|
||||
|
||||
USBD_CtlContinueSendData(pdev , NULL, 0);
|
||||
ep->ctl_data_len = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((pdev->dev.class_cb->EP0_TxSent != NULL)&&
|
||||
(pdev->dev.device_status == USB_OTG_CONFIGURED))
|
||||
{
|
||||
pdev->dev.class_cb->EP0_TxSent(pdev);
|
||||
}
|
||||
USBD_CtlReceiveStatus(pdev);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (pdev->dev.test_mode == 1)
|
||||
{
|
||||
USBD_RunTestMode(pdev);
|
||||
pdev->dev.test_mode = 0;
|
||||
}
|
||||
}
|
||||
else if((pdev->dev.class_cb->DataIn != NULL)&&
|
||||
(pdev->dev.device_status == USB_OTG_CONFIGURED))
|
||||
{
|
||||
pdev->dev.class_cb->DataIn(pdev, epnum);
|
||||
}
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_RunTestMode
|
||||
* Launch test mode process
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t USBD_RunTestMode (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, SET_TEST_MODE.d32);
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_Reset
|
||||
* Handle Reset event
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
/* Open EP0 OUT */
|
||||
DCD_EP_Open(pdev,
|
||||
0x00,
|
||||
USB_OTG_MAX_EP0_SIZE,
|
||||
EP_TYPE_CTRL);
|
||||
|
||||
/* Open EP0 IN */
|
||||
DCD_EP_Open(pdev,
|
||||
0x80,
|
||||
USB_OTG_MAX_EP0_SIZE,
|
||||
EP_TYPE_CTRL);
|
||||
|
||||
/* Upon Reset call usr call back */
|
||||
pdev->dev.device_status = USB_OTG_DEFAULT;
|
||||
pdev->dev.usr_cb->DeviceReset(pdev->cfg.speed);
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_Resume
|
||||
* Handle Resume event
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
/* Upon Resume call usr call back */
|
||||
pdev->dev.usr_cb->DeviceResumed();
|
||||
pdev->dev.device_status = pdev->dev.device_old_status;
|
||||
pdev->dev.device_status = USB_OTG_CONFIGURED;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_Suspend
|
||||
* Handle Suspend event
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
pdev->dev.device_old_status = pdev->dev.device_status;
|
||||
pdev->dev.device_status = USB_OTG_SUSPENDED;
|
||||
/* Upon Resume call usr call back */
|
||||
pdev->dev.usr_cb->DeviceSuspended();
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_SOF
|
||||
* Handle SOF event
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
if(pdev->dev.class_cb->SOF)
|
||||
{
|
||||
pdev->dev.class_cb->SOF(pdev);
|
||||
}
|
||||
return USBD_OK;
|
||||
}
|
||||
/**
|
||||
* @brief USBD_SetCfg
|
||||
* Configure device and start the interface
|
||||
* @param pdev: device instance
|
||||
* @param cfgidx: configuration index
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx)
|
||||
{
|
||||
pdev->dev.class_cb->Init(pdev, cfgidx);
|
||||
|
||||
/* Upon set config call usr call back */
|
||||
pdev->dev.usr_cb->DeviceConfigured();
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_ClrCfg
|
||||
* Clear current configuration
|
||||
* @param pdev: device instance
|
||||
* @param cfgidx: configuration index
|
||||
* @retval status: USBD_Status
|
||||
*/
|
||||
USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx)
|
||||
{
|
||||
pdev->dev.class_cb->DeInit(pdev, cfgidx);
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_IsoINIncomplete
|
||||
* Handle iso in incomplete event
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
pdev->dev.class_cb->IsoINIncomplete(pdev);
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_IsoOUTIncomplete
|
||||
* Handle iso out incomplete event
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
pdev->dev.class_cb->IsoOUTIncomplete(pdev);
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
#ifdef VBUS_SENSING_ENABLED
|
||||
/**
|
||||
* @brief USBD_DevConnected
|
||||
* Handle device connection event
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
pdev->dev.usr_cb->DeviceConnected();
|
||||
pdev->dev.connection_status = 1;
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_DevDisconnected
|
||||
* Handle device disconnection event
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
pdev->dev.usr_cb->DeviceDisconnected();
|
||||
pdev->dev.class_cb->DeInit(pdev, 0);
|
||||
pdev->dev.connection_status = 0;
|
||||
return USBD_OK;
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_core.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Header file for usbd_core.c
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_CORE_H
|
||||
#define __USBD_CORE_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_dcd.h"
|
||||
#include "usbd_def.h"
|
||||
//#include "usbd_conf.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_CORE
|
||||
* @brief This file is the Header file for usbd_core.c file
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
USBD_OK = 0,
|
||||
USBD_BUSY,
|
||||
USBD_FAIL,
|
||||
}USBD_Status;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
void USBD_Init(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_OTG_CORE_ID_TypeDef coreID,
|
||||
USBD_DEVICE *pDevice,
|
||||
USBD_Class_cb_TypeDef *class_cb,
|
||||
USBD_Usr_cb_TypeDef *usr_cb);
|
||||
|
||||
USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx);
|
||||
|
||||
USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USBD_CORE_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_def.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief general defines for the usb device library
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
||||
#ifndef __USBD_DEF_H
|
||||
#define __USBD_DEF_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
//#include "usbd_conf.h"
|
||||
#define USB_MAX_STR_DESC_SIZ 255
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DEF
|
||||
* @brief general defines for the usb device library file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DEF_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef NULL
|
||||
#define NULL 0
|
||||
#endif
|
||||
|
||||
#define USB_LEN_DEV_QUALIFIER_DESC 0x0A
|
||||
#define USB_LEN_DEV_DESC 0x12
|
||||
#define USB_LEN_CFG_DESC 0x09
|
||||
#define USB_LEN_IF_DESC 0x09
|
||||
#define USB_LEN_EP_DESC 0x07
|
||||
#define USB_LEN_OTG_DESC 0x03
|
||||
|
||||
#define USBD_IDX_LANGID_STR 0x00
|
||||
#define USBD_IDX_MFC_STR 0x01
|
||||
#define USBD_IDX_PRODUCT_STR 0x02
|
||||
#define USBD_IDX_SERIAL_STR 0x03
|
||||
#define USBD_IDX_CONFIG_STR 0x04
|
||||
#define USBD_IDX_INTERFACE_STR 0x05
|
||||
|
||||
#define USB_REQ_TYPE_STANDARD 0x00
|
||||
#define USB_REQ_TYPE_CLASS 0x20
|
||||
#define USB_REQ_TYPE_VENDOR 0x40
|
||||
#define USB_REQ_TYPE_MASK 0x60
|
||||
|
||||
#define USB_REQ_RECIPIENT_DEVICE 0x00
|
||||
#define USB_REQ_RECIPIENT_INTERFACE 0x01
|
||||
#define USB_REQ_RECIPIENT_ENDPOINT 0x02
|
||||
#define USB_REQ_RECIPIENT_MASK 0x03
|
||||
|
||||
#define USB_REQ_GET_STATUS 0x00
|
||||
#define USB_REQ_CLEAR_FEATURE 0x01
|
||||
#define USB_REQ_SET_FEATURE 0x03
|
||||
#define USB_REQ_SET_ADDRESS 0x05
|
||||
#define USB_REQ_GET_DESCRIPTOR 0x06
|
||||
#define USB_REQ_SET_DESCRIPTOR 0x07
|
||||
#define USB_REQ_GET_CONFIGURATION 0x08
|
||||
#define USB_REQ_SET_CONFIGURATION 0x09
|
||||
#define USB_REQ_GET_INTERFACE 0x0A
|
||||
#define USB_REQ_SET_INTERFACE 0x0B
|
||||
#define USB_REQ_SYNCH_FRAME 0x0C
|
||||
|
||||
#define USB_DESC_TYPE_DEVICE 1
|
||||
#define USB_DESC_TYPE_CONFIGURATION 2
|
||||
#define USB_DESC_TYPE_STRING 3
|
||||
#define USB_DESC_TYPE_INTERFACE 4
|
||||
#define USB_DESC_TYPE_ENDPOINT 5
|
||||
#define USB_DESC_TYPE_DEVICE_QUALIFIER 6
|
||||
#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7
|
||||
|
||||
|
||||
#define USB_CONFIG_REMOTE_WAKEUP 2
|
||||
#define USB_CONFIG_SELF_POWERED 1
|
||||
|
||||
#define USB_FEATURE_EP_HALT 0
|
||||
#define USB_FEATURE_REMOTE_WAKEUP 1
|
||||
#define USB_FEATURE_TEST_MODE 2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_DEF_Exported_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_DEF_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
|
||||
(((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))
|
||||
|
||||
#define LOBYTE(x) ((uint8_t)(x & 0x00FF))
|
||||
#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_DEF_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_DEF_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USBD_DEF_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,317 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_desc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides the USBD descriptors and string formating method.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_core.h"
|
||||
#include "usbd_desc.h"
|
||||
#include "usbd_req.h"
|
||||
#include "usb_regs.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_DESC
|
||||
* @brief USBD descriptors module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_DESC_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_DESC_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
#define USBD_VID 0x0483 // TODO set VID
|
||||
|
||||
#define USBD_PID 0x5720 // TODO set PID
|
||||
|
||||
/** @defgroup USB_String_Descriptors
|
||||
* @{
|
||||
*/
|
||||
#define USBD_LANGID_STRING 0x409
|
||||
#define USBD_MANUFACTURER_STRING "STMicroelectronics" // TODO set
|
||||
#define USBD_PRODUCT_HS_STRING "VCP/MSC in HS Mode" // TODO set
|
||||
#define USBD_SERIALNUMBER_HS_STRING "00000000001A" // TODO set
|
||||
#define USBD_PRODUCT_FS_STRING "VCP/MSC in FS Mode" // TODO set
|
||||
#define USBD_SERIALNUMBER_FS_STRING "00000000001B" // TODO set
|
||||
#define USBD_CONFIGURATION_HS_STRING "VCP/MSC Config" // TODO set
|
||||
#define USBD_INTERFACE_HS_STRING "VCP/MSC Interface" // TODO set
|
||||
#define USBD_CONFIGURATION_FS_STRING "VCP/MSC Config" // TODO set
|
||||
#define USBD_INTERFACE_FS_STRING "VCP/MSC Interface" // TODO set
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_DESC_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_DESC_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
USBD_DEVICE USR_desc =
|
||||
{
|
||||
USBD_USR_DeviceDescriptor,
|
||||
USBD_USR_LangIDStrDescriptor,
|
||||
USBD_USR_ManufacturerStrDescriptor,
|
||||
USBD_USR_ProductStrDescriptor,
|
||||
USBD_USR_SerialStrDescriptor,
|
||||
USBD_USR_ConfigStrDescriptor,
|
||||
USBD_USR_InterfaceStrDescriptor,
|
||||
|
||||
};
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
/* USB Standard Device Descriptor */
|
||||
__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END =
|
||||
{
|
||||
0x12, /*bLength */
|
||||
USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/
|
||||
0x00, /*bcdUSB */
|
||||
0x02,
|
||||
0x00, /*bDeviceClass*/
|
||||
0x00, /*bDeviceSubClass*/
|
||||
0x00, /*bDeviceProtocol*/
|
||||
USB_OTG_MAX_EP0_SIZE, /*bMaxPacketSize*/
|
||||
LOBYTE(USBD_VID), /*idVendor*/
|
||||
HIBYTE(USBD_VID), /*idVendor*/
|
||||
LOBYTE(USBD_PID), /*idVendor*/
|
||||
HIBYTE(USBD_PID), /*idVendor*/
|
||||
0x00, /*bcdDevice rel. 2.00*/
|
||||
0x02,
|
||||
USBD_IDX_MFC_STR, /*Index of manufacturer string*/
|
||||
USBD_IDX_PRODUCT_STR, /*Index of product string*/
|
||||
USBD_IDX_SERIAL_STR, /*Index of serial number string*/
|
||||
USBD_CFG_MAX_NUM /*bNumConfigurations*/
|
||||
} ; /* USB_DeviceDescriptor */
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
/* USB Standard Device Descriptor */
|
||||
__ALIGN_BEGIN uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =
|
||||
{
|
||||
USB_LEN_DEV_QUALIFIER_DESC,
|
||||
USB_DESC_TYPE_DEVICE_QUALIFIER,
|
||||
0x00,
|
||||
0x02,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x40,
|
||||
0x01,
|
||||
0x00,
|
||||
};
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
/* USB Standard Device Descriptor */
|
||||
__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END =
|
||||
{
|
||||
USB_SIZ_STRING_LANGID,
|
||||
USB_DESC_TYPE_STRING,
|
||||
LOBYTE(USBD_LANGID_STRING),
|
||||
HIBYTE(USBD_LANGID_STRING),
|
||||
};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_DESC_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_DESC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_DeviceDescriptor
|
||||
* return the device descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer to data length variable
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length)
|
||||
{
|
||||
*length = sizeof(USBD_DeviceDesc);
|
||||
return USBD_DeviceDesc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_LangIDStrDescriptor
|
||||
* return the LangID string descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer to data length variable
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length)
|
||||
{
|
||||
*length = sizeof(USBD_LangIDDesc);
|
||||
return USBD_LangIDDesc;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_ProductStrDescriptor
|
||||
* return the product string descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer to data length variable
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length)
|
||||
{
|
||||
|
||||
|
||||
if(speed == 0)
|
||||
{
|
||||
USBD_GetString (USBD_PRODUCT_HS_STRING, USBD_StrDesc, length);
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_GetString (USBD_PRODUCT_FS_STRING, USBD_StrDesc, length);
|
||||
}
|
||||
return USBD_StrDesc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_ManufacturerStrDescriptor
|
||||
* return the manufacturer string descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer to data length variable
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length)
|
||||
{
|
||||
USBD_GetString (USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
|
||||
return USBD_StrDesc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_SerialStrDescriptor
|
||||
* return the serial number string descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer to data length variable
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length)
|
||||
{
|
||||
if(speed == USB_OTG_SPEED_HIGH)
|
||||
{
|
||||
USBD_GetString (USBD_SERIALNUMBER_HS_STRING, USBD_StrDesc, length);
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_GetString (USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length);
|
||||
}
|
||||
return USBD_StrDesc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_ConfigStrDescriptor
|
||||
* return the configuration string descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer to data length variable
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length)
|
||||
{
|
||||
if(speed == USB_OTG_SPEED_HIGH)
|
||||
{
|
||||
USBD_GetString (USBD_CONFIGURATION_HS_STRING, USBD_StrDesc, length);
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_GetString (USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length);
|
||||
}
|
||||
return USBD_StrDesc;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_InterfaceStrDescriptor
|
||||
* return the interface string descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer to data length variable
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length)
|
||||
{
|
||||
if(speed == 0)
|
||||
{
|
||||
USBD_GetString (USBD_INTERFACE_HS_STRING, USBD_StrDesc, length);
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_GetString (USBD_INTERFACE_FS_STRING, USBD_StrDesc, length);
|
||||
}
|
||||
return USBD_StrDesc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_desc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header file for the usbd_desc.c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
||||
#ifndef __USB_DESC_H
|
||||
#define __USB_DESC_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_def.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DESC
|
||||
* @brief general defines for the usb device library file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_DESC_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
#define USB_DEVICE_DESCRIPTOR_TYPE 0x01
|
||||
#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02
|
||||
#define USB_STRING_DESCRIPTOR_TYPE 0x03
|
||||
#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04
|
||||
#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05
|
||||
#define USB_SIZ_DEVICE_DESC 18
|
||||
#define USB_SIZ_STRING_LANGID 4
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_DESC_Exported_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_DESC_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_DESC_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC];
|
||||
extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ];
|
||||
extern uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC];
|
||||
extern uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC];
|
||||
extern uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID];
|
||||
extern USBD_DEVICE USR_desc;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_DESC_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length);
|
||||
uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length);
|
||||
uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length);
|
||||
uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length);
|
||||
uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length);
|
||||
uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length);
|
||||
uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length);
|
||||
|
||||
#ifdef USB_SUPPORT_USER_STRING_DESC
|
||||
uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length);
|
||||
#endif /* USB_SUPPORT_USER_STRING_DESC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USBD_DESC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_ioreq.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides the IO requests APIs for control endpoints.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_ioreq.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_IOREQ
|
||||
* @brief control I/O requests module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_IOREQ_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_IOREQ_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_IOREQ_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_IOREQ_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_IOREQ_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_IOREQ_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USBD_CtlSendData
|
||||
* send data on the ctl pipe
|
||||
* @param pdev: device instance
|
||||
* @param buff: pointer to data buffer
|
||||
* @param len: length of data to be sent
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t *pbuf,
|
||||
uint16_t len)
|
||||
{
|
||||
USBD_Status ret = USBD_OK;
|
||||
|
||||
pdev->dev.in_ep[0].total_data_len = len;
|
||||
pdev->dev.in_ep[0].rem_data_len = len;
|
||||
pdev->dev.device_state = USB_OTG_EP0_DATA_IN;
|
||||
|
||||
DCD_EP_Tx (pdev, 0, pbuf, len);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_CtlContinueSendData
|
||||
* continue sending data on the ctl pipe
|
||||
* @param pdev: device instance
|
||||
* @param buff: pointer to data buffer
|
||||
* @param len: length of data to be sent
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t *pbuf,
|
||||
uint16_t len)
|
||||
{
|
||||
USBD_Status ret = USBD_OK;
|
||||
|
||||
DCD_EP_Tx (pdev, 0, pbuf, len);
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_CtlPrepareRx
|
||||
* receive data on the ctl pipe
|
||||
* @param pdev: USB OTG device instance
|
||||
* @param buff: pointer to data buffer
|
||||
* @param len: length of data to be received
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t *pbuf,
|
||||
uint16_t len)
|
||||
{
|
||||
USBD_Status ret = USBD_OK;
|
||||
|
||||
pdev->dev.out_ep[0].total_data_len = len;
|
||||
pdev->dev.out_ep[0].rem_data_len = len;
|
||||
pdev->dev.device_state = USB_OTG_EP0_DATA_OUT;
|
||||
|
||||
DCD_EP_PrepareRx (pdev,
|
||||
0,
|
||||
pbuf,
|
||||
len);
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_CtlContinueRx
|
||||
* continue receive data on the ctl pipe
|
||||
* @param pdev: USB OTG device instance
|
||||
* @param buff: pointer to data buffer
|
||||
* @param len: length of data to be received
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t *pbuf,
|
||||
uint16_t len)
|
||||
{
|
||||
USBD_Status ret = USBD_OK;
|
||||
|
||||
DCD_EP_PrepareRx (pdev,
|
||||
0,
|
||||
pbuf,
|
||||
len);
|
||||
return ret;
|
||||
}
|
||||
/**
|
||||
* @brief USBD_CtlSendStatus
|
||||
* send zero lzngth packet on the ctl pipe
|
||||
* @param pdev: USB OTG device instance
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USBD_Status ret = USBD_OK;
|
||||
pdev->dev.device_state = USB_OTG_EP0_STATUS_IN;
|
||||
DCD_EP_Tx (pdev,
|
||||
0,
|
||||
NULL,
|
||||
0);
|
||||
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_CtlReceiveStatus
|
||||
* receive zero lzngth packet on the ctl pipe
|
||||
* @param pdev: USB OTG device instance
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
USBD_Status ret = USBD_OK;
|
||||
pdev->dev.device_state = USB_OTG_EP0_STATUS_OUT;
|
||||
DCD_EP_PrepareRx ( pdev,
|
||||
0,
|
||||
NULL,
|
||||
0);
|
||||
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_GetRxCount
|
||||
* returns the received data length
|
||||
* @param pdev: USB OTG device instance
|
||||
* epnum: endpoint index
|
||||
* @retval Rx Data blength
|
||||
*/
|
||||
uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum)
|
||||
{
|
||||
return pdev->dev.out_ep[epnum].xfer_count;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,121 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_ioreq.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header file for the usbd_ioreq.c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
||||
#ifndef __USBD_IOREQ_H_
|
||||
#define __USBD_IOREQ_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_def.h"
|
||||
#include "usbd_core.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_IOREQ
|
||||
* @brief header file for the usbd_ioreq.c file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_IOREQ_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_IOREQ_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_IOREQ_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_IOREQ_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t *buf,
|
||||
uint16_t len);
|
||||
|
||||
USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t *pbuf,
|
||||
uint16_t len);
|
||||
|
||||
USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t *pbuf,
|
||||
uint16_t len);
|
||||
|
||||
USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t *pbuf,
|
||||
uint16_t len);
|
||||
|
||||
USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev ,
|
||||
uint8_t epnum);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USBD_IOREQ_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,401 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_bot.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides all the BOT protocol core functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_msc_bot.h"
|
||||
#include "usbd_msc_scsi.h"
|
||||
#include "usbd_ioreq.h"
|
||||
#include "usbd_msc_mem.h"
|
||||
#include "usbd_msc_conf.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_BOT
|
||||
* @brief BOT protocol module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MSC_BOT_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_BOT_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_BOT_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_BOT_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
uint16_t MSC_BOT_DataLen;
|
||||
uint8_t MSC_BOT_State;
|
||||
uint8_t MSC_BOT_Status;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __ALIGN_END ;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_BOT_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
static void MSC_BOT_SendData (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t* pbuf,
|
||||
uint16_t len);
|
||||
|
||||
static void MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_BOT_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_Init
|
||||
* Initialize the BOT Process
|
||||
* @param pdev: device instance
|
||||
* @retval None
|
||||
*/
|
||||
void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
MSC_BOT_State = BOT_IDLE;
|
||||
MSC_BOT_Status = BOT_STATE_NORMAL;
|
||||
USBD_STORAGE_fops->Init(0);
|
||||
|
||||
DCD_EP_Flush(pdev, MSC_OUT_EP);
|
||||
DCD_EP_Flush(pdev, MSC_IN_EP);
|
||||
/* Prapare EP to Receive First BOT Cmd */
|
||||
DCD_EP_PrepareRx (pdev,
|
||||
MSC_OUT_EP,
|
||||
(uint8_t *)&MSC_BOT_cbw,
|
||||
BOT_CBW_LENGTH);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_Reset
|
||||
* Reset the BOT Machine
|
||||
* @param pdev: device instance
|
||||
* @retval None
|
||||
*/
|
||||
void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
MSC_BOT_State = BOT_IDLE;
|
||||
MSC_BOT_Status = BOT_STATE_RECOVERY;
|
||||
/* Prapare EP to Receive First BOT Cmd */
|
||||
DCD_EP_PrepareRx (pdev,
|
||||
MSC_OUT_EP,
|
||||
(uint8_t *)&MSC_BOT_cbw,
|
||||
BOT_CBW_LENGTH);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_DeInit
|
||||
* Uninitialize the BOT Machine
|
||||
* @param pdev: device instance
|
||||
* @retval None
|
||||
*/
|
||||
void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
MSC_BOT_State = BOT_IDLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_DataIn
|
||||
* Handle BOT IN data stage
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint index
|
||||
* @retval None
|
||||
*/
|
||||
void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum)
|
||||
{
|
||||
|
||||
switch (MSC_BOT_State)
|
||||
{
|
||||
case BOT_DATA_IN:
|
||||
if(SCSI_ProcessCmd(pdev,
|
||||
MSC_BOT_cbw.bLUN,
|
||||
&MSC_BOT_cbw.CB[0]) < 0)
|
||||
{
|
||||
MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
|
||||
}
|
||||
break;
|
||||
|
||||
case BOT_SEND_DATA:
|
||||
case BOT_LAST_DATA_IN:
|
||||
MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief MSC_BOT_DataOut
|
||||
* Proccess MSC OUT data
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint index
|
||||
* @retval None
|
||||
*/
|
||||
void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum)
|
||||
{
|
||||
switch (MSC_BOT_State)
|
||||
{
|
||||
case BOT_IDLE:
|
||||
MSC_BOT_CBW_Decode(pdev);
|
||||
break;
|
||||
|
||||
case BOT_DATA_OUT:
|
||||
|
||||
if(SCSI_ProcessCmd(pdev,
|
||||
MSC_BOT_cbw.bLUN,
|
||||
&MSC_BOT_cbw.CB[0]) < 0)
|
||||
{
|
||||
MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_CBW_Decode
|
||||
* Decode the CBW command and set the BOT state machine accordingtly
|
||||
* @param pdev: device instance
|
||||
* @retval None
|
||||
*/
|
||||
static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag;
|
||||
MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength;
|
||||
|
||||
if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) ||
|
||||
(MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)||
|
||||
(MSC_BOT_cbw.bLUN > 1) ||
|
||||
(MSC_BOT_cbw.bCBLength < 1) ||
|
||||
(MSC_BOT_cbw.bCBLength > 16))
|
||||
{
|
||||
|
||||
SCSI_SenseCode(MSC_BOT_cbw.bLUN,
|
||||
ILLEGAL_REQUEST,
|
||||
INVALID_CDB);
|
||||
MSC_BOT_Status = BOT_STATE_ERROR;
|
||||
MSC_BOT_Abort(pdev);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
if(SCSI_ProcessCmd(pdev,
|
||||
MSC_BOT_cbw.bLUN,
|
||||
&MSC_BOT_cbw.CB[0]) < 0)
|
||||
{
|
||||
MSC_BOT_Abort(pdev);
|
||||
}
|
||||
/*Burst xfer handled internally*/
|
||||
else if ((MSC_BOT_State != BOT_DATA_IN) &&
|
||||
(MSC_BOT_State != BOT_DATA_OUT) &&
|
||||
(MSC_BOT_State != BOT_LAST_DATA_IN))
|
||||
{
|
||||
if (MSC_BOT_DataLen > 0)
|
||||
{
|
||||
MSC_BOT_SendData(pdev,
|
||||
MSC_BOT_Data,
|
||||
MSC_BOT_DataLen);
|
||||
}
|
||||
else if (MSC_BOT_DataLen == 0)
|
||||
{
|
||||
MSC_BOT_SendCSW (pdev,
|
||||
CSW_CMD_PASSED);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_SendData
|
||||
* Send the requested data
|
||||
* @param pdev: device instance
|
||||
* @param buf: pointer to data buffer
|
||||
* @param len: Data Length
|
||||
* @retval None
|
||||
*/
|
||||
static void MSC_BOT_SendData(USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t* buf,
|
||||
uint16_t len)
|
||||
{
|
||||
|
||||
len = MIN (MSC_BOT_cbw.dDataLength, len);
|
||||
MSC_BOT_csw.dDataResidue -= len;
|
||||
MSC_BOT_csw.bStatus = CSW_CMD_PASSED;
|
||||
MSC_BOT_State = BOT_SEND_DATA;
|
||||
|
||||
DCD_EP_Tx (pdev, MSC_IN_EP, buf, len);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_SendCSW
|
||||
* Send the Command Status Wrapper
|
||||
* @param pdev: device instance
|
||||
* @param status : CSW status
|
||||
* @retval None
|
||||
*/
|
||||
void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t CSW_Status)
|
||||
{
|
||||
MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE;
|
||||
MSC_BOT_csw.bStatus = CSW_Status;
|
||||
MSC_BOT_State = BOT_IDLE;
|
||||
|
||||
DCD_EP_Tx (pdev,
|
||||
MSC_IN_EP,
|
||||
(uint8_t *)&MSC_BOT_csw,
|
||||
BOT_CSW_LENGTH);
|
||||
|
||||
/* Prapare EP to Receive next Cmd */
|
||||
DCD_EP_PrepareRx (pdev,
|
||||
MSC_OUT_EP,
|
||||
(uint8_t *)&MSC_BOT_cbw,
|
||||
BOT_CBW_LENGTH);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_Abort
|
||||
* Abort the current transfer
|
||||
* @param pdev: device instance
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static void MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev)
|
||||
{
|
||||
|
||||
if ((MSC_BOT_cbw.bmFlags == 0) &&
|
||||
(MSC_BOT_cbw.dDataLength != 0) &&
|
||||
(MSC_BOT_Status == BOT_STATE_NORMAL) )
|
||||
{
|
||||
DCD_EP_Stall(pdev, MSC_OUT_EP );
|
||||
}
|
||||
DCD_EP_Stall(pdev, MSC_IN_EP);
|
||||
|
||||
if(MSC_BOT_Status == BOT_STATE_ERROR)
|
||||
{
|
||||
DCD_EP_PrepareRx (pdev,
|
||||
MSC_OUT_EP,
|
||||
(uint8_t *)&MSC_BOT_cbw,
|
||||
BOT_CBW_LENGTH);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief MSC_BOT_CplClrFeature
|
||||
* Complete the clear feature request
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint index
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum)
|
||||
{
|
||||
if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */
|
||||
{
|
||||
DCD_EP_Stall(pdev, MSC_IN_EP);
|
||||
MSC_BOT_Status = BOT_STATE_NORMAL;
|
||||
}
|
||||
else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY))
|
||||
{
|
||||
MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
|
||||
}
|
||||
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,153 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_bot.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header for the usbd_msc_bot.c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
||||
#include "usbd_core.h"
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_MSC_BOT_H
|
||||
#define __USBD_MSC_BOT_H
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MSC_BOT
|
||||
* @brief This file is the Header file for usbd_bot.c
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
#define BOT_IDLE 0 /* Idle state */
|
||||
#define BOT_DATA_OUT 1 /* Data Out state */
|
||||
#define BOT_DATA_IN 2 /* Data In state */
|
||||
#define BOT_LAST_DATA_IN 3 /* Last Data In Last */
|
||||
#define BOT_SEND_DATA 4 /* Send Immediate data */
|
||||
|
||||
#define BOT_CBW_SIGNATURE 0x43425355
|
||||
#define BOT_CSW_SIGNATURE 0x53425355
|
||||
#define BOT_CBW_LENGTH 31
|
||||
#define BOT_CSW_LENGTH 13
|
||||
|
||||
/* CSW Status Definitions */
|
||||
#define CSW_CMD_PASSED 0x00
|
||||
#define CSW_CMD_FAILED 0x01
|
||||
#define CSW_PHASE_ERROR 0x02
|
||||
|
||||
/* BOT Status */
|
||||
#define BOT_STATE_NORMAL 0
|
||||
#define BOT_STATE_RECOVERY 1
|
||||
#define BOT_STATE_ERROR 2
|
||||
|
||||
|
||||
#define DIR_IN 0
|
||||
#define DIR_OUT 1
|
||||
#define BOTH_DIR 2
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MSC_CORE_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct _MSC_BOT_CBW
|
||||
{
|
||||
uint32_t dSignature;
|
||||
uint32_t dTag;
|
||||
uint32_t dDataLength;
|
||||
uint8_t bmFlags;
|
||||
uint8_t bLUN;
|
||||
uint8_t bCBLength;
|
||||
uint8_t CB[16];
|
||||
}
|
||||
MSC_BOT_CBW_TypeDef;
|
||||
|
||||
|
||||
typedef struct _MSC_BOT_CSW
|
||||
{
|
||||
uint32_t dSignature;
|
||||
uint32_t dTag;
|
||||
uint32_t dDataResidue;
|
||||
uint8_t bStatus;
|
||||
}
|
||||
MSC_BOT_CSW_TypeDef;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_CORE_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern uint8_t MSC_BOT_Data[];
|
||||
extern uint16_t MSC_BOT_DataLen;
|
||||
extern uint8_t MSC_BOT_State;
|
||||
extern uint8_t MSC_BOT_BurstMode;
|
||||
extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw;
|
||||
extern MSC_BOT_CSW_TypeDef MSC_BOT_csw;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup USBD_CORE_Exported_FunctionsPrototypes
|
||||
* @{
|
||||
*/
|
||||
void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev);
|
||||
void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev);
|
||||
void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev);
|
||||
void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
|
||||
void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
|
||||
void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t CSW_Status);
|
||||
|
||||
void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t epnum);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USBD_MSC_BOT_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_conf.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief USB Device configuration file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_CONF__H__
|
||||
#define __USBD_CONF__H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
//#define USBD_CFG_MAX_NUM 1
|
||||
//#define USBD_ITF_MAX_NUM 1
|
||||
|
||||
//#define USBD_SELF_POWERED
|
||||
|
||||
//#define USB_MAX_STR_DESC_SIZ 64
|
||||
|
||||
/* Class Layer Parameter */
|
||||
|
||||
#define MSC_IN_EP 0x81
|
||||
#define MSC_OUT_EP 0x01
|
||||
#ifdef USE_USB_OTG_HS
|
||||
#ifdef USE_ULPI_PHY
|
||||
#define MSC_MAX_PACKET 512
|
||||
#else
|
||||
#define MSC_MAX_PACKET 64
|
||||
#endif
|
||||
#else /*USE_USB_OTG_FS*/
|
||||
#define MSC_MAX_PACKET 64
|
||||
#endif
|
||||
|
||||
|
||||
#define MSC_MEDIA_PACKET 4096
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CONF_Exported_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CONF_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif //__USBD_CONF__H__
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,497 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_core.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides all the MSC core functions.
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
* ===================================================================
|
||||
* MSC Class Description
|
||||
* ===================================================================
|
||||
* This module manages the MSC class V1.0 following the "Universal
|
||||
* Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
|
||||
* Sep. 31, 1999".
|
||||
* This driver implements the following aspects of the specification:
|
||||
* - Bulk-Only Transport protocol
|
||||
* - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
|
||||
*
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_msc_mem.h"
|
||||
#include "usbd_msc_core.h"
|
||||
#include "usbd_msc_bot.h"
|
||||
#include "usbd_msc_conf.h"
|
||||
#include "usbd_req.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_CORE
|
||||
* @brief Mass storage core module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MSC_CORE_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_CORE_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_CORE_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_CORE_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
uint8_t USBD_MSC_Init (void *pdev,
|
||||
uint8_t cfgidx);
|
||||
|
||||
uint8_t USBD_MSC_DeInit (void *pdev,
|
||||
uint8_t cfgidx);
|
||||
|
||||
uint8_t USBD_MSC_Setup (void *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
uint8_t USBD_MSC_DataIn (void *pdev,
|
||||
uint8_t epnum);
|
||||
|
||||
|
||||
uint8_t USBD_MSC_DataOut (void *pdev,
|
||||
uint8_t epnum);
|
||||
|
||||
uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed,
|
||||
uint16_t *length);
|
||||
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed,
|
||||
uint16_t *length);
|
||||
#endif
|
||||
|
||||
|
||||
uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ];
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_CORE_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
USBD_Class_cb_TypeDef USBD_MSC_cb =
|
||||
{
|
||||
USBD_MSC_Init,
|
||||
USBD_MSC_DeInit,
|
||||
USBD_MSC_Setup,
|
||||
NULL, /*EP0_TxSent*/
|
||||
NULL, /*EP0_RxReady*/
|
||||
USBD_MSC_DataIn,
|
||||
USBD_MSC_DataOut,
|
||||
NULL, /*SOF */
|
||||
NULL,
|
||||
NULL,
|
||||
USBD_MSC_GetCfgDesc,
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
USBD_MSC_GetOtherCfgDesc,
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
/* USB Mass storage device Configuration Descriptor */
|
||||
/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
|
||||
__ALIGN_BEGIN uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END =
|
||||
{
|
||||
|
||||
0x09, /* bLength: Configuation Descriptor size */
|
||||
USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
|
||||
USB_MSC_CONFIG_DESC_SIZ,
|
||||
|
||||
0x00,
|
||||
0x01, /* bNumInterfaces: 1 interface */
|
||||
0x01, /* bConfigurationValue: */
|
||||
0x04, /* iConfiguration: */
|
||||
0xC0, /* bmAttributes: */
|
||||
0x32, /* MaxPower 100 mA */
|
||||
|
||||
/******************** Mass Storage interface ********************/
|
||||
0x09, /* bLength: Interface Descriptor size */
|
||||
0x04, /* bDescriptorType: */
|
||||
0x00, /* bInterfaceNumber: Number of Interface */
|
||||
0x00, /* bAlternateSetting: Alternate setting */
|
||||
0x02, /* bNumEndpoints*/
|
||||
0x08, /* bInterfaceClass: MSC Class */
|
||||
0x06, /* bInterfaceSubClass : SCSI transparent*/
|
||||
0x50, /* nInterfaceProtocol */
|
||||
0x05, /* iInterface: */
|
||||
/******************** Mass Storage Endpoints ********************/
|
||||
0x07, /*Endpoint descriptor length = 7*/
|
||||
0x05, /*Endpoint descriptor type */
|
||||
MSC_IN_EP, /*Endpoint address (IN, address 1) */
|
||||
0x02, /*Bulk endpoint type */
|
||||
LOBYTE(MSC_MAX_PACKET),
|
||||
HIBYTE(MSC_MAX_PACKET),
|
||||
0x00, /*Polling interval in milliseconds */
|
||||
|
||||
0x07, /*Endpoint descriptor length = 7 */
|
||||
0x05, /*Endpoint descriptor type */
|
||||
MSC_OUT_EP, /*Endpoint address (OUT, address 1) */
|
||||
0x02, /*Bulk endpoint type */
|
||||
LOBYTE(MSC_MAX_PACKET),
|
||||
HIBYTE(MSC_MAX_PACKET),
|
||||
0x00 /*Polling interval in milliseconds*/
|
||||
};
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t USBD_MSC_OtherCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END =
|
||||
{
|
||||
|
||||
0x09, /* bLength: Configuation Descriptor size */
|
||||
USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION,
|
||||
USB_MSC_CONFIG_DESC_SIZ,
|
||||
|
||||
0x00,
|
||||
0x01, /* bNumInterfaces: 1 interface */
|
||||
0x01, /* bConfigurationValue: */
|
||||
0x04, /* iConfiguration: */
|
||||
0xC0, /* bmAttributes: */
|
||||
0x32, /* MaxPower 100 mA */
|
||||
|
||||
/******************** Mass Storage interface ********************/
|
||||
0x09, /* bLength: Interface Descriptor size */
|
||||
0x04, /* bDescriptorType: */
|
||||
0x00, /* bInterfaceNumber: Number of Interface */
|
||||
0x00, /* bAlternateSetting: Alternate setting */
|
||||
0x02, /* bNumEndpoints*/
|
||||
0x08, /* bInterfaceClass: MSC Class */
|
||||
0x06, /* bInterfaceSubClass : SCSI transparent command set*/
|
||||
0x50, /* nInterfaceProtocol */
|
||||
0x05, /* iInterface: */
|
||||
/******************** Mass Storage Endpoints ********************/
|
||||
0x07, /*Endpoint descriptor length = 7*/
|
||||
0x05, /*Endpoint descriptor type */
|
||||
MSC_IN_EP, /*Endpoint address (IN, address 1) */
|
||||
0x02, /*Bulk endpoint type */
|
||||
0x40,
|
||||
0x00,
|
||||
0x00, /*Polling interval in milliseconds */
|
||||
|
||||
0x07, /*Endpoint descriptor length = 7 */
|
||||
0x05, /*Endpoint descriptor type */
|
||||
MSC_OUT_EP, /*Endpoint address (OUT, address 1) */
|
||||
0x02, /*Bulk endpoint type */
|
||||
0x40,
|
||||
0x00,
|
||||
0x00 /*Polling interval in milliseconds*/
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_CORE_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief USBD_MSC_Init
|
||||
* Initialize the mass storage configuration
|
||||
* @param pdev: device instance
|
||||
* @param cfgidx: configuration index
|
||||
* @retval status
|
||||
*/
|
||||
uint8_t USBD_MSC_Init (void *pdev,
|
||||
uint8_t cfgidx)
|
||||
{
|
||||
USBD_MSC_DeInit(pdev , cfgidx );
|
||||
|
||||
/* Open EP IN */
|
||||
DCD_EP_Open(pdev,
|
||||
MSC_IN_EP,
|
||||
MSC_EPIN_SIZE,
|
||||
USB_OTG_EP_BULK);
|
||||
|
||||
/* Open EP OUT */
|
||||
DCD_EP_Open(pdev,
|
||||
MSC_OUT_EP,
|
||||
MSC_EPOUT_SIZE,
|
||||
USB_OTG_EP_BULK);
|
||||
|
||||
/* Init the BOT layer */
|
||||
MSC_BOT_Init(pdev);
|
||||
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_MSC_DeInit
|
||||
* DeInitilaize the mass storage configuration
|
||||
* @param pdev: device instance
|
||||
* @param cfgidx: configuration index
|
||||
* @retval status
|
||||
*/
|
||||
uint8_t USBD_MSC_DeInit (void *pdev,
|
||||
uint8_t cfgidx)
|
||||
{
|
||||
/* Close MSC EPs */
|
||||
DCD_EP_Close (pdev , MSC_IN_EP);
|
||||
DCD_EP_Close (pdev , MSC_OUT_EP);
|
||||
|
||||
/* Un Init the BOT layer */
|
||||
MSC_BOT_DeInit(pdev);
|
||||
return USBD_OK;
|
||||
}
|
||||
/**
|
||||
* @brief USBD_MSC_Setup
|
||||
* Handle the MSC specific requests
|
||||
* @param pdev: device instance
|
||||
* @param req: USB request
|
||||
* @retval status
|
||||
*/
|
||||
uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req)
|
||||
{
|
||||
|
||||
switch (req->bmRequest & USB_REQ_TYPE_MASK)
|
||||
{
|
||||
|
||||
/* Class request */
|
||||
case USB_REQ_TYPE_CLASS :
|
||||
switch (req->bRequest)
|
||||
{
|
||||
case BOT_GET_MAX_LUN :
|
||||
|
||||
if((req->wValue == 0) &&
|
||||
(req->wLength == 1) &&
|
||||
((req->bmRequest & 0x80) == 0x80))
|
||||
{
|
||||
USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun();
|
||||
if(USBD_MSC_MaxLun > 0)
|
||||
{
|
||||
USBD_CtlSendData (pdev,
|
||||
&USBD_MSC_MaxLun,
|
||||
1);
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
return USBD_FAIL;
|
||||
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
return USBD_FAIL;
|
||||
}
|
||||
break;
|
||||
|
||||
case BOT_RESET :
|
||||
if((req->wValue == 0) &&
|
||||
(req->wLength == 0) &&
|
||||
((req->bmRequest & 0x80) != 0x80))
|
||||
{
|
||||
MSC_BOT_Reset(pdev);
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
return USBD_FAIL;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
return USBD_FAIL;
|
||||
}
|
||||
break;
|
||||
/* Interface & Endpoint request */
|
||||
case USB_REQ_TYPE_STANDARD:
|
||||
switch (req->bRequest)
|
||||
{
|
||||
case USB_REQ_GET_INTERFACE :
|
||||
USBD_CtlSendData (pdev,
|
||||
&USBD_MSC_AltSet,
|
||||
1);
|
||||
break;
|
||||
|
||||
case USB_REQ_SET_INTERFACE :
|
||||
USBD_MSC_AltSet = (uint8_t)(req->wValue);
|
||||
break;
|
||||
|
||||
case USB_REQ_CLEAR_FEATURE:
|
||||
|
||||
/* Flush the FIFO and Clear the stall status */
|
||||
DCD_EP_Flush(pdev, (uint8_t)req->wIndex);
|
||||
|
||||
/* Re-activate the EP */
|
||||
DCD_EP_Close (pdev , (uint8_t)req->wIndex);
|
||||
if((((uint8_t)req->wIndex) & 0x80) == 0x80)
|
||||
{
|
||||
DCD_EP_Open(pdev,
|
||||
((uint8_t)req->wIndex),
|
||||
MSC_EPIN_SIZE,
|
||||
USB_OTG_EP_BULK);
|
||||
}
|
||||
else
|
||||
{
|
||||
DCD_EP_Open(pdev,
|
||||
((uint8_t)req->wIndex),
|
||||
MSC_EPOUT_SIZE,
|
||||
USB_OTG_EP_BULK);
|
||||
}
|
||||
|
||||
/* Handle BOT error */
|
||||
MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
|
||||
break;
|
||||
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_MSC_DataIn
|
||||
* handle data IN Stage
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint index
|
||||
* @retval status
|
||||
*/
|
||||
uint8_t USBD_MSC_DataIn (void *pdev,
|
||||
uint8_t epnum)
|
||||
{
|
||||
MSC_BOT_DataIn(pdev , epnum);
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_MSC_DataOut
|
||||
* handle data OUT Stage
|
||||
* @param pdev: device instance
|
||||
* @param epnum: endpoint index
|
||||
* @retval status
|
||||
*/
|
||||
uint8_t USBD_MSC_DataOut (void *pdev,
|
||||
uint8_t epnum)
|
||||
{
|
||||
MSC_BOT_DataOut(pdev , epnum);
|
||||
return USBD_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_MSC_GetCfgDesc
|
||||
* return configuration descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer data length
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length)
|
||||
{
|
||||
*length = sizeof (USBD_MSC_CfgDesc);
|
||||
return USBD_MSC_CfgDesc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_MSC_GetOtherCfgDesc
|
||||
* return other speed configuration descriptor
|
||||
* @param speed : current device speed
|
||||
* @param length : pointer data length
|
||||
* @retval pointer to descriptor buffer
|
||||
*/
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed,
|
||||
uint16_t *length)
|
||||
{
|
||||
*length = sizeof (USBD_MSC_OtherCfgDesc);
|
||||
return USBD_MSC_OtherCfgDesc;
|
||||
}
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_core.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header for the usbd_msc_core.c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef _USB_MSC_CORE_H_
|
||||
#define _USB_MSC_CORE_H_
|
||||
|
||||
#include "usbd_ioreq.h"
|
||||
|
||||
/** @addtogroup USBD_MSC_BOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_MSC
|
||||
* @brief This file is the Header file for USBD_msc.c
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_BOT_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
#define BOT_GET_MAX_LUN 0xFE
|
||||
#define BOT_RESET 0xFF
|
||||
#define USB_MSC_CONFIG_DESC_SIZ 32
|
||||
|
||||
#define MSC_EPIN_SIZE MSC_MAX_PACKET
|
||||
#define MSC_EPOUT_SIZE MSC_MAX_PACKET
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_CORE_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern USBD_Class_cb_TypeDef USBD_MSC_cb;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif // _USB_MSC_CORE_H_
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_data.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides all the vital inquiry pages and sense data.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_msc_data.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_DATA
|
||||
* @brief Mass storage info/data module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MSC_DATA_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_DATA_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_DATA_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_DATA_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* USB Mass storage Page 0 Inquiry Data */
|
||||
const uint8_t MSC_Page00_Inquiry_Data[] = {//7
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
(LENGTH_INQUIRY_PAGE00 - 4),
|
||||
0x00,
|
||||
0x80,
|
||||
0x83
|
||||
};
|
||||
/* USB Mass storage sense 6 Data */
|
||||
const uint8_t MSC_Mode_Sense6_data[] = {
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
/* USB Mass storage sense 10 Data */
|
||||
const uint8_t MSC_Mode_Sense10_data[] = {
|
||||
0x00,
|
||||
0x06,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_DATA_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_DATA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_data.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header for the usbd_msc_data.c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
||||
#ifndef _USBD_MSC_DATA_H_
|
||||
#define _USBD_MSC_DATA_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
//#include "usbd_conf.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_INFO
|
||||
* @brief general defines for the usb device library file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USB_INFO_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
#define MODE_SENSE6_LEN 8
|
||||
#define MODE_SENSE10_LEN 8
|
||||
#define LENGTH_INQUIRY_PAGE00 7
|
||||
#define LENGTH_FORMAT_CAPACITIES 20
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_INFO_Exported_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_INFO_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_INFO_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern const uint8_t MSC_Page00_Inquiry_Data[];
|
||||
extern const uint8_t MSC_Mode_Sense6_data[];
|
||||
extern const uint8_t MSC_Mode_Sense10_data[] ;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_INFO_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* _USBD_MSC_DATA_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_mem.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header for the STORAGE DISK file file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
||||
#ifndef __USBD_MEM_H
|
||||
#define __USBD_MEM_H
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
#include "usbd_def.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_MEM
|
||||
* @brief header file for the storage disk file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_MEM_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
#define USBD_STD_INQUIRY_LENGTH 36
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_MEM_Exported_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct _USBD_STORAGE
|
||||
{
|
||||
int8_t (* Init) (uint8_t lun);
|
||||
int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size);
|
||||
int8_t (* IsReady) (uint8_t lun);
|
||||
int8_t (* IsWriteProtected) (uint8_t lun);
|
||||
int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
|
||||
int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
|
||||
int8_t (* GetMaxLun)(void);
|
||||
int8_t *pInquiry;
|
||||
|
||||
}USBD_STORAGE_cb_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_MEM_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_MEM_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_MEM_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
extern USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USBD_MEM_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,729 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_scsi.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides all the USBD SCSI layer functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_msc_bot.h"
|
||||
#include "usbd_msc_scsi.h"
|
||||
#include "usbd_msc_mem.h"
|
||||
#include "usbd_msc_data.h"
|
||||
#include "usbd_msc_conf.h"
|
||||
|
||||
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_SCSI
|
||||
* @brief Mass storage SCSI layer module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MSC_SCSI_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_SCSI_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_SCSI_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_SCSI_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH];
|
||||
uint8_t SCSI_Sense_Head;
|
||||
uint8_t SCSI_Sense_Tail;
|
||||
|
||||
uint32_t SCSI_blk_size;
|
||||
uint32_t SCSI_blk_nbr;
|
||||
|
||||
uint32_t SCSI_blk_addr;
|
||||
uint32_t SCSI_blk_len;
|
||||
|
||||
USB_OTG_CORE_HANDLE *cdev;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_SCSI_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_Write10(uint8_t lun , uint8_t *params);
|
||||
static int8_t SCSI_Read10(uint8_t lun , uint8_t *params);
|
||||
static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params);
|
||||
static int8_t SCSI_CheckAddressRange (uint8_t lun ,
|
||||
uint32_t blk_offset ,
|
||||
uint16_t blk_nbr);
|
||||
static int8_t SCSI_ProcessRead (uint8_t lun);
|
||||
|
||||
static int8_t SCSI_ProcessWrite (uint8_t lun);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup MSC_SCSI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief SCSI_ProcessCmd
|
||||
* Process SCSI commands
|
||||
* @param pdev: device instance
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t lun,
|
||||
uint8_t *params)
|
||||
{
|
||||
cdev = pdev;
|
||||
|
||||
switch (params[0])
|
||||
{
|
||||
case SCSI_TEST_UNIT_READY:
|
||||
return SCSI_TestUnitReady(lun, params);
|
||||
|
||||
case SCSI_REQUEST_SENSE:
|
||||
return SCSI_RequestSense (lun, params);
|
||||
case SCSI_INQUIRY:
|
||||
return SCSI_Inquiry(lun, params);
|
||||
|
||||
case SCSI_START_STOP_UNIT:
|
||||
return SCSI_StartStopUnit(lun, params);
|
||||
|
||||
case SCSI_ALLOW_MEDIUM_REMOVAL:
|
||||
return SCSI_StartStopUnit(lun, params);
|
||||
|
||||
case SCSI_MODE_SENSE6:
|
||||
return SCSI_ModeSense6 (lun, params);
|
||||
|
||||
case SCSI_MODE_SENSE10:
|
||||
return SCSI_ModeSense10 (lun, params);
|
||||
|
||||
case SCSI_READ_FORMAT_CAPACITIES:
|
||||
return SCSI_ReadFormatCapacity(lun, params);
|
||||
|
||||
case SCSI_READ_CAPACITY10:
|
||||
return SCSI_ReadCapacity10(lun, params);
|
||||
|
||||
case SCSI_READ10:
|
||||
return SCSI_Read10(lun, params);
|
||||
|
||||
case SCSI_WRITE10:
|
||||
return SCSI_Write10(lun, params);
|
||||
|
||||
case SCSI_VERIFY10:
|
||||
return SCSI_Verify10(lun, params);
|
||||
|
||||
default:
|
||||
SCSI_SenseCode(lun,
|
||||
ILLEGAL_REQUEST,
|
||||
INVALID_CDB);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief SCSI_TestUnitReady
|
||||
* Process SCSI Test Unit Ready Command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params)
|
||||
{
|
||||
|
||||
/* case 9 : Hi > D0 */
|
||||
if (MSC_BOT_cbw.dDataLength != 0)
|
||||
{
|
||||
SCSI_SenseCode(MSC_BOT_cbw.bLUN,
|
||||
ILLEGAL_REQUEST,
|
||||
INVALID_CDB);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if(USBD_STORAGE_fops->IsReady(lun) !=0 )
|
||||
{
|
||||
SCSI_SenseCode(lun,
|
||||
NOT_READY,
|
||||
MEDIUM_NOT_PRESENT);
|
||||
return -1;
|
||||
}
|
||||
MSC_BOT_DataLen = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_Inquiry
|
||||
* Process Inquiry command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params)
|
||||
{
|
||||
uint8_t* pPage;
|
||||
uint16_t len;
|
||||
|
||||
if (params[1] & 0x01)/*Evpd is set*/
|
||||
{
|
||||
pPage = (uint8_t *)MSC_Page00_Inquiry_Data;
|
||||
len = LENGTH_INQUIRY_PAGE00;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH];
|
||||
len = pPage[4] + 5;
|
||||
|
||||
if (params[4] <= len)
|
||||
{
|
||||
len = params[4];
|
||||
}
|
||||
}
|
||||
MSC_BOT_DataLen = len;
|
||||
|
||||
while (len)
|
||||
{
|
||||
len--;
|
||||
MSC_BOT_Data[len] = pPage[len];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_ReadCapacity10
|
||||
* Process Read Capacity 10 command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params)
|
||||
{
|
||||
|
||||
if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0)
|
||||
{
|
||||
SCSI_SenseCode(lun,
|
||||
NOT_READY,
|
||||
MEDIUM_NOT_PRESENT);
|
||||
return -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1) >> 24); // dpgeorge added paren
|
||||
MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1) >> 16); // dpgeorge added paren
|
||||
MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1) >> 8); // dpgeorge added paren
|
||||
MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1);
|
||||
|
||||
MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24);
|
||||
MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16);
|
||||
MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8);
|
||||
MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size);
|
||||
|
||||
MSC_BOT_DataLen = 8;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief SCSI_ReadFormatCapacity
|
||||
* Process Read Format Capacity command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params)
|
||||
{
|
||||
|
||||
uint32_t blk_size;
|
||||
uint32_t blk_nbr;
|
||||
uint16_t i;
|
||||
|
||||
for(i=0 ; i < 12 ; i++)
|
||||
{
|
||||
MSC_BOT_Data[i] = 0;
|
||||
}
|
||||
|
||||
if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0)
|
||||
{
|
||||
SCSI_SenseCode(lun,
|
||||
NOT_READY,
|
||||
MEDIUM_NOT_PRESENT);
|
||||
return -1;
|
||||
}
|
||||
else
|
||||
{
|
||||
MSC_BOT_Data[3] = 0x08;
|
||||
MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1) >> 24); // dpgeorge added paren
|
||||
MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1) >> 16); // dpgeorge added paren
|
||||
MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1) >> 8); // dpgeorge added paren
|
||||
MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1);
|
||||
|
||||
MSC_BOT_Data[8] = 0x02;
|
||||
MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16);
|
||||
MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8);
|
||||
MSC_BOT_Data[11] = (uint8_t)(blk_size);
|
||||
|
||||
MSC_BOT_DataLen = 12;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief SCSI_ModeSense6
|
||||
* Process Mode Sense6 command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params)
|
||||
{
|
||||
|
||||
uint16_t len = 8 ;
|
||||
MSC_BOT_DataLen = len;
|
||||
|
||||
while (len)
|
||||
{
|
||||
len--;
|
||||
MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_ModeSense10
|
||||
* Process Mode Sense10 command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params)
|
||||
{
|
||||
uint16_t len = 8;
|
||||
|
||||
MSC_BOT_DataLen = len;
|
||||
|
||||
while (len)
|
||||
{
|
||||
len--;
|
||||
MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_RequestSense
|
||||
* Process Request Sense command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params)
|
||||
{
|
||||
uint8_t i;
|
||||
|
||||
for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++)
|
||||
{
|
||||
MSC_BOT_Data[i] = 0;
|
||||
}
|
||||
|
||||
MSC_BOT_Data[0] = 0x70;
|
||||
MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6;
|
||||
|
||||
if((SCSI_Sense_Head != SCSI_Sense_Tail)) {
|
||||
|
||||
MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey;
|
||||
MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ;
|
||||
MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC;
|
||||
SCSI_Sense_Head++;
|
||||
|
||||
if (SCSI_Sense_Head == SENSE_LIST_DEEPTH)
|
||||
{
|
||||
SCSI_Sense_Head = 0;
|
||||
}
|
||||
}
|
||||
MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN;
|
||||
|
||||
if (params[4] <= REQUEST_SENSE_DATA_LEN)
|
||||
{
|
||||
MSC_BOT_DataLen = params[4];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_SenseCode
|
||||
* Load the last error code in the error list
|
||||
* @param lun: Logical unit number
|
||||
* @param sKey: Sense Key
|
||||
* @param ASC: Additional Sense Key
|
||||
* @retval none
|
||||
|
||||
*/
|
||||
void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC)
|
||||
{
|
||||
SCSI_Sense[SCSI_Sense_Tail].Skey = sKey;
|
||||
SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8;
|
||||
SCSI_Sense_Tail++;
|
||||
if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH)
|
||||
{
|
||||
SCSI_Sense_Tail = 0;
|
||||
}
|
||||
}
|
||||
/**
|
||||
* @brief SCSI_StartStopUnit
|
||||
* Process Start Stop Unit command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params)
|
||||
{
|
||||
MSC_BOT_DataLen = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_Read10
|
||||
* Process Read10 command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_Read10(uint8_t lun , uint8_t *params)
|
||||
{
|
||||
if(MSC_BOT_State == BOT_IDLE) /* Idle */
|
||||
{
|
||||
|
||||
/* case 10 : Ho <> Di */
|
||||
|
||||
if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80)
|
||||
{
|
||||
SCSI_SenseCode(MSC_BOT_cbw.bLUN,
|
||||
ILLEGAL_REQUEST,
|
||||
INVALID_CDB);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if(USBD_STORAGE_fops->IsReady(lun) !=0 )
|
||||
{
|
||||
SCSI_SenseCode(lun,
|
||||
NOT_READY,
|
||||
MEDIUM_NOT_PRESENT);
|
||||
return -1;
|
||||
}
|
||||
|
||||
SCSI_blk_addr = (params[2] << 24) | \
|
||||
(params[3] << 16) | \
|
||||
(params[4] << 8) | \
|
||||
params[5];
|
||||
|
||||
SCSI_blk_len = (params[7] << 8) | \
|
||||
params[8];
|
||||
|
||||
|
||||
|
||||
if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
|
||||
{
|
||||
return -1; /* error */
|
||||
}
|
||||
|
||||
MSC_BOT_State = BOT_DATA_IN;
|
||||
SCSI_blk_addr *= SCSI_blk_size;
|
||||
SCSI_blk_len *= SCSI_blk_size;
|
||||
|
||||
/* cases 4,5 : Hi <> Dn */
|
||||
if (MSC_BOT_cbw.dDataLength != SCSI_blk_len)
|
||||
{
|
||||
SCSI_SenseCode(MSC_BOT_cbw.bLUN,
|
||||
ILLEGAL_REQUEST,
|
||||
INVALID_CDB);
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
MSC_BOT_DataLen = MSC_MEDIA_PACKET;
|
||||
|
||||
return SCSI_ProcessRead(lun);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_Write10
|
||||
* Process Write10 command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params)
|
||||
{
|
||||
if (MSC_BOT_State == BOT_IDLE) /* Idle */
|
||||
{
|
||||
|
||||
/* case 8 : Hi <> Do */
|
||||
|
||||
if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80)
|
||||
{
|
||||
SCSI_SenseCode(MSC_BOT_cbw.bLUN,
|
||||
ILLEGAL_REQUEST,
|
||||
INVALID_CDB);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check whether Media is ready */
|
||||
if(USBD_STORAGE_fops->IsReady(lun) !=0 )
|
||||
{
|
||||
SCSI_SenseCode(lun,
|
||||
NOT_READY,
|
||||
MEDIUM_NOT_PRESENT);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check If media is write-protected */
|
||||
if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 )
|
||||
{
|
||||
SCSI_SenseCode(lun,
|
||||
NOT_READY,
|
||||
WRITE_PROTECTED);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
SCSI_blk_addr = (params[2] << 24) | \
|
||||
(params[3] << 16) | \
|
||||
(params[4] << 8) | \
|
||||
params[5];
|
||||
SCSI_blk_len = (params[7] << 8) | \
|
||||
params[8];
|
||||
|
||||
/* check if LBA address is in the right range */
|
||||
if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
|
||||
{
|
||||
return -1; /* error */
|
||||
}
|
||||
|
||||
SCSI_blk_addr *= SCSI_blk_size;
|
||||
SCSI_blk_len *= SCSI_blk_size;
|
||||
|
||||
/* cases 3,11,13 : Hn,Ho <> D0 */
|
||||
if (MSC_BOT_cbw.dDataLength != SCSI_blk_len)
|
||||
{
|
||||
SCSI_SenseCode(MSC_BOT_cbw.bLUN,
|
||||
ILLEGAL_REQUEST,
|
||||
INVALID_CDB);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Prepare EP to receive first data packet */
|
||||
MSC_BOT_State = BOT_DATA_OUT;
|
||||
DCD_EP_PrepareRx (cdev,
|
||||
MSC_OUT_EP,
|
||||
MSC_BOT_Data,
|
||||
MIN (SCSI_blk_len, MSC_MEDIA_PACKET));
|
||||
}
|
||||
else /* Write Process ongoing */
|
||||
{
|
||||
return SCSI_ProcessWrite(lun);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief SCSI_Verify10
|
||||
* Process Verify10 command
|
||||
* @param lun: Logical unit number
|
||||
* @param params: Command parameters
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){
|
||||
if ((params[1]& 0x02) == 0x02)
|
||||
{
|
||||
SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
|
||||
return -1; /* Error, Verify Mode Not supported*/
|
||||
}
|
||||
|
||||
if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
|
||||
{
|
||||
return -1; /* error */
|
||||
}
|
||||
MSC_BOT_DataLen = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_CheckAddressRange
|
||||
* Check address range
|
||||
* @param lun: Logical unit number
|
||||
* @param blk_offset: first block address
|
||||
* @param blk_nbr: number of block to be processed
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr)
|
||||
{
|
||||
|
||||
if ((blk_offset + blk_nbr) > SCSI_blk_nbr )
|
||||
{
|
||||
SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE);
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_ProcessRead
|
||||
* Handle Read Process
|
||||
* @param lun: Logical unit number
|
||||
* @retval status
|
||||
*/
|
||||
static int8_t SCSI_ProcessRead (uint8_t lun)
|
||||
{
|
||||
uint32_t len;
|
||||
|
||||
len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET);
|
||||
|
||||
if( USBD_STORAGE_fops->Read(lun ,
|
||||
MSC_BOT_Data,
|
||||
SCSI_blk_addr / SCSI_blk_size,
|
||||
len / SCSI_blk_size) < 0)
|
||||
{
|
||||
|
||||
SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
DCD_EP_Tx (cdev,
|
||||
MSC_IN_EP,
|
||||
MSC_BOT_Data,
|
||||
len);
|
||||
|
||||
|
||||
SCSI_blk_addr += len;
|
||||
SCSI_blk_len -= len;
|
||||
|
||||
/* case 6 : Hi = Di */
|
||||
MSC_BOT_csw.dDataResidue -= len;
|
||||
|
||||
if (SCSI_blk_len == 0)
|
||||
{
|
||||
MSC_BOT_State = BOT_LAST_DATA_IN;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SCSI_ProcessWrite
|
||||
* Handle Write Process
|
||||
* @param lun: Logical unit number
|
||||
* @retval status
|
||||
*/
|
||||
|
||||
static int8_t SCSI_ProcessWrite (uint8_t lun)
|
||||
{
|
||||
uint32_t len;
|
||||
|
||||
len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET);
|
||||
|
||||
if(USBD_STORAGE_fops->Write(lun ,
|
||||
MSC_BOT_Data,
|
||||
SCSI_blk_addr / SCSI_blk_size,
|
||||
len / SCSI_blk_size) < 0)
|
||||
{
|
||||
SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
SCSI_blk_addr += len;
|
||||
SCSI_blk_len -= len;
|
||||
|
||||
/* case 12 : Ho = Do */
|
||||
MSC_BOT_csw.dDataResidue -= len;
|
||||
|
||||
if (SCSI_blk_len == 0)
|
||||
{
|
||||
MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Prapare EP to Receive next packet */
|
||||
DCD_EP_PrepareRx (cdev,
|
||||
MSC_OUT_EP,
|
||||
MSC_BOT_Data,
|
||||
MIN (SCSI_blk_len, MSC_MEDIA_PACKET));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_msc_scsi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header for the usbd_msc_scsi.c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_MSC_SCSI_H
|
||||
#define __USBD_MSC_SCSI_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_def.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_SCSI
|
||||
* @brief header file for the storage disk file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_SCSI_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SENSE_LIST_DEEPTH 4
|
||||
|
||||
/* SCSI Commands */
|
||||
#define SCSI_FORMAT_UNIT 0x04
|
||||
#define SCSI_INQUIRY 0x12
|
||||
#define SCSI_MODE_SELECT6 0x15
|
||||
#define SCSI_MODE_SELECT10 0x55
|
||||
#define SCSI_MODE_SENSE6 0x1A
|
||||
#define SCSI_MODE_SENSE10 0x5A
|
||||
#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E
|
||||
#define SCSI_READ6 0x08
|
||||
#define SCSI_READ10 0x28
|
||||
#define SCSI_READ12 0xA8
|
||||
#define SCSI_READ16 0x88
|
||||
|
||||
#define SCSI_READ_CAPACITY10 0x25
|
||||
#define SCSI_READ_CAPACITY16 0x9E
|
||||
|
||||
#define SCSI_REQUEST_SENSE 0x03
|
||||
#define SCSI_START_STOP_UNIT 0x1B
|
||||
#define SCSI_TEST_UNIT_READY 0x00
|
||||
#define SCSI_WRITE6 0x0A
|
||||
#define SCSI_WRITE10 0x2A
|
||||
#define SCSI_WRITE12 0xAA
|
||||
#define SCSI_WRITE16 0x8A
|
||||
|
||||
#define SCSI_VERIFY10 0x2F
|
||||
#define SCSI_VERIFY12 0xAF
|
||||
#define SCSI_VERIFY16 0x8F
|
||||
|
||||
#define SCSI_SEND_DIAGNOSTIC 0x1D
|
||||
#define SCSI_READ_FORMAT_CAPACITIES 0x23
|
||||
|
||||
#define NO_SENSE 0
|
||||
#define RECOVERED_ERROR 1
|
||||
#define NOT_READY 2
|
||||
#define MEDIUM_ERROR 3
|
||||
#define HARDWARE_ERROR 4
|
||||
#define ILLEGAL_REQUEST 5
|
||||
#define UNIT_ATTENTION 6
|
||||
#define DATA_PROTECT 7
|
||||
#define BLANK_CHECK 8
|
||||
#define VENDOR_SPECIFIC 9
|
||||
#define COPY_ABORTED 10
|
||||
#define ABORTED_COMMAND 11
|
||||
#define VOLUME_OVERFLOW 13
|
||||
#define MISCOMPARE 14
|
||||
|
||||
|
||||
#define INVALID_CDB 0x20
|
||||
#define INVALID_FIELED_IN_COMMAND 0x24
|
||||
#define PARAMETER_LIST_LENGTH_ERROR 0x1A
|
||||
#define INVALID_FIELD_IN_PARAMETER_LIST 0x26
|
||||
#define ADDRESS_OUT_OF_RANGE 0x21
|
||||
#define MEDIUM_NOT_PRESENT 0x3A
|
||||
#define MEDIUM_HAVE_CHANGED 0x28
|
||||
#define WRITE_PROTECTED 0x27
|
||||
#define UNRECOVERED_READ_ERROR 0x11
|
||||
#define WRITE_FAULT 0x03
|
||||
|
||||
#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C
|
||||
#define READ_CAPACITY10_DATA_LEN 0x08
|
||||
#define MODE_SENSE10_DATA_LEN 0x08
|
||||
#define MODE_SENSE6_DATA_LEN 0x04
|
||||
#define REQUEST_SENSE_DATA_LEN 0x12
|
||||
#define STANDARD_INQUIRY_DATA_LEN 0x24
|
||||
#define BLKVFY 0x04
|
||||
|
||||
extern uint8_t Page00_Inquiry_Data[];
|
||||
extern uint8_t Standard_Inquiry_Data[];
|
||||
extern uint8_t Standard_Inquiry_Data2[];
|
||||
extern uint8_t Mode_Sense6_data[];
|
||||
extern uint8_t Mode_Sense10_data[];
|
||||
extern uint8_t Scsi_Sense_Data[];
|
||||
extern uint8_t ReadCapacity10_Data[];
|
||||
extern uint8_t ReadFormatCapacity_Data [];
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_SCSI_Exported_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef struct _SENSE_ITEM {
|
||||
char Skey;
|
||||
union {
|
||||
struct _ASCs {
|
||||
char ASC;
|
||||
char ASCQ;
|
||||
}b;
|
||||
unsigned int ASC;
|
||||
char *pData;
|
||||
} w;
|
||||
} SCSI_Sense_TypeDef;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_SCSI_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_SCSI_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH];
|
||||
extern uint8_t SCSI_Sense_Head;
|
||||
extern uint8_t SCSI_Sense_Tail;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/** @defgroup USBD_SCSI_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev,
|
||||
uint8_t lun,
|
||||
uint8_t *cmd);
|
||||
|
||||
void SCSI_SenseCode(uint8_t lun,
|
||||
uint8_t sKey,
|
||||
uint8_t ASC);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USBD_MSC_SCSI_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,868 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_req.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides the standard USB requests following chapter 9.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_req.h"
|
||||
#include "usbd_ioreq.h"
|
||||
#include "usbd_desc.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_REQ
|
||||
* @brief USB standard requests module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_REQ_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_REQ_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_REQ_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_REQ_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
extern __IO USB_OTG_DCTL_TypeDef SET_TEST_MODE;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint32_t USBD_default_cfg __ALIGN_END = 0;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0;
|
||||
|
||||
#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED
|
||||
#if defined ( __ICCARM__ ) /*!< IAR Compiler */
|
||||
#pragma data_alignment=4
|
||||
#endif
|
||||
#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */
|
||||
__ALIGN_BEGIN uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] __ALIGN_END ;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_REQ_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
static uint8_t USBD_GetLen(uint8_t *buf);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_REQ_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_StdDevReq
|
||||
* Handle standard usb device requests
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
|
||||
{
|
||||
USBD_Status ret = USBD_OK;
|
||||
|
||||
switch (req->bRequest)
|
||||
{
|
||||
case USB_REQ_GET_DESCRIPTOR:
|
||||
|
||||
USBD_GetDescriptor (pdev, req) ;
|
||||
break;
|
||||
|
||||
case USB_REQ_SET_ADDRESS:
|
||||
USBD_SetAddress(pdev, req);
|
||||
break;
|
||||
|
||||
case USB_REQ_SET_CONFIGURATION:
|
||||
USBD_SetConfig (pdev , req);
|
||||
break;
|
||||
|
||||
case USB_REQ_GET_CONFIGURATION:
|
||||
USBD_GetConfig (pdev , req);
|
||||
break;
|
||||
|
||||
case USB_REQ_GET_STATUS:
|
||||
USBD_GetStatus (pdev , req);
|
||||
break;
|
||||
|
||||
|
||||
case USB_REQ_SET_FEATURE:
|
||||
USBD_SetFeature (pdev , req);
|
||||
break;
|
||||
|
||||
case USB_REQ_CLEAR_FEATURE:
|
||||
USBD_ClrFeature (pdev , req);
|
||||
break;
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_StdItfReq
|
||||
* Handle standard usb interface requests
|
||||
* @param pdev: USB OTG device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
|
||||
{
|
||||
USBD_Status ret = USBD_OK;
|
||||
|
||||
switch (pdev->dev.device_status)
|
||||
{
|
||||
case USB_OTG_CONFIGURED:
|
||||
|
||||
if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM)
|
||||
{
|
||||
pdev->dev.class_cb->Setup (pdev, req);
|
||||
|
||||
if((req->wLength == 0)&& (ret == USBD_OK))
|
||||
{
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_StdEPReq
|
||||
* Handle standard usb endpoint requests
|
||||
* @param pdev: USB OTG device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
|
||||
{
|
||||
|
||||
uint8_t ep_addr;
|
||||
USBD_Status ret = USBD_OK;
|
||||
|
||||
ep_addr = LOBYTE(req->wIndex);
|
||||
|
||||
switch (req->bRequest)
|
||||
{
|
||||
|
||||
case USB_REQ_SET_FEATURE :
|
||||
|
||||
switch (pdev->dev.device_status)
|
||||
{
|
||||
case USB_OTG_ADDRESSED:
|
||||
if ((ep_addr != 0x00) && (ep_addr != 0x80))
|
||||
{
|
||||
DCD_EP_Stall(pdev , ep_addr);
|
||||
}
|
||||
break;
|
||||
|
||||
case USB_OTG_CONFIGURED:
|
||||
if (req->wValue == USB_FEATURE_EP_HALT)
|
||||
{
|
||||
if ((ep_addr != 0x00) && (ep_addr != 0x80))
|
||||
{
|
||||
DCD_EP_Stall(pdev , ep_addr);
|
||||
|
||||
}
|
||||
}
|
||||
pdev->dev.class_cb->Setup (pdev, req);
|
||||
USBD_CtlSendStatus(pdev);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case USB_REQ_CLEAR_FEATURE :
|
||||
|
||||
switch (pdev->dev.device_status)
|
||||
{
|
||||
case USB_OTG_ADDRESSED:
|
||||
if ((ep_addr != 0x00) && (ep_addr != 0x80))
|
||||
{
|
||||
DCD_EP_Stall(pdev , ep_addr);
|
||||
}
|
||||
break;
|
||||
|
||||
case USB_OTG_CONFIGURED:
|
||||
if (req->wValue == USB_FEATURE_EP_HALT)
|
||||
{
|
||||
if ((ep_addr != 0x00) && (ep_addr != 0x80))
|
||||
{
|
||||
DCD_EP_ClrStall(pdev , ep_addr);
|
||||
pdev->dev.class_cb->Setup (pdev, req);
|
||||
}
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case USB_REQ_GET_STATUS:
|
||||
switch (pdev->dev.device_status)
|
||||
{
|
||||
case USB_OTG_ADDRESSED:
|
||||
if ((ep_addr != 0x00) && (ep_addr != 0x80))
|
||||
{
|
||||
DCD_EP_Stall(pdev , ep_addr);
|
||||
}
|
||||
break;
|
||||
|
||||
case USB_OTG_CONFIGURED:
|
||||
|
||||
|
||||
if ((ep_addr & 0x80)== 0x80)
|
||||
{
|
||||
if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall)
|
||||
{
|
||||
USBD_ep_status = 0x0001;
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_ep_status = 0x0000;
|
||||
}
|
||||
}
|
||||
else if ((ep_addr & 0x80)== 0x00)
|
||||
{
|
||||
if(pdev->dev.out_ep[ep_addr].is_stall)
|
||||
{
|
||||
USBD_ep_status = 0x0001;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
USBD_ep_status = 0x0000;
|
||||
}
|
||||
}
|
||||
USBD_CtlSendData (pdev,
|
||||
(uint8_t *)&USBD_ep_status,
|
||||
2);
|
||||
break;
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
/**
|
||||
* @brief USBD_GetDescriptor
|
||||
* Handle Get Descriptor requests
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
uint16_t len;
|
||||
uint8_t *pbuf;
|
||||
|
||||
|
||||
switch (req->wValue >> 8)
|
||||
{
|
||||
case USB_DESC_TYPE_DEVICE:
|
||||
pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->cfg.speed, &len);
|
||||
if ((req->wLength == 64) ||( pdev->dev.device_status == USB_OTG_DEFAULT))
|
||||
{
|
||||
len = 8;
|
||||
}
|
||||
break;
|
||||
|
||||
case USB_DESC_TYPE_CONFIGURATION:
|
||||
pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len);
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
if((pdev->cfg.speed == USB_OTG_SPEED_FULL )&&
|
||||
(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY))
|
||||
{
|
||||
pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len);
|
||||
}
|
||||
#endif
|
||||
pbuf[1] = USB_DESC_TYPE_CONFIGURATION;
|
||||
pdev->dev.pConfig_descriptor = pbuf;
|
||||
break;
|
||||
|
||||
case USB_DESC_TYPE_STRING:
|
||||
switch ((uint8_t)(req->wValue))
|
||||
{
|
||||
case USBD_IDX_LANGID_STR:
|
||||
pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->cfg.speed, &len);
|
||||
break;
|
||||
|
||||
case USBD_IDX_MFC_STR:
|
||||
pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->cfg.speed, &len);
|
||||
break;
|
||||
|
||||
case USBD_IDX_PRODUCT_STR:
|
||||
pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->cfg.speed, &len);
|
||||
break;
|
||||
|
||||
case USBD_IDX_SERIAL_STR:
|
||||
pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->cfg.speed, &len);
|
||||
break;
|
||||
|
||||
case USBD_IDX_CONFIG_STR:
|
||||
pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->cfg.speed, &len);
|
||||
break;
|
||||
|
||||
case USBD_IDX_INTERFACE_STR:
|
||||
pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->cfg.speed, &len);
|
||||
break;
|
||||
|
||||
default:
|
||||
#ifdef USB_SUPPORT_USER_STRING_DESC
|
||||
pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->cfg.speed, (req->wValue) , &len);
|
||||
break;
|
||||
#else
|
||||
USBD_CtlError(pdev , req);
|
||||
return;
|
||||
#endif /* USBD_CtlError(pdev , req); */
|
||||
}
|
||||
break;
|
||||
case USB_DESC_TYPE_DEVICE_QUALIFIER:
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
if(pdev->cfg.speed == USB_OTG_SPEED_HIGH )
|
||||
{
|
||||
|
||||
pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len);
|
||||
|
||||
USBD_DeviceQualifierDesc[4]= pbuf[14];
|
||||
USBD_DeviceQualifierDesc[5]= pbuf[15];
|
||||
USBD_DeviceQualifierDesc[6]= pbuf[16];
|
||||
|
||||
pbuf = USBD_DeviceQualifierDesc;
|
||||
len = USB_LEN_DEV_QUALIFIER_DESC;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
return;
|
||||
}
|
||||
#else
|
||||
USBD_CtlError(pdev , req);
|
||||
return;
|
||||
#endif
|
||||
|
||||
case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
|
||||
#ifdef USB_OTG_HS_CORE
|
||||
|
||||
if(pdev->cfg.speed == USB_OTG_SPEED_HIGH )
|
||||
{
|
||||
pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len);
|
||||
pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
return;
|
||||
}
|
||||
#else
|
||||
USBD_CtlError(pdev , req);
|
||||
return;
|
||||
#endif
|
||||
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
return;
|
||||
}
|
||||
|
||||
if((len != 0)&& (req->wLength != 0))
|
||||
{
|
||||
|
||||
len = MIN(len , req->wLength);
|
||||
|
||||
USBD_CtlSendData (pdev,
|
||||
pbuf,
|
||||
len);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_SetAddress
|
||||
* Set device address
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
uint8_t dev_addr;
|
||||
|
||||
if ((req->wIndex == 0) && (req->wLength == 0))
|
||||
{
|
||||
dev_addr = (uint8_t)(req->wValue) & 0x7F;
|
||||
|
||||
if (pdev->dev.device_status == USB_OTG_CONFIGURED)
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
}
|
||||
else
|
||||
{
|
||||
pdev->dev.device_address = dev_addr;
|
||||
DCD_EP_SetAddress(pdev, dev_addr);
|
||||
USBD_CtlSendStatus(pdev);
|
||||
|
||||
if (dev_addr != 0)
|
||||
{
|
||||
pdev->dev.device_status = USB_OTG_ADDRESSED;
|
||||
}
|
||||
else
|
||||
{
|
||||
pdev->dev.device_status = USB_OTG_DEFAULT;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_SetConfig
|
||||
* Handle Set device configuration request
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
|
||||
static uint8_t cfgidx;
|
||||
|
||||
cfgidx = (uint8_t)(req->wValue);
|
||||
|
||||
if (cfgidx > USBD_CFG_MAX_NUM )
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (pdev->dev.device_status)
|
||||
{
|
||||
case USB_OTG_ADDRESSED:
|
||||
if (cfgidx)
|
||||
{
|
||||
pdev->dev.device_config = cfgidx;
|
||||
pdev->dev.device_status = USB_OTG_CONFIGURED;
|
||||
USBD_SetCfg(pdev , cfgidx);
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
break;
|
||||
|
||||
case USB_OTG_CONFIGURED:
|
||||
if (cfgidx == 0)
|
||||
{
|
||||
pdev->dev.device_status = USB_OTG_ADDRESSED;
|
||||
pdev->dev.device_config = cfgidx;
|
||||
USBD_ClrCfg(pdev , cfgidx);
|
||||
USBD_CtlSendStatus(pdev);
|
||||
|
||||
}
|
||||
else if (cfgidx != pdev->dev.device_config)
|
||||
{
|
||||
/* Clear old configuration */
|
||||
USBD_ClrCfg(pdev , pdev->dev.device_config);
|
||||
|
||||
/* set new configuration */
|
||||
pdev->dev.device_config = cfgidx;
|
||||
USBD_SetCfg(pdev , cfgidx);
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
else
|
||||
{
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_GetConfig
|
||||
* Handle Get device configuration request
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
|
||||
if (req->wLength != 1)
|
||||
{
|
||||
USBD_CtlError(pdev , req);
|
||||
}
|
||||
else
|
||||
{
|
||||
switch (pdev->dev.device_status )
|
||||
{
|
||||
case USB_OTG_ADDRESSED:
|
||||
|
||||
USBD_CtlSendData (pdev,
|
||||
(uint8_t *)&USBD_default_cfg,
|
||||
1);
|
||||
break;
|
||||
|
||||
case USB_OTG_CONFIGURED:
|
||||
|
||||
USBD_CtlSendData (pdev,
|
||||
&pdev->dev.device_config,
|
||||
1);
|
||||
break;
|
||||
|
||||
default:
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_GetStatus
|
||||
* Handle Get Status request
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
|
||||
|
||||
switch (pdev->dev.device_status)
|
||||
{
|
||||
case USB_OTG_ADDRESSED:
|
||||
case USB_OTG_CONFIGURED:
|
||||
|
||||
#ifdef USBD_SELF_POWERED
|
||||
USBD_cfg_status = USB_CONFIG_SELF_POWERED;
|
||||
#else
|
||||
USBD_cfg_status = 0x00;
|
||||
#endif
|
||||
|
||||
if (pdev->dev.DevRemoteWakeup)
|
||||
{
|
||||
USBD_cfg_status |= USB_CONFIG_REMOTE_WAKEUP;
|
||||
}
|
||||
|
||||
USBD_CtlSendData (pdev,
|
||||
(uint8_t *)&USBD_cfg_status,
|
||||
2);
|
||||
break;
|
||||
|
||||
default :
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_SetFeature
|
||||
* Handle Set device feature request
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
|
||||
USB_OTG_DCTL_TypeDef dctl;
|
||||
uint8_t test_mode = 0;
|
||||
|
||||
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
||||
{
|
||||
pdev->dev.DevRemoteWakeup = 1;
|
||||
pdev->dev.class_cb->Setup (pdev, req);
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
|
||||
else if ((req->wValue == USB_FEATURE_TEST_MODE) &&
|
||||
((req->wIndex & 0xFF) == 0))
|
||||
{
|
||||
dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL);
|
||||
|
||||
test_mode = req->wIndex >> 8;
|
||||
switch (test_mode)
|
||||
{
|
||||
case 1: // TEST_J
|
||||
dctl.b.tstctl = 1;
|
||||
break;
|
||||
|
||||
case 2: // TEST_K
|
||||
dctl.b.tstctl = 2;
|
||||
break;
|
||||
|
||||
case 3: // TEST_SE0_NAK
|
||||
dctl.b.tstctl = 3;
|
||||
break;
|
||||
|
||||
case 4: // TEST_PACKET
|
||||
dctl.b.tstctl = 4;
|
||||
break;
|
||||
|
||||
case 5: // TEST_FORCE_ENABLE
|
||||
dctl.b.tstctl = 5;
|
||||
break;
|
||||
}
|
||||
SET_TEST_MODE = dctl;
|
||||
pdev->dev.test_mode = 1;
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_ClrFeature
|
||||
* Handle clear device feature request
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval status
|
||||
*/
|
||||
static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
switch (pdev->dev.device_status)
|
||||
{
|
||||
case USB_OTG_ADDRESSED:
|
||||
case USB_OTG_CONFIGURED:
|
||||
if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
|
||||
{
|
||||
pdev->dev.DevRemoteWakeup = 0;
|
||||
pdev->dev.class_cb->Setup (pdev, req);
|
||||
USBD_CtlSendStatus(pdev);
|
||||
}
|
||||
break;
|
||||
|
||||
default :
|
||||
USBD_CtlError(pdev , req);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_ParseSetupRequest
|
||||
* Copy buffer into setup structure
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet);
|
||||
req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1);
|
||||
req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2);
|
||||
req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4);
|
||||
req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6);
|
||||
|
||||
pdev->dev.in_ep[0].ctl_data_len = req->wLength ;
|
||||
pdev->dev.device_state = USB_OTG_EP0_SETUP;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_CtlError
|
||||
* Handle USB low level Error
|
||||
* @param pdev: device instance
|
||||
* @param req: usb request
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req)
|
||||
{
|
||||
|
||||
DCD_EP_Stall(pdev , 0x80);
|
||||
DCD_EP_Stall(pdev , 0);
|
||||
USB_OTG_EP0_OutStart(pdev);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_GetString
|
||||
* Convert Ascii string into unicode one
|
||||
* @param desc : descriptor buffer
|
||||
* @param unicode : Formatted string buffer (unicode)
|
||||
* @param len : descriptor length
|
||||
* @retval None
|
||||
*/
|
||||
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
|
||||
{
|
||||
uint8_t idx = 0;
|
||||
|
||||
if (desc != NULL)
|
||||
{
|
||||
*len = USBD_GetLen(desc) * 2 + 2;
|
||||
unicode[idx++] = *len;
|
||||
unicode[idx++] = USB_DESC_TYPE_STRING;
|
||||
|
||||
while (*desc != NULL)
|
||||
{
|
||||
unicode[idx++] = *desc++;
|
||||
unicode[idx++] = 0x00;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_GetLen
|
||||
* return the string length
|
||||
* @param buf : pointer to the ascii string buffer
|
||||
* @retval string length
|
||||
*/
|
||||
static uint8_t USBD_GetLen(uint8_t *buf)
|
||||
{
|
||||
uint8_t len = 0;
|
||||
|
||||
while (*buf != NULL)
|
||||
{
|
||||
len++;
|
||||
buf++;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_req.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief header file for the usbd_req.c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
|
||||
#ifndef __USB_REQUEST_H_
|
||||
#define __USB_REQUEST_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_def.h"
|
||||
#include "usbd_core.h"
|
||||
#include "usbd_conf.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_REQ
|
||||
* @brief header file for the usbd_ioreq.c file
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_REQ_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_REQ_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_REQ_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_REQ_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_REQ_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
|
||||
USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
|
||||
USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
|
||||
USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
|
||||
void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev,
|
||||
USB_SETUP_REQ *req);
|
||||
|
||||
void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* __USB_REQUEST_H_ */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,350 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_storage_msd.c
|
||||
* @author MCD application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file provides the disk operations functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_msc_mem.h"
|
||||
#include "usb_conf.h"
|
||||
|
||||
/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STORAGE
|
||||
* @brief media storage application module
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup STORAGE_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STORAGE_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define STORAGE_LUN_NBR 1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STORAGE_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STORAGE_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
/* USB Mass storage Standard Inquiry Data */
|
||||
const int8_t STORAGE_Inquirydata[] = {//36
|
||||
|
||||
/* LUN 0 */
|
||||
0x00,
|
||||
0x00, // make it 0x80 for a removable drive
|
||||
0x02,
|
||||
0x02,
|
||||
(USBD_STD_INQUIRY_LENGTH - 5),
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */
|
||||
'm', 'i', 'c', 'r', 'o', 'S', 'D', ' ', /* Product : 16 Bytes */
|
||||
'F', 'l', 'a', 's', 'h', ' ', ' ', ' ',
|
||||
'1', '.', '0' ,'0', /* Version : 4 Bytes */
|
||||
};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STORAGE_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
int8_t STORAGE_Init (uint8_t lun);
|
||||
|
||||
int8_t STORAGE_GetCapacity (uint8_t lun,
|
||||
uint32_t *block_num,
|
||||
uint32_t *block_size);
|
||||
|
||||
int8_t STORAGE_IsReady (uint8_t lun);
|
||||
|
||||
int8_t STORAGE_IsWriteProtected (uint8_t lun);
|
||||
|
||||
int8_t STORAGE_Read (uint8_t lun,
|
||||
uint8_t *buf,
|
||||
uint32_t blk_addr,
|
||||
uint16_t blk_len);
|
||||
|
||||
int8_t STORAGE_Write (uint8_t lun,
|
||||
uint8_t *buf,
|
||||
uint32_t blk_addr,
|
||||
uint16_t blk_len);
|
||||
|
||||
int8_t STORAGE_GetMaxLun (void);
|
||||
|
||||
|
||||
USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops =
|
||||
{
|
||||
STORAGE_Init,
|
||||
STORAGE_GetCapacity,
|
||||
STORAGE_IsReady,
|
||||
STORAGE_IsWriteProtected,
|
||||
STORAGE_Read,
|
||||
STORAGE_Write,
|
||||
STORAGE_GetMaxLun,
|
||||
(int8_t *)STORAGE_Inquirydata,
|
||||
};
|
||||
|
||||
USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops;
|
||||
/*
|
||||
#ifndef USE_STM3210C_EVAL
|
||||
extern SD_CardInfo SDCardInfo;
|
||||
#endif
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup STORAGE_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialize the storage medium
|
||||
* @param lun : logical unit number
|
||||
* @retval Status
|
||||
*/
|
||||
|
||||
int8_t STORAGE_Init (uint8_t lun)
|
||||
{
|
||||
/*
|
||||
#ifndef USE_STM3210C_EVAL
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
NVIC_InitStructure.NVIC_IRQChannel = SDIO_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority =0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
#endif
|
||||
if( SD_Init() != 0)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
*/
|
||||
|
||||
return (0);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return medium capacity and block size
|
||||
* @param lun : logical unit number
|
||||
* @param block_num : number of physical block
|
||||
* @param block_size : size of a physical block
|
||||
* @retval Status
|
||||
*/
|
||||
int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint32_t *block_size)
|
||||
{
|
||||
/*
|
||||
#ifdef USE_STM3210C_EVAL
|
||||
SD_CardInfo SDCardInfo;
|
||||
|
||||
SD_GetCardInfo(&SDCardInfo);
|
||||
|
||||
#else
|
||||
if(SD_GetStatus() != 0 )
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
#endif
|
||||
*/
|
||||
|
||||
|
||||
*block_size = 512;
|
||||
//*block_num = SDCardInfo.CardCapacity / 512;
|
||||
*block_num = 256 + 128;
|
||||
|
||||
return (0);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the medium is ready
|
||||
* @param lun : logical unit number
|
||||
* @retval Status
|
||||
*/
|
||||
int8_t STORAGE_IsReady (uint8_t lun)
|
||||
{
|
||||
|
||||
/*
|
||||
#ifndef USE_STM3210C_EVAL
|
||||
|
||||
static int8_t last_status = 0;
|
||||
|
||||
if(last_status < 0)
|
||||
{
|
||||
SD_Init();
|
||||
last_status = 0;
|
||||
}
|
||||
|
||||
if(SD_GetStatus() != 0)
|
||||
{
|
||||
last_status = -1;
|
||||
return (-1);
|
||||
}
|
||||
#else
|
||||
if( SD_Init() != 0)
|
||||
{
|
||||
return (-1);
|
||||
}
|
||||
#endif
|
||||
*/
|
||||
return (0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the medium is write-protected
|
||||
* @param lun : logical unit number
|
||||
* @retval Status
|
||||
*/
|
||||
int8_t STORAGE_IsWriteProtected (uint8_t lun)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read data from the medium
|
||||
* @param lun : logical unit number
|
||||
* @param buf : Pointer to the buffer to save data
|
||||
* @param blk_addr : address of 1st block to be read
|
||||
* @param blk_len : nmber of blocks to be read
|
||||
* @retval Status
|
||||
*/
|
||||
int disk_read (
|
||||
uint8_t pdrv, /* Physical drive nmuber (0..) */
|
||||
uint8_t *buff, /* Data buffer to store read data */
|
||||
uint32_t sector, /* Sector address (LBA) */
|
||||
uint32_t count /* Number of sectors to read (1..128) */
|
||||
);
|
||||
int8_t STORAGE_Read (uint8_t lun,
|
||||
uint8_t *buf,
|
||||
uint32_t blk_addr,
|
||||
uint16_t blk_len)
|
||||
{
|
||||
|
||||
/*
|
||||
if( SD_ReadMultiBlocks (buf,
|
||||
blk_addr * 512,
|
||||
512,
|
||||
blk_len) != 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
#ifndef USE_STM3210C_EVAL
|
||||
SD_WaitReadOperation();
|
||||
while (SD_GetStatus() != SD_TRANSFER_OK);
|
||||
#endif
|
||||
*/
|
||||
disk_read(0, buf, blk_addr, blk_len);
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief Write data to the medium
|
||||
* @param lun : logical unit number
|
||||
* @param buf : Pointer to the buffer to write from
|
||||
* @param blk_addr : address of 1st block to be written
|
||||
* @param blk_len : nmber of blocks to be read
|
||||
* @retval Status
|
||||
*/
|
||||
int disk_write (
|
||||
uint8_t pdrv, /* Physical drive nmuber (0..) */
|
||||
const uint8_t *buff, /* Data to be written */
|
||||
uint32_t sector, /* Sector address (LBA) */
|
||||
uint32_t count /* Number of sectors to write (1..128) */
|
||||
);
|
||||
int8_t STORAGE_Write (uint8_t lun,
|
||||
uint8_t *buf,
|
||||
uint32_t blk_addr,
|
||||
uint16_t blk_len)
|
||||
{
|
||||
|
||||
/*
|
||||
if( SD_WriteMultiBlocks (buf,
|
||||
blk_addr * 512,
|
||||
512,
|
||||
blk_len) != 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
#ifndef USE_STM3210C_EVAL
|
||||
SD_WaitWriteOperation();
|
||||
while (SD_GetStatus() != SD_TRANSFER_OK);
|
||||
#endif
|
||||
*/
|
||||
disk_write(0, buf, blk_addr, blk_len);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return number of supported logical unit
|
||||
* @param None
|
||||
* @retval number of logical unit
|
||||
*/
|
||||
|
||||
int8_t STORAGE_GetMaxLun (void)
|
||||
{
|
||||
return (STORAGE_LUN_NBR - 1);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_usr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file includes the user application layer
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "usbd_usr.h"
|
||||
#include "usbd_ioreq.h"
|
||||
#include "std.h"
|
||||
|
||||
USBD_Usr_cb_TypeDef USR_cb = {
|
||||
USBD_USR_Init,
|
||||
USBD_USR_DeviceReset,
|
||||
USBD_USR_DeviceConfigured,
|
||||
USBD_USR_DeviceSuspended,
|
||||
USBD_USR_DeviceResumed,
|
||||
USBD_USR_DeviceConnected,
|
||||
USBD_USR_DeviceDisconnected,
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_Init
|
||||
* Displays the message on LCD for host lib initialization
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void USBD_USR_Init() {
|
||||
printf("USB OTG FS\n");
|
||||
printf("USB device start\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_DeviceReset
|
||||
* Displays the message on LCD on device Reset Event
|
||||
* @param speed : device speed
|
||||
* @retval None
|
||||
*/
|
||||
void USBD_USR_DeviceReset(uint8_t speed) {
|
||||
printf("USB reset %d\n", speed);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_DeviceConfigured
|
||||
* Displays the message on LCD on device configuration Event
|
||||
* @param None
|
||||
* @retval Staus
|
||||
*/
|
||||
void USBD_USR_DeviceConfigured() {
|
||||
printf("USB dev config\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_DeviceSuspended
|
||||
* Displays the message on LCD on device suspend Event
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void USBD_USR_DeviceSuspended() {
|
||||
printf("USB dev suspend\n");
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_DeviceResumed
|
||||
* Displays the message on LCD on device resume Event
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void USBD_USR_DeviceResumed() {
|
||||
printf("USB dev resume\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_DeviceConnected
|
||||
* Displays the message on LCD on device connection Event
|
||||
* @param None
|
||||
* @retval Staus
|
||||
*/
|
||||
void USBD_USR_DeviceConnected() {
|
||||
printf("USB dev connect\n");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief USBD_USR_DeviceDisonnected
|
||||
* Displays the message on LCD on device disconnection Event
|
||||
* @param None
|
||||
* @retval Staus
|
||||
*/
|
||||
void USBD_USR_DeviceDisconnected() {
|
||||
printf("USB dev disconn\n");
|
||||
}
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,141 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file usbd_usr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Header file for usbd_usr.c
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __USBD_USR_H__
|
||||
#define __USBD_USR_H__
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usbd_core.h"
|
||||
|
||||
|
||||
/** @addtogroup USBD_USER
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USBD_MSC_DEMO_USER_CALLBACKS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_USR
|
||||
* @brief This file is the Header file for usbd_usr.c
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup USBD_USR_Exported_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern USBD_Usr_cb_TypeDef USR_cb;
|
||||
extern USBD_Usr_cb_TypeDef USR_FS_cb;
|
||||
extern USBD_Usr_cb_TypeDef USR_HS_cb;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup USBD_USR_Exported_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_USR_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_USR_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
void USBD_USR_Init(void);
|
||||
void USBD_USR_DeviceReset (uint8_t speed);
|
||||
void USBD_USR_DeviceConfigured (void);
|
||||
void USBD_USR_DeviceSuspended(void);
|
||||
void USBD_USR_DeviceResumed(void);
|
||||
|
||||
void USBD_USR_DeviceConnected(void);
|
||||
void USBD_USR_DeviceDisconnected(void);
|
||||
|
||||
void USBD_USR_FS_Init(void);
|
||||
void USBD_USR_FS_DeviceReset (uint8_t speed);
|
||||
void USBD_USR_FS_DeviceConfigured (void);
|
||||
void USBD_USR_FS_DeviceSuspended(void);
|
||||
void USBD_USR_FS_DeviceResumed(void);
|
||||
|
||||
void USBD_USR_FS_DeviceConnected(void);
|
||||
void USBD_USR_FS_DeviceDisconnected(void);
|
||||
|
||||
void USBD_USR_HS_Init(void);
|
||||
void USBD_USR_HS_DeviceReset (uint8_t speed);
|
||||
void USBD_USR_HS_DeviceConfigured (void);
|
||||
void USBD_USR_HS_DeviceSuspended(void);
|
||||
void USBD_USR_HS_DeviceResumed(void);
|
||||
|
||||
void USBD_USR_HS_DeviceConnected(void);
|
||||
void USBD_USR_HS_DeviceDisconnected(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USBD_USR_Exported_FunctionsPrototype
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /*__USBD_USR_H__*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,829 @@
|
|||
#include <stm32f4xx.h>
|
||||
#include <stm32f4xx_rcc.h>
|
||||
#include "std.h"
|
||||
|
||||
#include "font_petme128_8x8.h"
|
||||
|
||||
void delay_ms(int ms);
|
||||
|
||||
void impl02_c_version() {
|
||||
int x = 0;
|
||||
while (x < 400) {
|
||||
int y = 0;
|
||||
while (y < 400) {
|
||||
volatile int z = 0;
|
||||
while (z < 400) {
|
||||
z = z + 1;
|
||||
}
|
||||
y = y + 1;
|
||||
}
|
||||
x = x + 1;
|
||||
}
|
||||
}
|
||||
|
||||
void set_bits(__IO uint32_t *addr, uint32_t shift, uint32_t mask, uint32_t value) {
|
||||
uint32_t x = *addr;
|
||||
x &= ~(mask << shift);
|
||||
x |= (value << shift);
|
||||
*addr = x;
|
||||
}
|
||||
|
||||
void gpio_init() {
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN | RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOAEN;
|
||||
}
|
||||
|
||||
#define PYB_LEDR_PORT (GPIOA)
|
||||
#define PYB_LEDR1_PORT_NUM (8)
|
||||
#define PYB_LEDR2_PORT_NUM (10)
|
||||
#define PYB_LEDG_PORT (GPIOC)
|
||||
#define PYB_LEDG1_PORT_NUM (4)
|
||||
#define PYB_LEDG2_PORT_NUM (5)
|
||||
|
||||
void gpio_pin_init(GPIO_TypeDef *gpio, uint32_t pin, uint32_t moder, uint32_t otyper, uint32_t ospeedr, uint32_t pupdr) {
|
||||
set_bits(&gpio->MODER, 2 * pin, 3, moder);
|
||||
set_bits(&gpio->OTYPER, pin, 1, otyper);
|
||||
set_bits(&gpio->OSPEEDR, 2 * pin, 3, ospeedr);
|
||||
set_bits(&gpio->PUPDR, 2 * pin, 3, pupdr);
|
||||
}
|
||||
|
||||
void gpio_pin_af(GPIO_TypeDef *gpio, uint32_t pin, uint32_t af) {
|
||||
// set the AF bits for the given pin
|
||||
// pins 0-7 use low word of AFR, pins 8-15 use high word
|
||||
set_bits(&gpio->AFR[pin >> 3], 4 * (pin & 0x07), 0xf, af);
|
||||
}
|
||||
|
||||
void mma_init() {
|
||||
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // enable I2C1
|
||||
gpio_pin_init(GPIOB, 6 /* B6 is SCL */, 2 /* AF mode */, 1 /* open drain output */, 1 /* 25 MHz */, 0 /* no pull up or pull down */);
|
||||
gpio_pin_init(GPIOB, 7 /* B7 is SDA */, 2 /* AF mode */, 1 /* open drain output */, 1 /* 25 MHz */, 0 /* no pull up or pull down */);
|
||||
gpio_pin_af(GPIOB, 6, 4 /* AF 4 for I2C1 */);
|
||||
gpio_pin_af(GPIOB, 7, 4 /* AF 4 for I2C1 */);
|
||||
|
||||
// get clock speeds
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
|
||||
// disable the I2C peripheral before we configure it
|
||||
I2C1->CR1 &= ~I2C_CR1_PE;
|
||||
|
||||
// program peripheral input clock
|
||||
I2C1->CR2 = 4; // no interrupts; 4 MHz (hopefully!) (could go up to 42MHz)
|
||||
|
||||
// configure clock control reg
|
||||
uint32_t freq = rcc_clocks.PCLK1_Frequency / (100000 << 1); // want 100kHz, this is the formula for freq
|
||||
I2C1->CCR = freq; // standard mode (speed), freq calculated as above
|
||||
|
||||
// configure rise time reg
|
||||
I2C1->TRISE = (rcc_clocks.PCLK1_Frequency / 1000000) + 1; // formula for trise, gives maximum rise time
|
||||
|
||||
// enable the I2C peripheral
|
||||
I2C1->CR1 |= I2C_CR1_PE;
|
||||
|
||||
// set START bit in CR1 to generate a start cond!
|
||||
}
|
||||
|
||||
uint32_t i2c_get_sr() {
|
||||
// must read SR1 first, then SR2, as the read can clear some flags
|
||||
uint32_t sr1 = I2C1->SR1;
|
||||
uint32_t sr2 = I2C1->SR2;
|
||||
return (sr2 << 16) | sr1;
|
||||
}
|
||||
|
||||
void mma_restart(uint8_t addr, int write) {
|
||||
// send start condition
|
||||
I2C1->CR1 |= I2C_CR1_START;
|
||||
|
||||
// wait for BUSY, MSL and SB --> Slave has acknowledged start condition
|
||||
while ((i2c_get_sr() & 0x00030001) != 0x00030001) {
|
||||
}
|
||||
|
||||
if (write) {
|
||||
// send address and write bit
|
||||
I2C1->DR = (addr << 1) | 0;
|
||||
// wait for BUSY, MSL, ADDR, TXE and TRA
|
||||
while ((i2c_get_sr() & 0x00070082) != 0x00070082) {
|
||||
}
|
||||
} else {
|
||||
// send address and read bit
|
||||
I2C1->DR = (addr << 1) | 1;
|
||||
// wait for BUSY, MSL and ADDR flags
|
||||
while ((i2c_get_sr() & 0x00030002) != 0x00030002) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void mma_start(uint8_t addr, int write) {
|
||||
// wait until I2C is not busy
|
||||
while (I2C1->SR2 & I2C_SR2_BUSY) {
|
||||
}
|
||||
|
||||
// do rest of start
|
||||
mma_restart(addr, write);
|
||||
}
|
||||
|
||||
void mma_send_byte(uint8_t data) {
|
||||
// send byte
|
||||
I2C1->DR = data;
|
||||
// wait for TRA, BUSY, MSL, TXE and BTF (byte transmitted)
|
||||
int timeout = 1000000;
|
||||
while ((i2c_get_sr() & 0x00070084) != 0x00070084) {
|
||||
if (timeout-- <= 0) {
|
||||
printf("mma_send_byte timed out!\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t mma_read_ack() {
|
||||
// enable ACK of received byte
|
||||
I2C1->CR1 |= I2C_CR1_ACK;
|
||||
// wait for BUSY, MSL and RXNE (byte received)
|
||||
while ((i2c_get_sr() & 0x00030040) != 0x00030040) {
|
||||
}
|
||||
// read and return data
|
||||
uint8_t data = I2C1->DR;
|
||||
return data;
|
||||
}
|
||||
|
||||
uint8_t mma_read_nack() {
|
||||
// disable ACK of received byte (to indicate end of receiving)
|
||||
I2C1->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
|
||||
// last byte should apparently also generate a stop condition
|
||||
I2C1->CR1 |= I2C_CR1_STOP;
|
||||
// wait for BUSY, MSL and RXNE (byte received)
|
||||
while ((i2c_get_sr() & 0x00030040) != 0x00030040) {
|
||||
}
|
||||
// read and return data
|
||||
uint8_t data = I2C1->DR;
|
||||
return data;
|
||||
}
|
||||
|
||||
void mma_stop() {
|
||||
// send stop condition
|
||||
I2C1->CR1 |= I2C_CR1_STOP;
|
||||
}
|
||||
|
||||
void led_init() {
|
||||
// set the output high (so LED is off)
|
||||
PYB_LEDR_PORT->BSRRL = 1 << PYB_LEDR1_PORT_NUM;
|
||||
PYB_LEDR_PORT->BSRRL = 1 << PYB_LEDR2_PORT_NUM;
|
||||
PYB_LEDG_PORT->BSRRL = 1 << PYB_LEDG1_PORT_NUM;
|
||||
PYB_LEDG_PORT->BSRRL = 1 << PYB_LEDG2_PORT_NUM;
|
||||
// make it an open drain output
|
||||
gpio_pin_init(PYB_LEDR_PORT, PYB_LEDR1_PORT_NUM, 1, 1, 0, 0);
|
||||
gpio_pin_init(PYB_LEDR_PORT, PYB_LEDR2_PORT_NUM, 1, 1, 0, 0);
|
||||
gpio_pin_init(PYB_LEDG_PORT, PYB_LEDG1_PORT_NUM, 1, 1, 0, 0);
|
||||
gpio_pin_init(PYB_LEDG_PORT, PYB_LEDG2_PORT_NUM, 1, 1, 0, 0);
|
||||
}
|
||||
|
||||
static void led_state(uint32_t led_port, int s) {
|
||||
if (s == 0) {
|
||||
// LED off, output is high
|
||||
if (led_port == PYB_LEDR1_PORT_NUM || led_port == PYB_LEDR2_PORT_NUM) {
|
||||
PYB_LEDR_PORT->BSRRL = 1 << led_port;
|
||||
} else {
|
||||
PYB_LEDG_PORT->BSRRL = 1 << led_port;
|
||||
}
|
||||
} else {
|
||||
// LED on, output is low
|
||||
if (led_port == PYB_LEDR1_PORT_NUM || led_port == PYB_LEDR2_PORT_NUM) {
|
||||
PYB_LEDR_PORT->BSRRH = 1 << led_port;
|
||||
} else {
|
||||
PYB_LEDG_PORT->BSRRH = 1 << led_port;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define PYB_USRSW_PORT (GPIOA)
|
||||
#define PYB_USRSW_PORT_NUM (13)
|
||||
|
||||
void sw_init() {
|
||||
// make it an input with pull-up
|
||||
gpio_pin_init(PYB_USRSW_PORT, PYB_USRSW_PORT_NUM, 0, 0, 0, 1);
|
||||
}
|
||||
|
||||
int sw_get() {
|
||||
if (PYB_USRSW_PORT->IDR & (1 << PYB_USRSW_PORT_NUM)) {
|
||||
// pulled high, so switch is not pressed
|
||||
return 0;
|
||||
} else {
|
||||
// pulled low, so switch is pressed
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
#define PYB_LCD_PORT (GPIOA)
|
||||
#define PYB_LCD_CS1_PIN (0)
|
||||
#define PYB_LCD_RST_PIN (1)
|
||||
#define PYB_LCD_A0_PIN (2)
|
||||
#define PYB_LCD_SCL_PIN (3)
|
||||
#define PYB_LCD_SI_PIN (4)
|
||||
|
||||
static void lcd_comm_out(uint8_t i) {
|
||||
delay_ms(0);
|
||||
PYB_LCD_PORT->BSRRH = 1 << PYB_LCD_CS1_PIN; // CS=0; enable
|
||||
PYB_LCD_PORT->BSRRH = 1 << PYB_LCD_A0_PIN; // A0=0; select instr reg
|
||||
// send byte bigendian, latches on rising clock
|
||||
for (uint32_t n = 0; n < 8; n++) {
|
||||
delay_ms(0);
|
||||
PYB_LCD_PORT->BSRRH = 1 << PYB_LCD_SCL_PIN; // SCL=0
|
||||
if ((i & 0x80) == 0) {
|
||||
PYB_LCD_PORT->BSRRH = 1 << PYB_LCD_SI_PIN; // SI=0
|
||||
} else {
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_SI_PIN; // SI=1
|
||||
}
|
||||
i <<= 1;
|
||||
delay_ms(0);
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_SCL_PIN; // SCL=1
|
||||
}
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_CS1_PIN; // CS=1; disable
|
||||
|
||||
/*
|
||||
in Python, native types:
|
||||
CS1_PIN(const) = 0
|
||||
n = int(0)
|
||||
delay_ms(0)
|
||||
PORT[word:BSRRH] = 1 << CS1_PIN
|
||||
for n in range(0, 8):
|
||||
delay_ms(0)
|
||||
PORT[word:BSRRH] = 1 << SCL_PIN
|
||||
if i & 0x80 == 0:
|
||||
PORT[word:BSRRH] = 1 << SI_PIN
|
||||
else:
|
||||
PORT[word:BSRRL] = 1 << SI_PIN
|
||||
i <<= 1
|
||||
delay_ms(0)
|
||||
PORT[word:BSRRL] = 1 << SCL_PIN
|
||||
*/
|
||||
}
|
||||
|
||||
static void lcd_data_out(uint8_t i) {
|
||||
delay_ms(0);
|
||||
PYB_LCD_PORT->BSRRH = 1 << PYB_LCD_CS1_PIN; // CS=0; enable
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_A0_PIN; // A0=1; select data reg
|
||||
// send byte bigendian, latches on rising clock
|
||||
for (uint32_t n = 0; n < 8; n++) {
|
||||
delay_ms(0);
|
||||
PYB_LCD_PORT->BSRRH = 1 << PYB_LCD_SCL_PIN; // SCL=0
|
||||
if ((i & 0x80) == 0) {
|
||||
PYB_LCD_PORT->BSRRH = 1 << PYB_LCD_SI_PIN; // SI=0
|
||||
} else {
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_SI_PIN; // SI=1
|
||||
}
|
||||
i <<= 1;
|
||||
delay_ms(0);
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_SCL_PIN; // SCL=1
|
||||
}
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_CS1_PIN; // CS=1; disable
|
||||
}
|
||||
|
||||
#define LCD_BUF_W (16)
|
||||
#define LCD_BUF_H (4)
|
||||
char lcd_buffer[LCD_BUF_W * LCD_BUF_H];
|
||||
int lcd_line;
|
||||
int lcd_column;
|
||||
int lcd_next_line;
|
||||
|
||||
void lcd_print_strn(const char *str, unsigned int len) {
|
||||
int redraw_min = lcd_line * LCD_BUF_W + lcd_column;
|
||||
int redraw_max = redraw_min;
|
||||
int did_new_line = 0;
|
||||
for (; len > 0; len--, str++) {
|
||||
// move to next line if needed
|
||||
if (lcd_next_line) {
|
||||
if (lcd_line + 1 < LCD_BUF_H) {
|
||||
lcd_line += 1;
|
||||
} else {
|
||||
lcd_line = LCD_BUF_H - 1;
|
||||
for (int i = 0; i < LCD_BUF_W * (LCD_BUF_H - 1); i++) {
|
||||
lcd_buffer[i] = lcd_buffer[i + LCD_BUF_W];
|
||||
}
|
||||
for (int i = 0; i < LCD_BUF_W; i++) {
|
||||
lcd_buffer[LCD_BUF_W * (LCD_BUF_H - 1) + i] = ' ';
|
||||
}
|
||||
redraw_min = 0;
|
||||
redraw_max = LCD_BUF_W * LCD_BUF_H;
|
||||
}
|
||||
lcd_next_line = 0;
|
||||
lcd_column = 0;
|
||||
did_new_line = 1;
|
||||
}
|
||||
if (*str == '\n') {
|
||||
lcd_next_line = 1;
|
||||
} else if (lcd_column >= LCD_BUF_W) {
|
||||
lcd_next_line = 1;
|
||||
str -= 1;
|
||||
len += 1;
|
||||
} else {
|
||||
lcd_buffer[lcd_line * LCD_BUF_W + lcd_column] = *str;
|
||||
lcd_column += 1;
|
||||
int max = lcd_line * LCD_BUF_W + lcd_column;
|
||||
if (max > redraw_max) {
|
||||
redraw_max = max;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int last_page = -1;
|
||||
for (int i = redraw_min; i < redraw_max; i++) {
|
||||
int page = i / LCD_BUF_W;
|
||||
if (page != last_page) {
|
||||
int offset = 8 * (i - (page * LCD_BUF_W));
|
||||
lcd_comm_out(0xb0 | page); // page address set
|
||||
lcd_comm_out(0x10 | ((offset >> 4) & 0x0f)); // column address set upper
|
||||
lcd_comm_out(0x00 | (offset & 0x0f)); // column address set lower
|
||||
last_page = page;
|
||||
}
|
||||
int chr = lcd_buffer[i];
|
||||
if (chr < 32 || chr > 126) {
|
||||
chr = 127;
|
||||
}
|
||||
const uint8_t *chr_data = &font_petme128_8x8[(chr - 32) * 8];
|
||||
for (int i = 0; i < 8; i++) {
|
||||
lcd_data_out(chr_data[i]);
|
||||
}
|
||||
}
|
||||
|
||||
if (did_new_line) {
|
||||
delay_ms(200);
|
||||
}
|
||||
}
|
||||
|
||||
static void lcd_init() {
|
||||
// set the outputs high
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_CS1_PIN;
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_RST_PIN;
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_A0_PIN;
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_SCL_PIN;
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_SI_PIN;
|
||||
// make them push/pull outputs
|
||||
gpio_pin_init(PYB_LCD_PORT, PYB_LCD_CS1_PIN, 1, 0, 0, 0);
|
||||
gpio_pin_init(PYB_LCD_PORT, PYB_LCD_RST_PIN, 1, 0, 0, 0);
|
||||
gpio_pin_init(PYB_LCD_PORT, PYB_LCD_A0_PIN, 1, 0, 0, 0);
|
||||
gpio_pin_init(PYB_LCD_PORT, PYB_LCD_SCL_PIN, 1, 0, 0, 0);
|
||||
gpio_pin_init(PYB_LCD_PORT, PYB_LCD_SI_PIN, 1, 0, 0, 0);
|
||||
|
||||
// init the LCD
|
||||
delay_ms(1); // wait a bit
|
||||
PYB_LCD_PORT->BSRRH = 1 << PYB_LCD_RST_PIN; // RST=0; reset
|
||||
delay_ms(1); // wait for reset; 2us min
|
||||
PYB_LCD_PORT->BSRRL = 1 << PYB_LCD_RST_PIN; // RST=1; enable
|
||||
delay_ms(1); // wait for reset; 2us min
|
||||
lcd_comm_out(0xa0); // ADC select, normal
|
||||
lcd_comm_out(0xc8); // common output mode select, reverse
|
||||
lcd_comm_out(0xa2); // LCD bias set, 1/9 bias
|
||||
lcd_comm_out(0x2f); // power control set, 0b111=(booster on, vreg on, vfollow on)
|
||||
lcd_comm_out(0x21); // v0 voltage regulator internal resistor ratio set, 0b001=small
|
||||
lcd_comm_out(0x81); // electronic volume mode set
|
||||
lcd_comm_out(0x34); // electronic volume register set, 0b110100
|
||||
lcd_comm_out(0x40); // display start line set, 0
|
||||
lcd_comm_out(0xaf); // LCD display, on
|
||||
|
||||
// clear display
|
||||
for (int page = 0; page < 4; page++) {
|
||||
lcd_comm_out(0xb0 | page); // page address set
|
||||
lcd_comm_out(0x10); // column address set upper
|
||||
lcd_comm_out(0x00); // column address set lower
|
||||
for (int i = 0; i < 128; i++) {
|
||||
lcd_data_out(0x00);
|
||||
}
|
||||
}
|
||||
|
||||
for (int i = 0; i < LCD_BUF_H * LCD_BUF_W; i++) {
|
||||
lcd_buffer[i] = ' ';
|
||||
}
|
||||
lcd_line = 0;
|
||||
lcd_column = 0;
|
||||
lcd_next_line = 0;
|
||||
}
|
||||
|
||||
void __fatal_error(const char *msg) {
|
||||
lcd_print_strn("\nFATAL ERROR:\n", 14);
|
||||
lcd_print_strn(msg, strlen(msg));
|
||||
|
||||
for (;;) {
|
||||
led_state(PYB_LEDR1_PORT_NUM, 1);
|
||||
led_state(PYB_LEDR2_PORT_NUM, 0);
|
||||
delay_ms(150);
|
||||
led_state(PYB_LEDR1_PORT_NUM, 0);
|
||||
led_state(PYB_LEDR2_PORT_NUM, 1);
|
||||
delay_ms(150);
|
||||
}
|
||||
}
|
||||
|
||||
#include "misc.h"
|
||||
#include "lexer.h"
|
||||
#include "mpyconfig.h"
|
||||
#include "parse.h"
|
||||
#include "compile.h"
|
||||
#include "runtime.h"
|
||||
|
||||
/*
|
||||
py_obj_t pyb_delay(py_obj_t count) {
|
||||
delay_ms(rt_get_int(count));
|
||||
return py_const_none;
|
||||
}
|
||||
|
||||
py_obj_t pyb_led(py_obj_t state) {
|
||||
led_state(PYB_LEDG1_PORT_NUM, rt_is_true(state));
|
||||
return state;
|
||||
}
|
||||
|
||||
py_obj_t pyb_sw() {
|
||||
if (sw_get()) {
|
||||
return py_const_true;
|
||||
} else {
|
||||
return py_const_false;
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
#include "asmthumb.h"
|
||||
typedef void (*fun_t)();
|
||||
|
||||
#include "ff.h"
|
||||
FATFS fatfs0;
|
||||
|
||||
int main() {
|
||||
// should disable JTAG
|
||||
|
||||
//qstr_init();
|
||||
//rt_init();
|
||||
|
||||
gpio_init();
|
||||
led_init();
|
||||
sw_init();
|
||||
lcd_init();
|
||||
|
||||
// print a message
|
||||
printf(" micro py board\n");
|
||||
|
||||
// flash to indicate we are alive!
|
||||
for (int i = 0; i < 2; i++) {
|
||||
led_state(PYB_LEDR1_PORT_NUM, 1);
|
||||
led_state(PYB_LEDR2_PORT_NUM, 0);
|
||||
delay_ms(200);
|
||||
led_state(PYB_LEDR1_PORT_NUM, 0);
|
||||
led_state(PYB_LEDR2_PORT_NUM, 1);
|
||||
delay_ms(200);
|
||||
}
|
||||
|
||||
led_state(PYB_LEDR1_PORT_NUM, 0);
|
||||
led_state(PYB_LEDR2_PORT_NUM, 0);
|
||||
led_state(PYB_LEDG1_PORT_NUM, 0);
|
||||
led_state(PYB_LEDG2_PORT_NUM, 0);
|
||||
|
||||
// get and print clock speeds
|
||||
// SYSCLK=168MHz, HCLK=168MHz, PCLK1=42MHz, PCLK2=84MHz
|
||||
/*
|
||||
{
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
printf("S=%lu H=%lu P1=%lu P2=%lu\n", rcc_clocks.SYSCLK_Frequency, rcc_clocks.HCLK_Frequency, rcc_clocks.PCLK1_Frequency, rcc_clocks.PCLK2_Frequency);
|
||||
delay_ms(1000);
|
||||
}
|
||||
*/
|
||||
|
||||
/*
|
||||
extern int _sidata;
|
||||
extern int _sdata;
|
||||
extern int _edata;
|
||||
extern int _sbss;
|
||||
extern int _ebss;
|
||||
delay_ms(2000);
|
||||
printf("_sidata=%04x\n", _sidata);
|
||||
printf("_sdata=%04x\n", _sdata);
|
||||
printf("_edata=%04x\n", _edata);
|
||||
printf("_sbss=%04x\n", _sbss);
|
||||
printf("_ebss=%04x\n", _ebss);
|
||||
//printf("sizeof(int)=%d\n", sizeof(int)); // 4
|
||||
delay_ms(2000);
|
||||
*/
|
||||
|
||||
//printf("init;al=%u\n", m_get_total_bytes_allocated()); // 1600, due to qstr_init
|
||||
//delay_ms(1000);
|
||||
|
||||
#if 0
|
||||
// Python!
|
||||
if (0) {
|
||||
//const char *pysrc = "def f():\n x=x+1\nprint(42)\n";
|
||||
const char *pysrc =
|
||||
// impl01.py
|
||||
/*
|
||||
"x = 0\n"
|
||||
"while x < 400:\n"
|
||||
" y = 0\n"
|
||||
" while y < 400:\n"
|
||||
" z = 0\n"
|
||||
" while z < 400:\n"
|
||||
" z = z + 1\n"
|
||||
" y = y + 1\n"
|
||||
" x = x + 1\n";
|
||||
*/
|
||||
// impl02.py
|
||||
"#@micropython.native\n"
|
||||
"def f():\n"
|
||||
" x = 0\n"
|
||||
" while x < 400:\n"
|
||||
" y = 0\n"
|
||||
" while y < 400:\n"
|
||||
" z = 0\n"
|
||||
" while z < 400:\n"
|
||||
" z = z + 1\n"
|
||||
" y = y + 1\n"
|
||||
" x = x + 1\n"
|
||||
"f()\n";
|
||||
/*
|
||||
"print('in python!')\n"
|
||||
"x = 0\n"
|
||||
"while x < 4:\n"
|
||||
" pyb_led(True)\n"
|
||||
" pyb_delay(201)\n"
|
||||
" pyb_led(False)\n"
|
||||
" pyb_delay(201)\n"
|
||||
" x = x + 1\n"
|
||||
"print('press me!')\n"
|
||||
"while True:\n"
|
||||
" pyb_led(pyb_sw())\n";
|
||||
*/
|
||||
/*
|
||||
// impl16.py
|
||||
"@micropython.asm_thumb\n"
|
||||
"def delay(r0):\n"
|
||||
" b(loop_entry)\n"
|
||||
" label(loop1)\n"
|
||||
" movw(r1, 55999)\n"
|
||||
" label(loop2)\n"
|
||||
" subs(r1, r1, 1)\n"
|
||||
" cmp(r1, 0)\n"
|
||||
" bgt(loop2)\n"
|
||||
" subs(r0, r0, 1)\n"
|
||||
" label(loop_entry)\n"
|
||||
" cmp(r0, 0)\n"
|
||||
" bgt(loop1)\n"
|
||||
"print('in python!')\n"
|
||||
"@micropython.native\n"
|
||||
"def flash(n):\n"
|
||||
" x = 0\n"
|
||||
" while x < n:\n"
|
||||
" pyb_led(True)\n"
|
||||
" delay(249)\n"
|
||||
" pyb_led(False)\n"
|
||||
" delay(249)\n"
|
||||
" x = x + 1\n"
|
||||
"flash(20)\n";
|
||||
*/
|
||||
|
||||
py_lexer_t *lex = py_lexer_from_str_len("<>", pysrc, strlen(pysrc), false);
|
||||
|
||||
if (0) {
|
||||
while (!py_lexer_is_kind(lex, PY_TOKEN_END)) {
|
||||
py_token_show(py_lexer_cur(lex));
|
||||
py_lexer_to_next(lex);
|
||||
delay_ms(1000);
|
||||
}
|
||||
} else {
|
||||
// nalloc=1740;6340;6836 -> 140;4600;496 bytes for lexer, parser, compiler
|
||||
printf("lex; al=%u\n", m_get_total_bytes_allocated());
|
||||
delay_ms(1000);
|
||||
py_parse_node_t pn = py_parse(lex, 0);
|
||||
//printf("----------------\n");
|
||||
printf("pars;al=%u\n", m_get_total_bytes_allocated());
|
||||
delay_ms(1000);
|
||||
//parse_node_show(pn, 0);
|
||||
py_compile(pn);
|
||||
printf("comp;al=%u\n", m_get_total_bytes_allocated());
|
||||
delay_ms(1000);
|
||||
|
||||
if (1) {
|
||||
// execute it!
|
||||
|
||||
// add some functions to the python namespace
|
||||
rt_store_name(qstr_from_str_static("pyb_delay"), rt_make_function_1(pyb_delay));
|
||||
rt_store_name(qstr_from_str_static("pyb_led"), rt_make_function_1(pyb_led));
|
||||
rt_store_name(qstr_from_str_static("pyb_sw"), rt_make_function_0(pyb_sw));
|
||||
|
||||
py_obj_t module_fun = rt_make_function_from_id(1);
|
||||
|
||||
led_state(PYB_LEDG1_PORT_NUM, 1);
|
||||
delay_ms(100);
|
||||
led_state(PYB_LEDG1_PORT_NUM, 0);
|
||||
py_obj_t ret = rt_call_function_0(module_fun);
|
||||
led_state(PYB_LEDG1_PORT_NUM, 1);
|
||||
delay_ms(100);
|
||||
led_state(PYB_LEDG1_PORT_NUM, 0);
|
||||
|
||||
printf("done! got: ");
|
||||
py_obj_print(ret);
|
||||
printf("\n");
|
||||
delay_ms(1000);
|
||||
printf("nalloc=%u\n", m_get_total_bytes_allocated());
|
||||
delay_ms(1000);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
// benchmark C version of impl02.py
|
||||
if (0) {
|
||||
led_state(PYB_LEDG1_PORT_NUM, 1);
|
||||
delay_ms(100);
|
||||
led_state(PYB_LEDG1_PORT_NUM, 0);
|
||||
impl02_c_version();
|
||||
led_state(PYB_LEDG1_PORT_NUM, 1);
|
||||
delay_ms(100);
|
||||
led_state(PYB_LEDG1_PORT_NUM, 0);
|
||||
}
|
||||
|
||||
// MMA testing
|
||||
if (0) {
|
||||
printf("1");
|
||||
mma_init();
|
||||
printf("2");
|
||||
mma_start(0x4c, 1);
|
||||
printf("3");
|
||||
mma_send_byte(0);
|
||||
printf("4");
|
||||
mma_stop();
|
||||
printf("5");
|
||||
mma_start(0x4c, 1);
|
||||
printf("6");
|
||||
mma_send_byte(0);
|
||||
printf("7");
|
||||
mma_restart(0x4c, 0);
|
||||
for (int i = 0; i <= 0xa; i++) {
|
||||
int data;
|
||||
if (i == 0xa) {
|
||||
data = mma_read_nack();
|
||||
} else {
|
||||
data = mma_read_ack();
|
||||
}
|
||||
printf(" %02x", data);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
mma_start(0x4c, 1);
|
||||
mma_send_byte(7); // mode
|
||||
mma_send_byte(1); // active mode
|
||||
mma_stop();
|
||||
|
||||
for (;;) {
|
||||
delay_ms(500);
|
||||
|
||||
mma_start(0x4c, 1);
|
||||
mma_send_byte(0);
|
||||
mma_restart(0x4c, 0);
|
||||
for (int i = 0; i <= 3; i++) {
|
||||
int data;
|
||||
if (i == 3) {
|
||||
data = mma_read_nack();
|
||||
printf(" %02x\n", data);
|
||||
} else {
|
||||
data = mma_read_ack() & 0x3f;
|
||||
if (data & 0x20) {
|
||||
data |= 0xc0;
|
||||
}
|
||||
printf(" % 2d", data);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// fatfs testing
|
||||
if (1) {
|
||||
FRESULT res = f_mount(&fatfs0, "0:", 1);
|
||||
if (res == FR_OK) {
|
||||
printf("mount success\n");
|
||||
} else if (res == FR_NO_FILESYSTEM) {
|
||||
res = f_mkfs("0:", 0, 0);
|
||||
if (res == FR_OK) {
|
||||
printf("mkfs success\n");
|
||||
} else {
|
||||
printf("mkfs fail %d\n", res);
|
||||
}
|
||||
} else {
|
||||
printf("mount fail %d\n", res);
|
||||
}
|
||||
|
||||
// write a file
|
||||
if (0) {
|
||||
FIL fp;
|
||||
f_open(&fp, "0:/boot.py", FA_WRITE | FA_CREATE_ALWAYS);
|
||||
UINT n;
|
||||
f_write(&fp, "# this is boot.py\n", 18, &n);
|
||||
printf("wrote %d\n", n);
|
||||
f_close(&fp);
|
||||
}
|
||||
|
||||
// read a file
|
||||
if (1) {
|
||||
FIL fp;
|
||||
f_open(&fp, "0:/boot.py", FA_READ);
|
||||
UINT n;
|
||||
char buf[20];
|
||||
f_read(&fp, buf, 18, &n);
|
||||
buf[n + 1] = 0;
|
||||
printf("read %d\n%s", n, buf);
|
||||
f_close(&fp);
|
||||
}
|
||||
|
||||
DWORD nclst;
|
||||
FATFS *fatfs;
|
||||
f_getfree("0:", &nclst, &fatfs);
|
||||
printf("free=%d\n", nclst * fatfs->csize * 512);
|
||||
|
||||
}
|
||||
|
||||
// SD card testing
|
||||
if (0) {
|
||||
//sdio_init();
|
||||
}
|
||||
|
||||
// USB VCP testing
|
||||
if (0) {
|
||||
//usb_vcp_init();
|
||||
}
|
||||
|
||||
// USB MSC testing
|
||||
if (1) {
|
||||
void usb_msc_init();
|
||||
usb_msc_init();
|
||||
}
|
||||
|
||||
int i = 0;
|
||||
int n = 0;
|
||||
|
||||
for (;;) {
|
||||
delay_ms(10);
|
||||
if (sw_get()) {
|
||||
led_state(PYB_LEDR1_PORT_NUM, 1);
|
||||
led_state(PYB_LEDG1_PORT_NUM, 0);
|
||||
i = 1 - i;
|
||||
if (i) {
|
||||
printf(" angel %05x.\n", n);
|
||||
//usb_vcp_send("hello!\r\n", 8);
|
||||
} else {
|
||||
printf(" mishka %4u.\n", n);
|
||||
//usb_vcp_send("angel!\r\n", 8);
|
||||
}
|
||||
n += 1;
|
||||
} else {
|
||||
led_state(PYB_LEDR1_PORT_NUM, 0);
|
||||
led_state(PYB_LEDG1_PORT_NUM, 1);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
void testf() {
|
||||
testf(1, 2, 3);
|
||||
testf(1, 2, 3, 4);
|
||||
testf(1, 2, 3, 4, 5);
|
||||
testf(1, 2, 3, 4, 5, 6);
|
||||
testf(1, 2, 3, 4, 5, 6, 7);
|
||||
}
|
||||
|
||||
int testg(int a, int b, int c, int d, int e) {
|
||||
return a + b + c + d + testh(e);
|
||||
}
|
||||
|
||||
int testh(int x, byte *y) {
|
||||
return x + (y[-2] << 2);
|
||||
}
|
||||
*/
|
||||
|
||||
/*
|
||||
void print_int(int x, int y, int z, int zz) {
|
||||
printf("I %x %x %x %x", x, y, z, zz);
|
||||
byte* ptr = (byte*)z;
|
||||
printf("\nP %02x %02x %02x %02x", ptr[-4], ptr[-3], ptr[-2], ptr[-1]);
|
||||
for (;;) {
|
||||
}
|
||||
}
|
||||
void print_int_0(int x) { printf("P0 %x", x); }
|
||||
void print_int_1(int x) { printf("P1 %x", x); }
|
||||
void print_int_2(int x) { printf("P2 %x", x); }
|
||||
void print_int_3(int x) { printf("P3 %x", x); }
|
||||
void print_int_4(int x) { printf("P4 %x", x); }
|
||||
|
||||
typedef struct _b_t {
|
||||
void (*m1)(void*, int);
|
||||
void (*m2)(void*, int);
|
||||
} b_t;
|
||||
typedef struct _a_t {
|
||||
b_t *b;
|
||||
} a_t;
|
||||
void b_m1(b_t*, int);
|
||||
void b_m2(b_t*, int);
|
||||
void f1(a_t *a) {
|
||||
a->b->m1(a->b, 2);
|
||||
a->b->m2(a->b, 4);
|
||||
b_m1(a->b, 2);
|
||||
b_m2(a->b, 4);
|
||||
}
|
||||
void b_m1(b_t *b, int x) {
|
||||
b->m1(b, x);
|
||||
}
|
||||
*/
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
#include <stdint.h>
|
||||
#include "std.h"
|
||||
|
||||
static uint32_t mem = 0;
|
||||
|
||||
void *malloc(size_t n) {
|
||||
if (mem == 0) {
|
||||
mem = 0x20008000; // need to use big ram block so we can execute code from it; start up a bit in case that's where bss is...?
|
||||
}
|
||||
void *ptr = (void*)mem;
|
||||
mem = (mem + n + 3) & (~3);
|
||||
if (mem > 0x20000000 + 0x18000) {
|
||||
void __fatal_error(const char*);
|
||||
__fatal_error("out of memory");
|
||||
}
|
||||
return ptr;
|
||||
}
|
||||
|
||||
void free(void *ptr) {
|
||||
}
|
||||
|
||||
void *calloc(size_t sz, size_t n) {
|
||||
char *ptr = malloc(sz * n);
|
||||
for (int i = 0; i < sz * n; i++) {
|
||||
ptr[i] = 0;
|
||||
}
|
||||
return ptr;
|
||||
}
|
||||
|
||||
void *realloc(void *ptr, size_t n) {
|
||||
return malloc(n);
|
||||
}
|
||||
|
||||
void __assert_func() {
|
||||
printf("\nASSERT FAIL!");
|
||||
for (;;) {
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
// options to control how Micro Python is built
|
||||
|
||||
#define MICROPY_ENABLE_FLOAT (1)
|
||||
#define MICROPY_EMIT_CPYTHON (0)
|
||||
#define MICROPY_EMIT_X64 (0)
|
||||
#define MICROPY_EMIT_THUMB (1)
|
||||
#define MICROPY_EMIT_INLINE_THUMB (1)
|
||||
|
||||
// type definitions for the specific machine
|
||||
|
||||
typedef int32_t machine_int_t; // must be pointer size
|
||||
typedef uint32_t machine_uint_t; // must be pointer size
|
||||
typedef void *machine_ptr_t; // must be of pointer size
|
||||
typedef float machine_float_t;
|
||||
|
|
@ -0,0 +1,277 @@
|
|||
#include <stdarg.h>
|
||||
#include "std.h"
|
||||
|
||||
#define PF_FLAG_LEFT_ADJUST (0x01)
|
||||
#define PF_FLAG_SHOW_SIGN (0x02)
|
||||
#define PF_FLAG_SPACE_SIGN (0x04)
|
||||
#define PF_FLAG_NO_TRAILZ (0x08)
|
||||
#define PF_FLAG_ZERO_PAD (0x10)
|
||||
|
||||
// tricky; we compute pad string by: pad_chars + (flags & PF_FLAG_ZERO_PAD)
|
||||
#define PF_PAD_SIZE PF_FLAG_ZERO_PAD
|
||||
static const char *pad_chars = " 0000000000000000";
|
||||
|
||||
typedef struct _pfenv_t {
|
||||
void *data;
|
||||
void (*print_strn)(void *, const char *str, unsigned int len);
|
||||
} pfenv_t;
|
||||
|
||||
static void print_str_dummy(void *data, const char *str, unsigned int len) {
|
||||
}
|
||||
|
||||
pfenv_t pfenv_dummy = {0, print_str_dummy};
|
||||
|
||||
static int pfenv_print_strn(pfenv_t *pfenv, const char *str, unsigned int len, int flags, int width) {
|
||||
int pad = width - len;
|
||||
if (pad > 0 && (flags & PF_FLAG_LEFT_ADJUST) == 0) {
|
||||
while (pad > 0) {
|
||||
int p = pad;
|
||||
if (p > PF_PAD_SIZE)
|
||||
p = PF_PAD_SIZE;
|
||||
pfenv->print_strn(pfenv->data, pad_chars + (flags & PF_FLAG_ZERO_PAD), p);
|
||||
pad -= p;
|
||||
}
|
||||
}
|
||||
pfenv->print_strn(pfenv->data, str, len);
|
||||
while (pad > 0) {
|
||||
int p = pad;
|
||||
if (p > PF_PAD_SIZE)
|
||||
p = PF_PAD_SIZE;
|
||||
pfenv->print_strn(pfenv->data, pad_chars, p);
|
||||
pad -= p;
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
// enough room for 32 signed number
|
||||
#define INT_BUF_SIZE (12)
|
||||
|
||||
static int pfenv_print_int(pfenv_t *pfenv, unsigned int x, int sgn, int base, int base_char, int flags, int width) {
|
||||
char sign = 0;
|
||||
if (sgn) {
|
||||
if ((int)x < 0) {
|
||||
sign = '-';
|
||||
x = -x;
|
||||
} else if (flags & PF_FLAG_SHOW_SIGN) {
|
||||
sign = '+';
|
||||
} else if (flags & PF_FLAG_SPACE_SIGN) {
|
||||
sign = ' ';
|
||||
}
|
||||
}
|
||||
|
||||
char buf[INT_BUF_SIZE];
|
||||
char *b = buf + INT_BUF_SIZE;
|
||||
|
||||
if (x == 0) {
|
||||
*(--b) = '0';
|
||||
} else {
|
||||
do {
|
||||
int c = x % base;
|
||||
x /= base;
|
||||
if (c >= 10) {
|
||||
c += base_char - 10;
|
||||
} else {
|
||||
c += '0';
|
||||
}
|
||||
*(--b) = c;
|
||||
} while (b > buf && x != 0);
|
||||
}
|
||||
|
||||
if (b > buf && sign != 0) {
|
||||
*(--b) = sign;
|
||||
}
|
||||
|
||||
return pfenv_print_strn(pfenv, b, buf + INT_BUF_SIZE - b, flags, width);
|
||||
}
|
||||
|
||||
void pfenv_prints(pfenv_t *pfenv, const char *str) {
|
||||
pfenv->print_strn(pfenv->data, str, strlen(str));
|
||||
}
|
||||
|
||||
int pfenv_printf(pfenv_t *pfenv, const char *fmt, va_list args) {
|
||||
int chrs = 0;
|
||||
for (;;) {
|
||||
{
|
||||
const char *f = fmt;
|
||||
while (*f != '\0' && *f != '%') {
|
||||
++f; // XXX UTF8 advance char
|
||||
}
|
||||
if (f > fmt) {
|
||||
pfenv->print_strn(pfenv->data, fmt, f - fmt);
|
||||
chrs += f - fmt;
|
||||
fmt = f;
|
||||
}
|
||||
}
|
||||
|
||||
if (*fmt == '\0') {
|
||||
break;
|
||||
}
|
||||
|
||||
// move past % character
|
||||
++fmt;
|
||||
|
||||
// parse flags, if they exist
|
||||
int flags = 0;
|
||||
while (*fmt != '\0') {
|
||||
if (*fmt == '-') flags |= PF_FLAG_LEFT_ADJUST;
|
||||
else if (*fmt == '+') flags |= PF_FLAG_SHOW_SIGN;
|
||||
else if (*fmt == ' ') flags |= PF_FLAG_SPACE_SIGN;
|
||||
else if (*fmt == '!') flags |= PF_FLAG_NO_TRAILZ;
|
||||
else if (*fmt == '0') flags |= PF_FLAG_ZERO_PAD;
|
||||
else break;
|
||||
++fmt;
|
||||
}
|
||||
|
||||
// parse width, if it exists
|
||||
int width = 0;
|
||||
for (; '0' <= *fmt && *fmt <= '9'; ++fmt) {
|
||||
width = width * 10 + *fmt - '0';
|
||||
}
|
||||
|
||||
// parse precision, if it exists
|
||||
int prec = -1;
|
||||
if (*fmt == '.') {
|
||||
++fmt;
|
||||
if (*fmt == '*') {
|
||||
++fmt;
|
||||
prec = va_arg(args, int);
|
||||
} else {
|
||||
prec = 0;
|
||||
for (; '0' <= *fmt && *fmt <= '9'; ++fmt) {
|
||||
prec = prec * 10 + *fmt - '0';
|
||||
}
|
||||
}
|
||||
if (prec < 0) {
|
||||
prec = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// parse long specifiers (current not used)
|
||||
//bool long_arg = false;
|
||||
if (*fmt == 'l') {
|
||||
++fmt;
|
||||
//long_arg = true;
|
||||
}
|
||||
|
||||
if (*fmt == '\0') {
|
||||
break;
|
||||
}
|
||||
|
||||
switch (*fmt) {
|
||||
case 'b':
|
||||
if (va_arg(args, int)) {
|
||||
chrs += pfenv_print_strn(pfenv, "true", 4, flags, width);
|
||||
} else {
|
||||
chrs += pfenv_print_strn(pfenv, "false", 5, flags, width);
|
||||
}
|
||||
break;
|
||||
case 'c':
|
||||
{
|
||||
char str = va_arg(args, int);
|
||||
chrs += pfenv_print_strn(pfenv, &str, 1, flags, width);
|
||||
break;
|
||||
}
|
||||
case 's':
|
||||
{
|
||||
const char *str = va_arg(args, const char*);
|
||||
if (str) {
|
||||
if (prec < 0) {
|
||||
prec = strlen(str);
|
||||
}
|
||||
chrs += pfenv_print_strn(pfenv, str, prec, flags, width);
|
||||
} else {
|
||||
chrs += pfenv_print_strn(pfenv, "(null)", 6, flags, width);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case 'u':
|
||||
chrs += pfenv_print_int(pfenv, va_arg(args, int), 0, 10, 'a', flags, width);
|
||||
break;
|
||||
case 'd':
|
||||
chrs += pfenv_print_int(pfenv, va_arg(args, int), 1, 10, 'a', flags, width);
|
||||
break;
|
||||
case 'x':
|
||||
case 'p': // ?
|
||||
chrs += pfenv_print_int(pfenv, va_arg(args, int), 0, 16, 'a', flags, width);
|
||||
break;
|
||||
case 'X':
|
||||
case 'P': // ?
|
||||
chrs += pfenv_print_int(pfenv, va_arg(args, int), 0, 16, 'A', flags, width);
|
||||
break;
|
||||
default:
|
||||
pfenv->print_strn(pfenv->data, fmt, 1);
|
||||
chrs += 1;
|
||||
break;
|
||||
}
|
||||
++fmt;
|
||||
}
|
||||
return chrs;
|
||||
}
|
||||
|
||||
void lcd_print_strn(const char *str, unsigned int len);
|
||||
|
||||
void xxx(void *data, const char *str, unsigned int len) {
|
||||
lcd_print_strn(str, len);
|
||||
}
|
||||
|
||||
pfenv_t pfenv_stdout = {0, xxx};
|
||||
|
||||
int printf(const char *fmt, ...) {
|
||||
//pfenv_t pfenv;
|
||||
//pfenv.data = 0;
|
||||
//pfenv.print_strn = xxx;
|
||||
va_list args;
|
||||
va_start(args, fmt);
|
||||
return pfenv_printf(&pfenv_stdout, fmt, args);
|
||||
}
|
||||
|
||||
// need this because gcc optimises printf("%c", c) -> putchar(c), and printf("a") -> putchar('a')
|
||||
int putchar(int c) {
|
||||
char chr = c;
|
||||
xxx(0, &chr, 1);
|
||||
return chr;
|
||||
}
|
||||
|
||||
// need this because gcc optimises printf("string\n") -> puts("string")
|
||||
int puts(const char *s) {
|
||||
xxx(0, s, strlen(s));
|
||||
char chr = '\n';
|
||||
xxx(0, &chr, 1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
typedef struct _strn_pfenv_t {
|
||||
char *cur;
|
||||
size_t remain;
|
||||
} strn_pfenv_t;
|
||||
|
||||
void strn_print_strn(void *data, const char *str, unsigned int len) {
|
||||
strn_pfenv_t *strn_pfenv = data;
|
||||
if (len > strn_pfenv->remain) {
|
||||
len = strn_pfenv->remain;
|
||||
}
|
||||
memcpy(strn_pfenv->cur, str, len);
|
||||
strn_pfenv->cur += len;
|
||||
strn_pfenv->remain -= len;
|
||||
}
|
||||
|
||||
int snprintf(char *str, size_t size, const char *fmt, ...) {
|
||||
strn_pfenv_t strn_pfenv;
|
||||
strn_pfenv.cur = str;
|
||||
strn_pfenv.remain = size;
|
||||
pfenv_t pfenv;
|
||||
pfenv.data = &strn_pfenv;
|
||||
pfenv.print_strn = strn_print_strn;
|
||||
va_list args;
|
||||
va_start(args, fmt);
|
||||
int len = pfenv_printf(&pfenv, fmt, args);
|
||||
// add terminating null byte
|
||||
if (size > 0) {
|
||||
if (strn_pfenv.remain == 0) {
|
||||
strn_pfenv.cur[-1] = 0;
|
||||
} else {
|
||||
strn_pfenv.cur[0] = 0;
|
||||
}
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
|
@ -0,0 +1,515 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32f40xx.s
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief STM32F40xx/41xx Devices vector table for RIDE7 toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
* - Set the vector table entries with the exceptions ISR address
|
||||
* - Configure the clock system and the external SRAM mounted on
|
||||
* STM324xG-EVAL board to be used as data memory (optional,
|
||||
* to be enabled by user)
|
||||
* - Branches to main in the C library (which eventually
|
||||
* calls main()).
|
||||
* After Reset the Cortex-M4 processor is in Thread mode,
|
||||
* priority is Privileged, and the Stack is set to Main.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m3
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval : None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window WatchDog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detection */
|
||||
.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||
.word FLASH_IRQHandler /* FLASH */
|
||||
.word RCC_IRQHandler /* RCC */
|
||||
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word CAN1_TX_IRQHandler /* CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
|
||||
.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
|
||||
.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FSMC_IRQHandler /* FSMC */
|
||||
.word SDIO_IRQHandler /* SDIO */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word CRYP_IRQHandler /* CRYP crypto */
|
||||
.word HASH_RNG_IRQHandler /* Hash and Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FSMC_IRQHandler
|
||||
.thumb_set FSMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_SCE_IRQHandler
|
||||
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRYP_IRQHandler
|
||||
.thumb_set CRYP_IRQHandler,Default_Handler
|
||||
|
||||
.weak HASH_RNG_IRQHandler
|
||||
.thumb_set HASH_RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
typedef unsigned int size_t;
|
||||
|
||||
void __assert_func();
|
||||
|
||||
void *malloc(size_t n);
|
||||
void free(void *ptr);
|
||||
void *calloc(size_t sz, size_t n);
|
||||
void *realloc(void *ptr, size_t n);
|
||||
|
||||
void *memcpy(void *dest, const void *src, size_t n);
|
||||
void *memset(void *s, int c, size_t n);
|
||||
|
||||
int strlen(const char *str);
|
||||
int strcmp(const char *s1, const char *s2);
|
||||
int strncmp(const char *s1, const char *s2, size_t n);
|
||||
char *strndup(const char *s, size_t n);
|
||||
char *strcpy(char *dest, const char *src);
|
||||
char *strcat(char *dest, const char *src);
|
||||
|
||||
int printf(const char *fmt, ...);
|
||||
int snprintf(char *str, size_t size, const char *fmt, ...);
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
GNU linker script for STM32F405
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x100000 /* 1 MiB */
|
||||
RAM_CCM (xrw) : ORIGIN = 0x10000000, LENGTH = 0x010000 /* 64 KiB */
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x020000 /* 128 KiB */
|
||||
}
|
||||
|
||||
/* define stack size and heap size here */
|
||||
stack_size = 2048;
|
||||
heap_size = 0x4000; /* 16KiB */
|
||||
|
||||
/* define beginning and ending of stack */
|
||||
_stack_start = ORIGIN(RAM) + LENGTH(RAM);
|
||||
_stack_end = _stack_start - stack_size;
|
||||
_estack = _stack_end;
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
/* *(.glue_7) */ /* glue arm to thumb code */
|
||||
/* *(.glue_7t) */ /* glue thumb to arm code */
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = .;
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data : AT ( _sidata )
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* Used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
. = ALIGN(4);
|
||||
.heap :
|
||||
{
|
||||
_heap_start = .;
|
||||
. = . + heap_size;
|
||||
} > RAM
|
||||
|
||||
. = ALIGN(4);
|
||||
. = _stack_end;
|
||||
.stack :
|
||||
{
|
||||
. = . + stack_size;
|
||||
} > RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/*
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
*/
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,255 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32fxxx_it.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief Main Interrupt Service Routines.
|
||||
* This file provides all exceptions handler and peripherals interrupt
|
||||
* service routine.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32fxxx_it.h"
|
||||
#include "stm32f4xx_exti.h"
|
||||
#include "usb_core.h"
|
||||
//#include "usbd_core.h"
|
||||
|
||||
//#include "usbd_cdc_core.h"
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
extern USB_OTG_CORE_HANDLE USB_OTG_dev;
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
extern uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
|
||||
|
||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
extern uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
|
||||
extern uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev);
|
||||
#endif
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/******************************************************************************/
|
||||
/* Cortex-M Processor Exceptions Handlers */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles NMI exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Hard Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Hard Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Memory Manage exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void MemManage_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Memory Manage exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Bus Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void BusFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Bus Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Usage Fault exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void UsageFault_Handler(void)
|
||||
{
|
||||
/* Go to infinite loop when Usage Fault exception occurs */
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SVCall exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SVC_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles Debug Monitor exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DebugMon_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles PendSVC exception.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PendSV_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SysTick Handler.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles EXTI15_10_IRQ Handler.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef USE_USB_OTG_FS
|
||||
void OTG_FS_WKUP_IRQHandler(void)
|
||||
{
|
||||
if(USB_OTG_dev.cfg.low_power)
|
||||
{
|
||||
*(uint32_t *)(0xE000ED10) &= 0xFFFFFFF9 ;
|
||||
SystemInit();
|
||||
USB_OTG_UngateClock(&USB_OTG_dev);
|
||||
}
|
||||
EXTI_ClearITPendingBit(EXTI_Line18);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief This function handles EXTI15_10_IRQ Handler.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef USE_USB_OTG_HS
|
||||
void OTG_HS_WKUP_IRQHandler(void)
|
||||
{
|
||||
if(USB_OTG_dev.cfg.low_power)
|
||||
{
|
||||
*(uint32_t *)(0xE000ED10) &= 0xFFFFFFF9 ;
|
||||
SystemInit();
|
||||
USB_OTG_UngateClock(&USB_OTG_dev);
|
||||
}
|
||||
EXTI_ClearITPendingBit(EXTI_Line20);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief This function handles OTG_HS Handler.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef USE_USB_OTG_HS
|
||||
void OTG_HS_IRQHandler(void)
|
||||
#else
|
||||
void OTG_FS_IRQHandler(void)
|
||||
#endif
|
||||
{
|
||||
USBD_OTG_ISR_Handler (&USB_OTG_dev);
|
||||
}
|
||||
|
||||
#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
|
||||
/**
|
||||
* @brief This function handles EP1_IN Handler.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void OTG_HS_EP1_IN_IRQHandler(void)
|
||||
{
|
||||
USBD_OTG_EP1IN_ISR_Handler (&USB_OTG_dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles EP1_OUT Handler.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void OTG_HS_EP1_OUT_IRQHandler(void)
|
||||
{
|
||||
USBD_OTG_EP1OUT_ISR_Handler (&USB_OTG_dev);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief This function handles SDIO global interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_IRQHandler(void)
|
||||
{
|
||||
/* Process All SDIO Interrupt Sources */
|
||||
//SD_ProcessIRQSrc();
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
/* STM32Fxxx Peripherals Interrupt Handlers */
|
||||
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
|
||||
/* available peripheral interrupt handler's name please refer to the startup */
|
||||
/* file (startup_stm32fxxx.s). */
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles PPP interrupt request.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
/*void PPP_IRQHandler(void)
|
||||
{
|
||||
}*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32fxxx_it.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 19-March-2012
|
||||
* @brief This file contains the headers of the interrupt handlers.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32Fxxx_IT_H
|
||||
#define __STM32Fxxx_IT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "usb_conf.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32Fxxx_IT_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
#include <stdint.h>
|
||||
#include "std.h"
|
||||
|
||||
void *memcpy(void *dest, const void *src, size_t n) {
|
||||
// TODO align and copy 32 bits at a time
|
||||
uint8_t *d = dest;
|
||||
const uint8_t *s = src;
|
||||
for (; n > 0; n--) {
|
||||
*d++ = *s++;
|
||||
}
|
||||
return dest;
|
||||
}
|
||||
|
||||
void *memset(void *s, int c, size_t n) {
|
||||
uint8_t *s2 = s;
|
||||
for (; n > 0; n--) {
|
||||
*s2++ = c;
|
||||
}
|
||||
return s;
|
||||
}
|
||||
|
||||
int strlen(const char *str) {
|
||||
int len = 0;
|
||||
for (const char *s = str; *s; s++) {
|
||||
len += 1;
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
int strcmp(const char *s1, const char *s2) {
|
||||
while (*s1 && *s2) {
|
||||
char c1 = *s1++; // XXX UTF8 get char, next char
|
||||
char c2 = *s2++; // XXX UTF8 get char, next char
|
||||
if (c1 < c2) return -1;
|
||||
else if (c1 > c2) return 1;
|
||||
}
|
||||
if (*s2) return -1;
|
||||
else if (*s1) return 1;
|
||||
else return 0;
|
||||
}
|
||||
|
||||
int strncmp(const char *s1, const char *s2, size_t n) {
|
||||
while (*s1 && *s2 && n > 0) {
|
||||
char c1 = *s1++; // XXX UTF8 get char, next char
|
||||
char c2 = *s2++; // XXX UTF8 get char, next char
|
||||
n--;
|
||||
if (c1 < c2) return -1;
|
||||
else if (c1 > c2) return 1;
|
||||
}
|
||||
if (n == 0) return 0;
|
||||
else if (*s2) return -1;
|
||||
else if (*s1) return 1;
|
||||
else return 0;
|
||||
}
|
||||
|
||||
char *strndup(const char *s, size_t n) {
|
||||
size_t len = strlen(s);
|
||||
if (n > len) {
|
||||
n = len;
|
||||
}
|
||||
char *s2 = malloc(n + 1);
|
||||
memcpy(s2, s, n);
|
||||
s2[n] = '\0';
|
||||
return s2;
|
||||
}
|
||||
|
||||
char *strcpy(char *dest, const char *src) {
|
||||
char *d = dest;
|
||||
while (*src) {
|
||||
*d++ = *src++;
|
||||
}
|
||||
*d = '\0';
|
||||
return dest;
|
||||
}
|
||||
|
||||
// needed because gcc optimises strcpy + strcat to this
|
||||
char *stpcpy(char *dest, const char *src) {
|
||||
while (*src) {
|
||||
*dest++ = *src++;
|
||||
}
|
||||
*dest = '\0';
|
||||
return dest;
|
||||
}
|
||||
|
||||
char *strcat(char *dest, const char *src) {
|
||||
char *d = dest;
|
||||
while (*d) {
|
||||
d++;
|
||||
}
|
||||
while (*src) {
|
||||
*d++ = *src++;
|
||||
}
|
||||
*d = '\0';
|
||||
return dest;
|
||||
}
|
||||
|
|
@ -0,0 +1,561 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f4xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.0
|
||||
* @date 11-January-2013
|
||||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
|
||||
* This file contains the system clock configuration for STM32F4xx devices,
|
||||
* and is generated by the clock configuration tool
|
||||
* stm32f4xx_Clock_Configuration_V1.1.0.xls
|
||||
*
|
||||
* 1. This file provides two functions and one global variable to be called from
|
||||
* user application:
|
||||
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
|
||||
* and Divider factors, AHB/APBx prescalers and Flash settings),
|
||||
* depending on the configuration made in the clock xls tool.
|
||||
* This function is called at startup just after reset and
|
||||
* before branch to main program. This call is made inside
|
||||
* the "startup_stm32f4xx.s" file.
|
||||
*
|
||||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
|
||||
* by the user application to setup the SysTick
|
||||
* timer or configure other parameters.
|
||||
*
|
||||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
|
||||
* be called whenever the core clock is changed
|
||||
* during program execution.
|
||||
*
|
||||
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
|
||||
* configure the system clock before to branch to main program.
|
||||
*
|
||||
* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and HSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
|
||||
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
||||
* 5. This file configures the system clock as follows:
|
||||
*=============================================================================
|
||||
*=============================================================================
|
||||
* Supported STM32F40xx/41xx/427x/437x devices
|
||||
*-----------------------------------------------------------------------------
|
||||
* System Clock source | PLL (HSE)
|
||||
*-----------------------------------------------------------------------------
|
||||
* SYSCLK(Hz) | 168000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* HCLK(Hz) | 168000000
|
||||
*-----------------------------------------------------------------------------
|
||||
* AHB Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 4
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency(Hz) | 8000000 changed dpgeorge
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_M | 8 changed dpgeorge
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_N | 336
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_P | 2
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL_Q | 7
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_N | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLLI2S_R | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* I2S input clock | NA
|
||||
*-----------------------------------------------------------------------------
|
||||
* VDD(V) | 3.3
|
||||
*-----------------------------------------------------------------------------
|
||||
* Main regulator output voltage | Scale1 mode
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency(WS) | 5
|
||||
*-----------------------------------------------------------------------------
|
||||
* Prefetch Buffer | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Instruction cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Data cache | ON
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB OTG FS, | Disabled
|
||||
* SDIO and RNG clock |
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f4xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32f4xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
|
||||
/************************* Miscellaneous Configuration ************************/
|
||||
/*!< Uncomment the following line if you need to use external SRAM mounted
|
||||
on STM324xG_EVAL/STM324x7I_EVAL boards as data memory */
|
||||
/* #define DATA_IN_ExtSRAM */
|
||||
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/******************************************************************************/
|
||||
|
||||
/************************* PLL Parameters *************************************/
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
|
||||
#define PLL_M 8
|
||||
#define PLL_N 336
|
||||
|
||||
/* SYSCLK = PLL_VCO / PLL_P */
|
||||
#define PLL_P 2
|
||||
|
||||
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
|
||||
#define PLL_Q 7
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t SystemCoreClock = 168000000;
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
static void SystemInit_ExtMemCtl(void);
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F4xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemFrequency variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
/* FPU settings ------------------------------------------------------------*/
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||
#endif
|
||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||
/* Set HSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000001;
|
||||
|
||||
/* Reset CFGR register */
|
||||
RCC->CFGR = 0x00000000;
|
||||
|
||||
/* Reset HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xFEF6FFFF;
|
||||
|
||||
/* Reset PLLCFGR register */
|
||||
RCC->PLLCFGR = 0x24003010;
|
||||
|
||||
/* Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/* Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
SystemInit_ExtMemCtl();
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
/* Configure the System clock source, PLL Multiplier and Divider factors,
|
||||
AHB/APBx prescalers and Flash settings ----------------------------------*/
|
||||
SetSysClock();
|
||||
|
||||
/* Configure the Vector Table location add offset address ------------------*/
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
* The SystemCoreClock variable contains the core clock (HCLK), it can
|
||||
* be used by the user application to setup the SysTick timer or configure
|
||||
* other parameters.
|
||||
*
|
||||
* @note Each time the core clock (HCLK) changes, this function must be called
|
||||
* to update SystemCoreClock variable value. Otherwise, any configuration
|
||||
* based on this variable will be incorrect.
|
||||
*
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
|
||||
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
*
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* HSI used as system clock source */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04: /* HSE used as system clock source */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08: /* PLL used as system clock source */
|
||||
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
|
||||
SYSCLK = PLL_VCO / PLL_P
|
||||
*/
|
||||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
|
||||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
|
||||
|
||||
if (pllsource != 0)
|
||||
{
|
||||
/* HSE used as PLL clock source */
|
||||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSI used as PLL clock source */
|
||||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
|
||||
}
|
||||
|
||||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
|
||||
SystemCoreClock = pllvco/pllp;
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK frequency --------------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
|
||||
* AHB/APBx prescalers and Flash settings
|
||||
* @Note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
/******************************************************************************/
|
||||
/* PLL (clocked by HSE) used as System clock source */
|
||||
/******************************************************************************/
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
/* Enable HSE */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
PWR->CR |= PWR_CR_VOS;
|
||||
|
||||
/* HCLK = SYSCLK / 1*/
|
||||
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
|
||||
|
||||
/* PCLK2 = HCLK / 2*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
|
||||
|
||||
/* PCLK1 = HCLK / 4*/
|
||||
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
|
||||
|
||||
/* Configure the main PLL */
|
||||
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
|
||||
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
|
||||
|
||||
/* Enable the main PLL */
|
||||
RCC->CR |= RCC_CR_PLLON;
|
||||
|
||||
/* Wait till the main PLL is ready */
|
||||
while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
|
||||
FLASH->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||
|
||||
/* Wait till the main PLL is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* If HSE fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Setup the external memory controller. Called in startup_stm32f4xx.s
|
||||
* before jump to __main
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
#ifdef DATA_IN_ExtSRAM
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f4xx.s before jump to main.
|
||||
* This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
|
||||
* This SRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/*
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
+ SRAM pins assignment +
|
||||
+-------------------+--------------------+------------------+------------------+
|
||||
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
|
||||
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
|
||||
| PD4 <-> FSMC_NOE | PE2 <-> FSMC_A23 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
|
||||
| PD5 <-> FSMC_NWE | PE3 <-> FSMC_A19 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
|
||||
| PD8 <-> FSMC_D13 | PE4 <-> FSMC_A20 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
|
||||
| PD9 <-> FSMC_D14 | PE5 <-> FSMC_A21 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
|
||||
| PD10 <-> FSMC_D15 | PE6 <-> FSMC_A22 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
|
||||
| PD11 <-> FSMC_A16 | PE7 <-> FSMC_D4 | PF13 <-> FSMC_A7 |------------------+
|
||||
| PD12 <-> FSMC_A17 | PE8 <-> FSMC_D5 | PF14 <-> FSMC_A8 |
|
||||
| PD13 <-> FSMC_A18 | PE9 <-> FSMC_D6 | PF15 <-> FSMC_A9 |
|
||||
| PD14 <-> FSMC_D0 | PE10 <-> FSMC_D7 |------------------+
|
||||
| PD15 <-> FSMC_D1 | PE11 <-> FSMC_D8 |
|
||||
+-------------------| PE12 <-> FSMC_D9 |
|
||||
| PE13 <-> FSMC_D10 |
|
||||
| PE14 <-> FSMC_D11 |
|
||||
| PE15 <-> FSMC_D12 |
|
||||
+--------------------+
|
||||
*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR |= 0x00000078;
|
||||
|
||||
/* Connect PDx pins to FSMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00cc00cc;
|
||||
GPIOD->AFR[1] = 0xcccccccc;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xaaaa0a0a;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xffff0f0f;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FSMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xcccccccc;
|
||||
GPIOE->AFR[1] = 0xcccccccc;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xaaaaaaaa;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xffffffff;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FSMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00cccccc;
|
||||
GPIOF->AFR[1] = 0xcccc0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xaa000aaa;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xff000fff;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FSMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00cccccc;
|
||||
GPIOG->AFR[1] = 0x000000c0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00080aaa;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000c0fff;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FSMC Configuration ------------------------------------------------------*/
|
||||
/* Enable the FSMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001011;
|
||||
FSMC_Bank1->BTCR[3] = 0x00000201;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
/*
|
||||
Bank1_SRAM2 is configured as follow:
|
||||
|
||||
p.FSMC_AddressSetupTime = 1;
|
||||
p.FSMC_AddressHoldTime = 0;
|
||||
p.FSMC_DataSetupTime = 2;
|
||||
p.FSMC_BusTurnAroundDuration = 0;
|
||||
p.FSMC_CLKDivision = 0;
|
||||
p.FSMC_DataLatency = 0;
|
||||
p.FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
|
||||
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
|
||||
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
|
||||
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
|
||||
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
|
||||
*/
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
#include "usbd_cdc_core.h"
|
||||
#include "usbd_msc_core.h"
|
||||
#include "usbd_usr.h"
|
||||
#include "usbd_desc.h"
|
||||
|
||||
//extern CDC_IF_Prop_TypeDef APP_FOPS;
|
||||
|
||||
USB_OTG_CORE_HANDLE USB_OTG_dev;
|
||||
|
||||
void usb_vcp_init() {
|
||||
//USBD_Init(&USB_OTG_dev, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_CDC_cb, &USR_cb);
|
||||
}
|
||||
|
||||
void usb_vcp_send(const char* str, int len) {
|
||||
//APP_FOPS.pIf_DataTx(str, len);
|
||||
}
|
||||
|
||||
void usb_msc_init() {
|
||||
USBD_Init(&USB_OTG_dev, USB_OTG_FS_CORE_ID, &USR_desc, &USBD_MSC_cb, &USR_cb);
|
||||
}
|
||||
Loading…
Reference in New Issue