2008-01-30 05:30:07 -07:00
|
|
|
/*
|
|
|
|
* Defines x86 CPU feature bits
|
|
|
|
*/
|
2008-10-22 23:26:29 -06:00
|
|
|
#ifndef _ASM_X86_CPUFEATURE_H
|
|
|
|
#define _ASM_X86_CPUFEATURE_H
|
2008-01-30 05:30:07 -07:00
|
|
|
|
2012-10-02 11:01:26 -06:00
|
|
|
#ifndef _ASM_X86_REQUIRED_FEATURES_H
|
2008-01-30 05:30:07 -07:00
|
|
|
#include <asm/required-features.h>
|
2012-10-02 11:01:26 -06:00
|
|
|
#endif
|
2008-01-30 05:30:07 -07:00
|
|
|
|
2010-07-07 18:29:18 -06:00
|
|
|
#define NCAPINTS 10 /* N 32-bit words worth of info */
|
2013-03-20 08:07:23 -06:00
|
|
|
#define NBUGINTS 1 /* N 32-bit bug flags */
|
2008-01-30 05:30:07 -07:00
|
|
|
|
2008-08-27 18:56:44 -06:00
|
|
|
/*
|
|
|
|
* Note: If the comment begins with a quoted string, that string is used
|
|
|
|
* in /proc/cpuinfo instead of the macro name. If the string is "",
|
|
|
|
* this feature bit is not displayed in /proc/cpuinfo at all.
|
|
|
|
*/
|
2008-01-30 05:30:07 -07:00
|
|
|
|
|
|
|
/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
|
|
|
|
#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
|
|
|
|
#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
|
|
|
|
#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
|
|
|
|
#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
|
|
|
|
#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
|
2008-08-27 22:20:07 -06:00
|
|
|
#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
|
2009-05-02 23:41:35 -06:00
|
|
|
#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Exception */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
|
|
|
|
#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
|
|
|
|
#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
|
|
|
|
#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
|
|
|
|
#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
|
|
|
|
#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
|
2008-08-27 22:20:07 -06:00
|
|
|
#define X86_FEATURE_CMOV (0*32+15) /* CMOV instructions */
|
|
|
|
/* (plus FCMOVcc, FCOMI with FPU) */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
|
|
|
|
#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
|
|
|
|
#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
|
2008-08-27 22:20:07 -06:00
|
|
|
#define X86_FEATURE_CLFLSH (0*32+19) /* "clflush" CLFLUSH instruction */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_DS (0*32+21) /* "dts" Debug Store */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
|
|
|
|
#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
|
|
|
|
#define X86_FEATURE_XMM (0*32+25) /* "sse" */
|
|
|
|
#define X86_FEATURE_XMM2 (0*32+26) /* "sse2" */
|
|
|
|
#define X86_FEATURE_SELFSNOOP (0*32+27) /* "ss" CPU self snoop */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_ACC (0*32+29) /* "tm" Automatic clock control */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
|
2008-01-30 05:30:07 -07:00
|
|
|
|
|
|
|
/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
|
|
|
|
/* Don't duplicate feature flags which are redundant with Intel! */
|
|
|
|
#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
|
|
|
|
#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
|
|
|
|
#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
|
|
|
|
#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_FXSR_OPT (1*32+25) /* FXSAVE/FXRSTOR optimizations */
|
|
|
|
#define X86_FEATURE_GBPAGES (1*32+26) /* "pdpe1gb" GB pages */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
|
|
|
|
#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
|
|
|
|
#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
|
|
|
|
#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
|
|
|
|
|
|
|
|
/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
|
|
|
|
#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
|
|
|
|
#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
|
|
|
|
#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
|
|
|
|
|
|
|
|
/* Other features, Linux-defined mapping, word 3 */
|
|
|
|
/* This range is used for feature bits which conflict or are synthesized */
|
|
|
|
#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
|
|
|
|
#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
|
|
|
|
#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
|
|
|
|
#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
|
|
|
|
/* cpu types for specific tunings: */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_K8 (3*32+ 4) /* "" Opteron, Athlon64 */
|
|
|
|
#define X86_FEATURE_K7 (3*32+ 5) /* "" Athlon */
|
|
|
|
#define X86_FEATURE_P3 (3*32+ 6) /* "" P3 */
|
|
|
|
#define X86_FEATURE_P4 (3*32+ 7) /* "" P4 */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
|
|
|
|
#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
|
2008-08-18 18:39:32 -06:00
|
|
|
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
|
|
|
|
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_SYSCALL32 (3*32+14) /* "" syscall in ia32 userspace */
|
|
|
|
#define X86_FEATURE_SYSENTER32 (3*32+15) /* "" sysenter in ia32 userspace */
|
2008-08-27 22:20:07 -06:00
|
|
|
#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
|
|
|
|
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
|
|
|
|
#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */
|
2008-08-18 18:39:32 -06:00
|
|
|
#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
|
2013-06-09 04:07:30 -06:00
|
|
|
#define X86_FEATURE_ALWAYS (3*32+21) /* "" Always-present feature */
|
2008-10-07 14:33:12 -06:00
|
|
|
#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
|
2008-10-31 12:59:53 -06:00
|
|
|
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
|
2008-12-16 12:59:24 -07:00
|
|
|
#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
|
2009-02-06 17:52:05 -07:00
|
|
|
#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
|
2009-06-08 07:55:09 -06:00
|
|
|
#define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */
|
2009-09-03 01:40:21 -06:00
|
|
|
#define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */
|
2009-09-02 02:56:56 -06:00
|
|
|
#define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */
|
2012-09-06 15:58:52 -06:00
|
|
|
#define X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */
|
2013-03-11 21:56:45 -06:00
|
|
|
#define X86_FEATURE_NONSTOP_TSC_S3 (3*32+30) /* TSC doesn't stop in S3 state */
|
2008-01-30 05:30:07 -07:00
|
|
|
|
|
|
|
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
|
2008-08-27 19:53:07 -06:00
|
|
|
#define X86_FEATURE_PCLMULQDQ (4*32+ 1) /* PCLMULQDQ instruction */
|
|
|
|
#define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_MWAIT (4*32+ 3) /* "monitor" Monitor/Mwait support */
|
|
|
|
#define X86_FEATURE_DSCPL (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
|
|
|
|
#define X86_FEATURE_VMX (4*32+ 5) /* Hardware virtualization */
|
2008-08-27 23:05:45 -06:00
|
|
|
#define X86_FEATURE_SMX (4*32+ 6) /* Safer mode */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
|
|
|
|
#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental SSE-3 */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_CID (4*32+10) /* Context ID */
|
2008-08-27 19:53:07 -06:00
|
|
|
#define X86_FEATURE_FMA (4*32+12) /* Fused multiply-add */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
|
|
|
|
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
|
2008-08-27 19:53:07 -06:00
|
|
|
#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */
|
2011-08-19 13:42:23 -06:00
|
|
|
#define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */
|
|
|
|
#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */
|
2008-07-10 12:16:50 -06:00
|
|
|
#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */
|
2009-05-10 05:37:56 -06:00
|
|
|
#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */
|
|
|
|
#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
|
2011-09-22 02:53:58 -06:00
|
|
|
#define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */
|
2008-08-27 19:53:07 -06:00
|
|
|
#define X86_FEATURE_AES (4*32+25) /* AES instructions */
|
|
|
|
#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
|
|
|
|
#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */
|
|
|
|
#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
|
2010-07-07 11:15:12 -06:00
|
|
|
#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */
|
2011-05-24 17:29:26 -06:00
|
|
|
#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */
|
2008-11-01 19:34:37 -06:00
|
|
|
#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */
|
2008-01-30 05:30:07 -07:00
|
|
|
|
|
|
|
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_XSTORE (5*32+ 2) /* "rng" RNG present (xstore) */
|
|
|
|
#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* "rng_en" RNG enabled */
|
|
|
|
#define X86_FEATURE_XCRYPT (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
|
|
|
|
#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* "ace_en" on-CPU crypto enabled */
|
2008-01-30 05:30:07 -07:00
|
|
|
#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
|
|
|
|
#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_PHE (5*32+10) /* PadLock Hash Engine */
|
|
|
|
#define X86_FEATURE_PHE_EN (5*32+11) /* PHE enabled */
|
|
|
|
#define X86_FEATURE_PMM (5*32+12) /* PadLock Montgomery Multiplier */
|
|
|
|
#define X86_FEATURE_PMM_EN (5*32+13) /* PMM enabled */
|
2008-01-30 05:30:07 -07:00
|
|
|
|
|
|
|
/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
|
|
|
|
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
|
|
|
|
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */
|
|
|
|
#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */
|
|
|
|
#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */
|
|
|
|
#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */
|
|
|
|
#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */
|
|
|
|
#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
|
|
|
|
#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
|
|
|
|
#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
|
|
|
|
#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */
|
2010-09-06 07:14:17 -06:00
|
|
|
#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */
|
2008-08-27 18:56:44 -06:00
|
|
|
#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */
|
|
|
|
#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */
|
2010-09-06 07:14:18 -06:00
|
|
|
#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */
|
|
|
|
#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
|
2012-01-20 09:38:23 -07:00
|
|
|
#define X86_FEATURE_TCE (6*32+17) /* translation cache extension */
|
2009-12-16 07:43:55 -07:00
|
|
|
#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */
|
2010-09-06 07:14:18 -06:00
|
|
|
#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
|
|
|
|
#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
|
2011-02-02 09:36:12 -07:00
|
|
|
#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */
|
2013-02-06 10:26:29 -07:00
|
|
|
#define X86_FEATURE_PERFCTR_NB (6*32+24) /* NB performance counter extensions */
|
2013-04-19 15:34:28 -06:00
|
|
|
#define X86_FEATURE_PERFCTR_L2 (6*32+28) /* L2 performance counter extensions */
|
2008-01-30 05:30:07 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Auxiliary flags: Linux defined - For features scattered in various
|
2010-07-07 18:29:18 -06:00
|
|
|
* CPUID levels like 0x6, 0xA etc, word 7
|
2008-01-30 05:30:07 -07:00
|
|
|
*/
|
|
|
|
#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */
|
2009-04-06 19:51:29 -06:00
|
|
|
#define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */
|
2010-03-31 13:56:41 -06:00
|
|
|
#define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */
|
2010-06-03 21:22:28 -06:00
|
|
|
#define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
|
2010-07-19 19:53:51 -06:00
|
|
|
#define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */
|
2010-07-29 18:13:42 -06:00
|
|
|
#define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */
|
|
|
|
#define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */
|
2012-06-22 11:58:06 -06:00
|
|
|
#define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */
|
2012-01-25 16:09:11 -07:00
|
|
|
#define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */
|
2013-04-04 10:19:04 -06:00
|
|
|
#define X86_FEATURE_PROC_FEEDBACK (7*32+ 9) /* AMD ProcFeedbackInterface */
|
2008-01-30 05:30:07 -07:00
|
|
|
|
2010-07-07 18:29:18 -06:00
|
|
|
/* Virtualization flags: Linux defined, word 8 */
|
2008-09-10 04:53:34 -06:00
|
|
|
#define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */
|
|
|
|
#define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */
|
|
|
|
#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
|
|
|
|
#define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */
|
|
|
|
#define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */
|
2010-07-19 19:53:51 -06:00
|
|
|
#define X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */
|
|
|
|
#define X86_FEATURE_LBRV (8*32+ 6) /* AMD LBR Virtualization support */
|
|
|
|
#define X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */
|
|
|
|
#define X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */
|
2010-09-06 07:14:20 -06:00
|
|
|
#define X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */
|
|
|
|
#define X86_FEATURE_VMCBCLEAN (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */
|
|
|
|
#define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */
|
|
|
|
#define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */
|
|
|
|
#define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */
|
|
|
|
#define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */
|
|
|
|
|
2008-09-10 04:53:34 -06:00
|
|
|
|
2010-07-07 18:29:18 -06:00
|
|
|
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
|
2010-07-19 19:53:51 -06:00
|
|
|
#define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
|
2012-11-29 13:42:50 -07:00
|
|
|
#define X86_FEATURE_TSC_ADJUST (9*32+ 1) /* TSC adjustment MSR 0x3b */
|
2011-11-28 04:55:19 -07:00
|
|
|
#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */
|
2012-02-21 18:25:50 -07:00
|
|
|
#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */
|
2011-11-28 04:55:19 -07:00
|
|
|
#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */
|
2011-05-17 19:44:26 -06:00
|
|
|
#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */
|
2011-11-28 04:55:19 -07:00
|
|
|
#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */
|
2011-05-17 16:29:10 -06:00
|
|
|
#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
|
2012-02-21 18:25:50 -07:00
|
|
|
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */
|
|
|
|
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */
|
2013-12-06 17:20:57 -07:00
|
|
|
#define X86_FEATURE_MPX (9*32+14) /* Memory Protection Extension */
|
2014-02-20 14:24:50 -07:00
|
|
|
#define X86_FEATURE_AVX512F (9*32+16) /* AVX-512 Foundation */
|
2012-07-20 14:35:06 -06:00
|
|
|
#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */
|
|
|
|
#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */
|
2012-09-09 12:12:04 -06:00
|
|
|
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */
|
2014-02-26 12:06:49 -07:00
|
|
|
#define X86_FEATURE_CLFLUSHOPT (9*32+23) /* CLFLUSHOPT instruction */
|
2014-02-20 14:24:50 -07:00
|
|
|
#define X86_FEATURE_AVX512PF (9*32+26) /* AVX-512 Prefetch */
|
|
|
|
#define X86_FEATURE_AVX512ER (9*32+27) /* AVX-512 Exponential and Reciprocal */
|
|
|
|
#define X86_FEATURE_AVX512CD (9*32+28) /* AVX-512 Conflict Detection */
|
2010-07-07 18:29:18 -06:00
|
|
|
|
2013-03-20 08:07:23 -06:00
|
|
|
/*
|
|
|
|
* BUG word(s)
|
|
|
|
*/
|
|
|
|
#define X86_BUG(x) (NCAPINTS*32 + (x))
|
|
|
|
|
2013-03-20 08:07:24 -06:00
|
|
|
#define X86_BUG_F00F X86_BUG(0) /* Intel F00F */
|
2013-03-20 08:07:25 -06:00
|
|
|
#define X86_BUG_FDIV X86_BUG(1) /* FPU FDIV */
|
2013-03-20 08:07:26 -06:00
|
|
|
#define X86_BUG_COMA X86_BUG(2) /* Cyrix 6x86 coma */
|
2013-03-20 08:07:27 -06:00
|
|
|
#define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* AMD Erratum 383 */
|
2013-03-20 08:07:28 -06:00
|
|
|
#define X86_BUG_AMD_APIC_C1E X86_BUG(4) /* AMD Erratum 400 */
|
2013-03-20 08:07:24 -06:00
|
|
|
|
2008-02-04 08:48:00 -07:00
|
|
|
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
|
|
|
|
|
2010-05-11 18:47:07 -06:00
|
|
|
#include <asm/asm.h>
|
2008-02-04 08:48:00 -07:00
|
|
|
#include <linux/bitops.h>
|
|
|
|
|
|
|
|
extern const char * const x86_cap_flags[NCAPINTS*32];
|
|
|
|
extern const char * const x86_power_flags[32];
|
|
|
|
|
2008-02-26 00:34:21 -07:00
|
|
|
#define test_cpu_cap(c, bit) \
|
|
|
|
test_bit(bit, (unsigned long *)((c)->x86_capability))
|
|
|
|
|
2011-03-12 04:50:10 -07:00
|
|
|
#define REQUIRED_MASK_BIT_SET(bit) \
|
2008-01-30 05:30:07 -07:00
|
|
|
( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \
|
|
|
|
(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \
|
|
|
|
(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \
|
|
|
|
(((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \
|
|
|
|
(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \
|
|
|
|
(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \
|
|
|
|
(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
|
2010-07-07 18:29:18 -06:00
|
|
|
(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \
|
|
|
|
(((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \
|
2011-03-12 04:50:10 -07:00
|
|
|
(((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) )
|
|
|
|
|
|
|
|
#define cpu_has(c, bit) \
|
|
|
|
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
|
2008-02-26 00:34:21 -07:00
|
|
|
test_cpu_cap(c, bit))
|
|
|
|
|
2011-03-12 04:50:10 -07:00
|
|
|
#define this_cpu_has(bit) \
|
|
|
|
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \
|
|
|
|
x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability))
|
|
|
|
|
2008-01-30 05:30:07 -07:00
|
|
|
#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
|
|
|
|
|
2008-01-30 05:30:55 -07:00
|
|
|
#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
|
|
|
|
#define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
|
2008-01-30 05:33:20 -07:00
|
|
|
#define setup_clear_cpu_cap(bit) do { \
|
|
|
|
clear_cpu_cap(&boot_cpu_data, bit); \
|
2009-05-10 00:47:42 -06:00
|
|
|
set_bit(bit, (unsigned long *)cpu_caps_cleared); \
|
2008-01-30 05:33:20 -07:00
|
|
|
} while (0)
|
2008-01-30 05:33:20 -07:00
|
|
|
#define setup_force_cpu_cap(bit) do { \
|
|
|
|
set_cpu_cap(&boot_cpu_data, bit); \
|
2009-05-10 00:47:42 -06:00
|
|
|
set_bit(bit, (unsigned long *)cpu_caps_set); \
|
2008-01-30 05:33:20 -07:00
|
|
|
} while (0)
|
2008-01-30 05:30:55 -07:00
|
|
|
|
2008-01-30 05:30:07 -07:00
|
|
|
#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
|
|
|
|
#define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
|
|
|
|
#define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
|
|
|
|
#define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
|
|
|
|
#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
|
|
|
|
#define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
|
|
|
|
#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
|
|
|
|
#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
|
|
|
|
#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
|
|
|
|
#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
|
|
|
|
#define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
|
|
|
|
#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
|
|
|
|
#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
|
|
|
|
#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
|
|
|
|
#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
|
2011-08-04 12:19:25 -06:00
|
|
|
#define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3)
|
2009-01-17 22:28:34 -07:00
|
|
|
#define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
|
2011-08-04 12:19:25 -06:00
|
|
|
#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
|
2013-04-13 04:46:45 -06:00
|
|
|
#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
|
2008-01-30 05:30:07 -07:00
|
|
|
#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
|
|
|
|
#define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
|
|
|
|
#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
|
|
|
|
#define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
|
|
|
|
#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
|
|
|
|
#define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
|
|
|
|
#define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
|
|
|
|
#define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN)
|
|
|
|
#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
|
|
|
|
#define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN)
|
|
|
|
#define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2)
|
|
|
|
#define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN)
|
|
|
|
#define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE)
|
|
|
|
#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
|
|
|
|
#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
|
|
|
|
#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
|
|
|
|
#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
|
|
|
|
#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
|
|
|
|
#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
|
|
|
|
#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
|
2008-02-04 08:48:09 -07:00
|
|
|
#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
|
2008-03-07 14:05:27 -07:00
|
|
|
#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
|
2008-03-18 18:00:14 -06:00
|
|
|
#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
|
2008-08-27 19:53:07 -06:00
|
|
|
#define cpu_has_xmm4_1 boot_cpu_has(X86_FEATURE_XMM4_1)
|
2008-08-25 09:14:51 -06:00
|
|
|
#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2)
|
2008-07-10 12:16:50 -06:00
|
|
|
#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
|
2008-08-27 19:53:07 -06:00
|
|
|
#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
|
2012-09-06 16:05:18 -06:00
|
|
|
#define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT)
|
2011-08-04 12:19:25 -06:00
|
|
|
#define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE)
|
2008-11-01 19:34:37 -06:00
|
|
|
#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
|
2009-10-18 20:53:06 -06:00
|
|
|
#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ)
|
2011-02-02 09:36:12 -07:00
|
|
|
#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE)
|
2013-02-06 10:26:29 -07:00
|
|
|
#define cpu_has_perfctr_nb boot_cpu_has(X86_FEATURE_PERFCTR_NB)
|
2013-04-19 15:34:28 -06:00
|
|
|
#define cpu_has_perfctr_l2 boot_cpu_has(X86_FEATURE_PERFCTR_L2)
|
2011-06-01 11:25:47 -06:00
|
|
|
#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8)
|
|
|
|
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16)
|
2012-09-06 15:58:52 -06:00
|
|
|
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU)
|
2012-10-19 02:58:13 -06:00
|
|
|
#define cpu_has_topoext boot_cpu_has(X86_FEATURE_TOPOEXT)
|
2008-01-30 05:30:07 -07:00
|
|
|
|
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
|
|
|
|
#undef cpu_has_vme
|
|
|
|
#define cpu_has_vme 0
|
|
|
|
|
|
|
|
#undef cpu_has_pae
|
|
|
|
#define cpu_has_pae ___BUG___
|
|
|
|
|
|
|
|
#undef cpu_has_mp
|
|
|
|
#define cpu_has_mp 1
|
|
|
|
|
|
|
|
#undef cpu_has_k6_mtrr
|
|
|
|
#define cpu_has_k6_mtrr 0
|
|
|
|
|
|
|
|
#undef cpu_has_cyrix_arr
|
|
|
|
#define cpu_has_cyrix_arr 0
|
|
|
|
|
|
|
|
#undef cpu_has_centaur_mcr
|
|
|
|
#define cpu_has_centaur_mcr 0
|
|
|
|
|
|
|
|
#endif /* CONFIG_X86_64 */
|
|
|
|
|
2010-08-29 18:45:40 -06:00
|
|
|
#if __GNUC__ >= 4
|
2013-06-09 04:07:32 -06:00
|
|
|
extern void warn_pre_alternatives(void);
|
2013-06-09 04:07:33 -06:00
|
|
|
extern bool __static_cpu_has_safe(u16 bit);
|
2013-06-09 04:07:32 -06:00
|
|
|
|
2010-05-11 18:47:07 -06:00
|
|
|
/*
|
|
|
|
* Static testing of CPU features. Used the same as boot_cpu_has().
|
|
|
|
* These are only valid after alternatives have run, but will statically
|
|
|
|
* patch the target code for additional performance.
|
|
|
|
*/
|
2010-06-09 18:10:43 -06:00
|
|
|
static __always_inline __pure bool __static_cpu_has(u16 bit)
|
2010-05-11 18:47:07 -06:00
|
|
|
{
|
2013-06-28 10:41:41 -06:00
|
|
|
#ifdef CC_HAVE_ASM_GOTO
|
2013-06-09 04:07:32 -06:00
|
|
|
|
|
|
|
#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
|
2013-06-28 10:41:41 -06:00
|
|
|
|
2013-06-09 04:07:32 -06:00
|
|
|
/*
|
|
|
|
* Catch too early usage of this before alternatives
|
|
|
|
* have run.
|
|
|
|
*/
|
2013-10-10 02:16:30 -06:00
|
|
|
asm_volatile_goto("1: jmp %l[t_warn]\n"
|
2013-06-09 04:07:32 -06:00
|
|
|
"2:\n"
|
|
|
|
".section .altinstructions,\"a\"\n"
|
|
|
|
" .long 1b - .\n"
|
|
|
|
" .long 0\n" /* no replacement */
|
|
|
|
" .word %P0\n" /* 1: do replace */
|
|
|
|
" .byte 2b - 1b\n" /* source len */
|
|
|
|
" .byte 0\n" /* replacement len */
|
|
|
|
".previous\n"
|
|
|
|
/* skipping size check since replacement size = 0 */
|
|
|
|
: : "i" (X86_FEATURE_ALWAYS) : : t_warn);
|
2013-06-28 10:41:41 -06:00
|
|
|
|
2013-06-09 04:07:32 -06:00
|
|
|
#endif
|
|
|
|
|
2013-10-10 02:16:30 -06:00
|
|
|
asm_volatile_goto("1: jmp %l[t_no]\n"
|
2010-05-11 18:47:07 -06:00
|
|
|
"2:\n"
|
|
|
|
".section .altinstructions,\"a\"\n"
|
2011-07-13 07:24:10 -06:00
|
|
|
" .long 1b - .\n"
|
|
|
|
" .long 0\n" /* no replacement */
|
2010-06-09 18:10:43 -06:00
|
|
|
" .word %P0\n" /* feature bit */
|
2010-05-11 18:47:07 -06:00
|
|
|
" .byte 2b - 1b\n" /* source len */
|
|
|
|
" .byte 0\n" /* replacement len */
|
|
|
|
".previous\n"
|
2010-06-09 18:10:43 -06:00
|
|
|
/* skipping size check since replacement size = 0 */
|
2010-05-11 18:47:07 -06:00
|
|
|
: : "i" (bit) : : t_no);
|
|
|
|
return true;
|
|
|
|
t_no:
|
|
|
|
return false;
|
2013-06-09 04:07:32 -06:00
|
|
|
|
|
|
|
#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
|
|
|
|
t_warn:
|
|
|
|
warn_pre_alternatives();
|
|
|
|
return false;
|
|
|
|
#endif
|
2013-06-28 10:41:41 -06:00
|
|
|
|
|
|
|
#else /* CC_HAVE_ASM_GOTO */
|
|
|
|
|
2010-05-11 18:47:07 -06:00
|
|
|
u8 flag;
|
|
|
|
/* Open-coded due to __stringify() in ALTERNATIVE() */
|
|
|
|
asm volatile("1: movb $0,%0\n"
|
|
|
|
"2:\n"
|
|
|
|
".section .altinstructions,\"a\"\n"
|
2011-07-13 07:24:10 -06:00
|
|
|
" .long 1b - .\n"
|
|
|
|
" .long 3f - .\n"
|
2010-06-09 18:10:43 -06:00
|
|
|
" .word %P1\n" /* feature bit */
|
2010-05-11 18:47:07 -06:00
|
|
|
" .byte 2b - 1b\n" /* source len */
|
|
|
|
" .byte 4f - 3f\n" /* replacement len */
|
2010-06-09 18:10:43 -06:00
|
|
|
".previous\n"
|
|
|
|
".section .discard,\"aw\",@progbits\n"
|
|
|
|
" .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
|
2010-05-11 18:47:07 -06:00
|
|
|
".previous\n"
|
|
|
|
".section .altinstr_replacement,\"ax\"\n"
|
|
|
|
"3: movb $1,%0\n"
|
|
|
|
"4:\n"
|
|
|
|
".previous\n"
|
|
|
|
: "=qm" (flag) : "i" (bit));
|
|
|
|
return flag;
|
2013-06-28 10:41:41 -06:00
|
|
|
|
|
|
|
#endif /* CC_HAVE_ASM_GOTO */
|
2010-05-11 18:47:07 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define static_cpu_has(bit) \
|
|
|
|
( \
|
|
|
|
__builtin_constant_p(boot_cpu_has(bit)) ? \
|
|
|
|
boot_cpu_has(bit) : \
|
2010-06-09 18:10:43 -06:00
|
|
|
__builtin_constant_p(bit) ? \
|
2010-05-11 18:47:07 -06:00
|
|
|
__static_cpu_has(bit) : \
|
|
|
|
boot_cpu_has(bit) \
|
|
|
|
)
|
2013-06-09 04:07:33 -06:00
|
|
|
|
|
|
|
static __always_inline __pure bool _static_cpu_has_safe(u16 bit)
|
|
|
|
{
|
2013-06-28 10:41:41 -06:00
|
|
|
#ifdef CC_HAVE_ASM_GOTO
|
2013-06-09 04:07:33 -06:00
|
|
|
/*
|
|
|
|
* We need to spell the jumps to the compiler because, depending on the offset,
|
|
|
|
* the replacement jump can be bigger than the original jump, and this we cannot
|
|
|
|
* have. Thus, we force the jump to the widest, 4-byte, signed relative
|
|
|
|
* offset even though the last would often fit in less bytes.
|
|
|
|
*/
|
2013-10-10 02:16:30 -06:00
|
|
|
asm_volatile_goto("1: .byte 0xe9\n .long %l[t_dynamic] - 2f\n"
|
2013-06-09 04:07:33 -06:00
|
|
|
"2:\n"
|
|
|
|
".section .altinstructions,\"a\"\n"
|
|
|
|
" .long 1b - .\n" /* src offset */
|
|
|
|
" .long 3f - .\n" /* repl offset */
|
|
|
|
" .word %P1\n" /* always replace */
|
|
|
|
" .byte 2b - 1b\n" /* src len */
|
|
|
|
" .byte 4f - 3f\n" /* repl len */
|
|
|
|
".previous\n"
|
|
|
|
".section .altinstr_replacement,\"ax\"\n"
|
|
|
|
"3: .byte 0xe9\n .long %l[t_no] - 2b\n"
|
|
|
|
"4:\n"
|
|
|
|
".previous\n"
|
|
|
|
".section .altinstructions,\"a\"\n"
|
|
|
|
" .long 1b - .\n" /* src offset */
|
|
|
|
" .long 0\n" /* no replacement */
|
|
|
|
" .word %P0\n" /* feature bit */
|
|
|
|
" .byte 2b - 1b\n" /* src len */
|
|
|
|
" .byte 0\n" /* repl len */
|
|
|
|
".previous\n"
|
|
|
|
: : "i" (bit), "i" (X86_FEATURE_ALWAYS)
|
|
|
|
: : t_dynamic, t_no);
|
|
|
|
return true;
|
|
|
|
t_no:
|
|
|
|
return false;
|
|
|
|
t_dynamic:
|
|
|
|
return __static_cpu_has_safe(bit);
|
2013-06-28 10:41:41 -06:00
|
|
|
#else
|
2013-06-09 04:07:33 -06:00
|
|
|
u8 flag;
|
|
|
|
/* Open-coded due to __stringify() in ALTERNATIVE() */
|
|
|
|
asm volatile("1: movb $2,%0\n"
|
|
|
|
"2:\n"
|
|
|
|
".section .altinstructions,\"a\"\n"
|
|
|
|
" .long 1b - .\n" /* src offset */
|
|
|
|
" .long 3f - .\n" /* repl offset */
|
|
|
|
" .word %P2\n" /* always replace */
|
|
|
|
" .byte 2b - 1b\n" /* source len */
|
|
|
|
" .byte 4f - 3f\n" /* replacement len */
|
|
|
|
".previous\n"
|
|
|
|
".section .discard,\"aw\",@progbits\n"
|
|
|
|
" .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
|
|
|
|
".previous\n"
|
|
|
|
".section .altinstr_replacement,\"ax\"\n"
|
|
|
|
"3: movb $0,%0\n"
|
|
|
|
"4:\n"
|
|
|
|
".previous\n"
|
|
|
|
".section .altinstructions,\"a\"\n"
|
|
|
|
" .long 1b - .\n" /* src offset */
|
|
|
|
" .long 5f - .\n" /* repl offset */
|
|
|
|
" .word %P1\n" /* feature bit */
|
|
|
|
" .byte 4b - 3b\n" /* src len */
|
|
|
|
" .byte 6f - 5f\n" /* repl len */
|
|
|
|
".previous\n"
|
|
|
|
".section .discard,\"aw\",@progbits\n"
|
|
|
|
" .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */
|
|
|
|
".previous\n"
|
|
|
|
".section .altinstr_replacement,\"ax\"\n"
|
|
|
|
"5: movb $1,%0\n"
|
|
|
|
"6:\n"
|
|
|
|
".previous\n"
|
|
|
|
: "=qm" (flag)
|
|
|
|
: "i" (bit), "i" (X86_FEATURE_ALWAYS));
|
|
|
|
return (flag == 2 ? __static_cpu_has_safe(bit) : flag);
|
2013-06-28 10:41:41 -06:00
|
|
|
#endif /* CC_HAVE_ASM_GOTO */
|
2013-06-09 04:07:33 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#define static_cpu_has_safe(bit) \
|
|
|
|
( \
|
|
|
|
__builtin_constant_p(boot_cpu_has(bit)) ? \
|
|
|
|
boot_cpu_has(bit) : \
|
|
|
|
_static_cpu_has_safe(bit) \
|
|
|
|
)
|
2010-05-27 13:02:00 -06:00
|
|
|
#else
|
|
|
|
/*
|
|
|
|
* gcc 3.x is too stupid to do the static test; fall back to dynamic.
|
|
|
|
*/
|
2013-06-09 04:07:33 -06:00
|
|
|
#define static_cpu_has(bit) boot_cpu_has(bit)
|
|
|
|
#define static_cpu_has_safe(bit) boot_cpu_has(bit)
|
2010-05-27 13:02:00 -06:00
|
|
|
#endif
|
2010-05-11 18:47:07 -06:00
|
|
|
|
2013-03-20 08:07:23 -06:00
|
|
|
#define cpu_has_bug(c, bit) cpu_has(c, (bit))
|
|
|
|
#define set_cpu_bug(c, bit) set_cpu_cap(c, (bit))
|
|
|
|
#define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit));
|
|
|
|
|
|
|
|
#define static_cpu_has_bug(bit) static_cpu_has((bit))
|
|
|
|
#define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit))
|
|
|
|
|
2008-02-04 08:48:00 -07:00
|
|
|
#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
|
|
|
|
|
2008-10-22 23:26:29 -06:00
|
|
|
#endif /* _ASM_X86_CPUFEATURE_H */
|