2009-06-05 06:42:42 -06:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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2012-10-02 11:01:07 -06:00
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#include <drm/drmP.h>
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2009-06-05 06:42:42 -06:00
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#include "radeon.h"
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2012-10-02 11:01:07 -06:00
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#include <drm/radeon_drm.h>
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2012-08-09 08:34:17 -06:00
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#include "radeon_asic.h"
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2009-06-05 06:42:42 -06:00
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2010-01-31 22:38:10 -07:00
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#include <linux/vga_switcheroo.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2010-01-31 22:38:10 -07:00
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2012-07-17 12:02:34 -06:00
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/**
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* radeon_driver_unload_kms - Main unload function for KMS.
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*
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* @dev: drm dev pointer
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*
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* This is the main unload function for KMS (all asics).
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* It calls radeon_modeset_fini() to tear down the
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* displays, and radeon_device_fini() to tear down
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* the rest of the device (CP, writeback, etc.).
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* Returns 0 on success.
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*/
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2009-12-09 10:21:55 -07:00
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int radeon_driver_unload_kms(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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if (rdev == NULL)
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return 0;
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2012-07-31 15:14:35 -06:00
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radeon_acpi_fini(rdev);
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2009-12-09 10:21:55 -07:00
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radeon_modeset_fini(rdev);
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radeon_device_fini(rdev);
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kfree(rdev);
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dev->dev_private = NULL;
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return 0;
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}
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2009-06-05 06:42:42 -06:00
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2012-07-17 12:02:34 -06:00
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/**
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* radeon_driver_load_kms - Main load function for KMS.
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*
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* @dev: drm dev pointer
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* @flags: device flags
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*
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* This is the main load function for KMS (all asics).
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* It calls radeon_device_init() to set up the non-display
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* parts of the chip (asic init, CP, writeback, etc.), and
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* radeon_modeset_init() to set up the display parts
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* (crtcs, encoders, hotplug detect, etc.).
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* Returns 0 on success, error on failure.
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*/
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2009-06-05 06:42:42 -06:00
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
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{
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struct radeon_device *rdev;
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2010-07-06 09:40:24 -06:00
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int r, acpi_status;
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2009-06-05 06:42:42 -06:00
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rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
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if (rdev == NULL) {
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return -ENOMEM;
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}
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dev->dev_private = (void *)rdev;
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/* update BUS flag */
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2010-12-14 10:16:38 -07:00
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if (drm_pci_device_is_agp(dev)) {
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2009-06-05 06:42:42 -06:00
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flags |= RADEON_IS_AGP;
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2011-06-27 10:07:50 -06:00
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} else if (pci_is_pcie(dev->pdev)) {
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2009-06-05 06:42:42 -06:00
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flags |= RADEON_IS_PCIE;
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} else {
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flags |= RADEON_IS_PCI;
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}
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2009-09-10 13:46:48 -06:00
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/* radeon_device_init should report only fatal error
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* like memory allocation failure or iomapping failure,
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* or memory manager initialization failure, it must
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* properly initialize the GPU MC controller and permit
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* VRAM allocation
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*/
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2009-06-05 06:42:42 -06:00
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r = radeon_device_init(rdev, dev, dev->pdev, flags);
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if (r) {
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2009-12-09 10:21:55 -07:00
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dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
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goto out;
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2009-09-10 13:46:48 -06:00
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}
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2010-07-06 09:40:24 -06:00
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2009-09-10 13:46:48 -06:00
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/* Again modeset_init should fail only on fatal error
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* otherwise it should provide enough functionalities
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* for shadowfb to run
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*/
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r = radeon_modeset_init(rdev);
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2009-12-09 10:21:55 -07:00
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if (r)
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dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
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2012-07-30 13:20:35 -06:00
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/* Call ACPI methods: require modeset init
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* but failure is not fatal
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*/
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if (!r) {
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acpi_status = radeon_acpi_init(rdev);
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if (acpi_status)
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dev_dbg(&dev->pdev->dev,
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"Error during ACPI methods call\n");
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}
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2009-12-09 10:21:55 -07:00
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out:
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if (r)
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radeon_driver_unload_kms(dev);
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return r;
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2009-06-05 06:42:42 -06:00
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}
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2012-07-17 12:02:34 -06:00
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/**
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* radeon_set_filp_rights - Set filp right.
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*
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* @dev: drm dev pointer
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* @owner: drm file
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* @applier: drm file
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* @value: value
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*
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* Sets the filp rights for the device (all asics).
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*/
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2011-01-04 21:46:48 -07:00
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static void radeon_set_filp_rights(struct drm_device *dev,
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struct drm_file **owner,
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struct drm_file *applier,
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uint32_t *value)
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{
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mutex_lock(&dev->struct_mutex);
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if (*value == 1) {
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/* wants rights */
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if (!*owner)
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*owner = applier;
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} else if (*value == 0) {
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/* revokes rights */
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if (*owner == applier)
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*owner = NULL;
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}
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*value = *owner == applier ? 1 : 0;
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mutex_unlock(&dev->struct_mutex);
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}
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2009-06-05 06:42:42 -06:00
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/*
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2011-01-04 21:46:48 -07:00
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* Userspace get information ioctl
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2009-06-05 06:42:42 -06:00
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*/
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2012-07-17 12:02:34 -06:00
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/**
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* radeon_info_ioctl - answer a device specific request.
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*
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* @rdev: radeon device pointer
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* @data: request object
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* @filp: drm filp
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*
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* This function is used to pass device specific parameters to the userspace
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* drivers. Examples include: pci device id, pipeline parms, tiling params,
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* etc. (all asics).
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* Returns 0 on success, -EINVAL on failure.
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*/
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2009-06-05 06:42:42 -06:00
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int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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{
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struct radeon_device *rdev = dev->dev_private;
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2012-08-09 08:34:17 -06:00
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struct drm_radeon_info *info = data;
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2010-05-12 10:01:13 -06:00
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struct radeon_mode_info *minfo = &rdev->mode_info;
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2012-08-09 08:34:17 -06:00
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uint32_t value, *value_ptr;
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uint64_t value64, *value_ptr64;
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2010-05-12 10:01:13 -06:00
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struct drm_crtc *crtc;
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int i, found;
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2009-06-05 06:42:42 -06:00
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2012-08-09 08:34:17 -06:00
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/* TIMESTAMP is a 64-bit value, needs special handling. */
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if (info->request == RADEON_INFO_TIMESTAMP) {
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if (rdev->family >= CHIP_R600) {
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value_ptr64 = (uint64_t*)((unsigned long)info->value);
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if (rdev->family >= CHIP_TAHITI) {
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value64 = si_get_gpu_clock(rdev);
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} else {
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value64 = r600_get_gpu_clock(rdev);
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}
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if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) {
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DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
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return -EFAULT;
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}
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return 0;
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} else {
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DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
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return -EINVAL;
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}
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}
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2009-06-05 06:42:42 -06:00
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value_ptr = (uint32_t *)((unsigned long)info->value);
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2012-08-09 08:34:17 -06:00
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if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) {
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DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
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2010-08-01 17:43:52 -06:00
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return -EFAULT;
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2012-08-09 08:34:17 -06:00
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}
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2010-08-01 17:43:52 -06:00
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2009-06-05 06:42:42 -06:00
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switch (info->request) {
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case RADEON_INFO_DEVICE_ID:
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value = dev->pci_device;
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break;
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case RADEON_INFO_NUM_GB_PIPES:
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value = rdev->num_gb_pipes;
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break;
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2009-08-19 17:11:39 -06:00
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case RADEON_INFO_NUM_Z_PIPES:
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value = rdev->num_z_pipes;
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break;
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2009-09-16 07:24:21 -06:00
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case RADEON_INFO_ACCEL_WORKING:
|
2010-06-03 17:00:03 -06:00
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/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
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if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
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value = false;
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else
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value = rdev->accel_working;
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2009-09-16 07:24:21 -06:00
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break;
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2010-05-12 10:01:13 -06:00
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case RADEON_INFO_CRTC_FROM_ID:
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for (i = 0, found = 0; i < rdev->num_crtc; i++) {
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crtc = (struct drm_crtc *)minfo->crtcs[i];
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|
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if (crtc && crtc->base.id == value) {
|
2010-07-21 12:05:35 -06:00
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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|
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value = radeon_crtc->crtc_id;
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2010-05-12 10:01:13 -06:00
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found = 1;
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|
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break;
|
|
|
|
}
|
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|
|
}
|
|
|
|
if (!found) {
|
2010-08-01 18:42:55 -06:00
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|
DRM_DEBUG_KMS("unknown crtc id %d\n", value);
|
2010-05-12 10:01:13 -06:00
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return -EINVAL;
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|
|
|
}
|
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|
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break;
|
2010-06-03 17:00:03 -06:00
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|
|
case RADEON_INFO_ACCEL_WORKING2:
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value = rdev->accel_working;
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break;
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2010-06-04 11:10:12 -06:00
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|
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case RADEON_INFO_TILING_CONFIG:
|
2012-03-20 15:18:26 -06:00
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if (rdev->family >= CHIP_TAHITI)
|
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value = rdev->config.si.tile_config;
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else if (rdev->family >= CHIP_CAYMAN)
|
2011-03-02 18:07:29 -07:00
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value = rdev->config.cayman.tile_config;
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else if (rdev->family >= CHIP_CEDAR)
|
2010-06-04 11:10:12 -06:00
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value = rdev->config.evergreen.tile_config;
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|
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else if (rdev->family >= CHIP_RV770)
|
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value = rdev->config.rv770.tile_config;
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else if (rdev->family >= CHIP_R600)
|
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value = rdev->config.r600.tile_config;
|
|
|
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else {
|
2010-08-01 18:42:55 -06:00
|
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|
DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
|
2010-06-04 11:10:12 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2010-08-12 06:25:47 -06:00
|
|
|
break;
|
2010-07-12 19:11:11 -06:00
|
|
|
case RADEON_INFO_WANT_HYPERZ:
|
2010-08-06 19:36:34 -06:00
|
|
|
/* The "value" here is both an input and output parameter.
|
|
|
|
* If the input value is 1, filp requests hyper-z access.
|
|
|
|
* If the input value is 0, filp revokes its hyper-z access.
|
|
|
|
*
|
|
|
|
* When returning, the value is 1 if filp owns hyper-z access,
|
|
|
|
* 0 otherwise. */
|
|
|
|
if (value >= 2) {
|
|
|
|
DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-01-04 21:46:48 -07:00
|
|
|
radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
|
|
|
|
break;
|
|
|
|
case RADEON_INFO_WANT_CMASK:
|
|
|
|
/* The same logic as Hyper-Z. */
|
|
|
|
if (value >= 2) {
|
|
|
|
DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
|
|
|
|
return -EINVAL;
|
2010-07-12 19:11:11 -06:00
|
|
|
}
|
2011-01-04 21:46:48 -07:00
|
|
|
radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
|
2010-06-04 11:10:12 -06:00
|
|
|
break;
|
2011-01-24 15:14:26 -07:00
|
|
|
case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
|
|
|
|
/* return clock value in KHz */
|
|
|
|
value = rdev->clock.spll.reference_freq * 10;
|
|
|
|
break;
|
2011-02-28 21:32:27 -07:00
|
|
|
case RADEON_INFO_NUM_BACKENDS:
|
2012-03-20 15:18:26 -06:00
|
|
|
if (rdev->family >= CHIP_TAHITI)
|
|
|
|
value = rdev->config.si.max_backends_per_se *
|
|
|
|
rdev->config.si.max_shader_engines;
|
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2011-03-02 18:07:29 -07:00
|
|
|
value = rdev->config.cayman.max_backends_per_se *
|
|
|
|
rdev->config.cayman.max_shader_engines;
|
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
2011-02-28 21:32:27 -07:00
|
|
|
value = rdev->config.evergreen.max_backends;
|
|
|
|
else if (rdev->family >= CHIP_RV770)
|
|
|
|
value = rdev->config.rv770.max_backends;
|
|
|
|
else if (rdev->family >= CHIP_R600)
|
|
|
|
value = rdev->config.r600.max_backends;
|
|
|
|
else {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2011-04-26 11:27:43 -06:00
|
|
|
case RADEON_INFO_NUM_TILE_PIPES:
|
2012-03-20 15:18:26 -06:00
|
|
|
if (rdev->family >= CHIP_TAHITI)
|
|
|
|
value = rdev->config.si.max_tile_pipes;
|
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2011-04-26 11:27:43 -06:00
|
|
|
value = rdev->config.cayman.max_tile_pipes;
|
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
|
|
|
value = rdev->config.evergreen.max_tile_pipes;
|
|
|
|
else if (rdev->family >= CHIP_RV770)
|
|
|
|
value = rdev->config.rv770.max_tile_pipes;
|
|
|
|
else if (rdev->family >= CHIP_R600)
|
|
|
|
value = rdev->config.r600.max_tile_pipes;
|
|
|
|
else {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2011-05-03 17:28:02 -06:00
|
|
|
case RADEON_INFO_FUSION_GART_WORKING:
|
|
|
|
value = 1;
|
|
|
|
break;
|
2011-07-15 13:53:52 -06:00
|
|
|
case RADEON_INFO_BACKEND_MAP:
|
2012-03-20 15:18:26 -06:00
|
|
|
if (rdev->family >= CHIP_TAHITI)
|
|
|
|
value = rdev->config.si.backend_map;
|
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2011-07-15 13:53:52 -06:00
|
|
|
value = rdev->config.cayman.backend_map;
|
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
|
|
|
value = rdev->config.evergreen.backend_map;
|
|
|
|
else if (rdev->family >= CHIP_RV770)
|
|
|
|
value = rdev->config.rv770.backend_map;
|
|
|
|
else if (rdev->family >= CHIP_R600)
|
|
|
|
value = rdev->config.r600.backend_map;
|
|
|
|
else {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
case RADEON_INFO_VA_START:
|
|
|
|
/* this is where we report if vm is supported or not */
|
|
|
|
if (rdev->family < CHIP_CAYMAN)
|
|
|
|
return -EINVAL;
|
|
|
|
value = RADEON_VA_RESERVED_SIZE;
|
|
|
|
break;
|
|
|
|
case RADEON_INFO_IB_VM_MAX_SIZE:
|
|
|
|
/* this is where we report if vm is supported or not */
|
|
|
|
if (rdev->family < CHIP_CAYMAN)
|
|
|
|
return -EINVAL;
|
|
|
|
value = RADEON_IB_VM_MAX_SIZE;
|
|
|
|
break;
|
2012-03-20 15:17:55 -06:00
|
|
|
case RADEON_INFO_MAX_PIPES:
|
2012-03-20 15:18:26 -06:00
|
|
|
if (rdev->family >= CHIP_TAHITI)
|
2012-06-01 16:58:22 -06:00
|
|
|
value = rdev->config.si.max_cu_per_sh;
|
2012-03-20 15:18:26 -06:00
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2012-03-20 15:17:55 -06:00
|
|
|
value = rdev->config.cayman.max_pipes_per_simd;
|
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
|
|
|
value = rdev->config.evergreen.max_pipes;
|
|
|
|
else if (rdev->family >= CHIP_RV770)
|
|
|
|
value = rdev->config.rv770.max_pipes;
|
|
|
|
else if (rdev->family >= CHIP_R600)
|
|
|
|
value = rdev->config.r600.max_pipes;
|
|
|
|
else {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2012-12-04 10:55:37 -07:00
|
|
|
case RADEON_INFO_MAX_SE:
|
|
|
|
if (rdev->family >= CHIP_TAHITI)
|
|
|
|
value = rdev->config.si.max_shader_engines;
|
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
|
|
|
value = rdev->config.cayman.max_shader_engines;
|
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
|
|
|
value = rdev->config.evergreen.num_ses;
|
|
|
|
else
|
|
|
|
value = 1;
|
|
|
|
break;
|
|
|
|
case RADEON_INFO_MAX_SH_PER_SE:
|
|
|
|
if (rdev->family >= CHIP_TAHITI)
|
|
|
|
value = rdev->config.si.max_sh_per_se;
|
|
|
|
else
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
2009-06-05 06:42:42 -06:00
|
|
|
default:
|
2010-08-01 18:42:55 -06:00
|
|
|
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
|
2009-06-05 06:42:42 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
|
2012-08-09 08:34:17 -06:00
|
|
|
DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
|
2009-06-05 06:42:42 -06:00
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Outdated mess for old drm with Xorg being in charge (void function now).
|
|
|
|
*/
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_driver_firstopen_kms - drm callback for first open
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
*
|
|
|
|
* Nothing to be done for KMS (all asics).
|
|
|
|
* Returns 0 on success.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_driver_firstopen_kms(struct drm_device *dev)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_driver_firstopen_kms - drm callback for last close
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
*
|
|
|
|
* Switch vga switcheroo state after last close (all asics).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_driver_lastclose_kms(struct drm_device *dev)
|
|
|
|
{
|
2010-01-31 22:38:10 -07:00
|
|
|
vga_switcheroo_process_delayed_switch();
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_driver_open_kms - drm callback for open
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @file_priv: drm file
|
|
|
|
*
|
|
|
|
* On device open, init vm on cayman+ (all asics).
|
|
|
|
* Returns 0 on success, error on failure.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|
|
|
{
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
|
|
|
file_priv->driver_priv = NULL;
|
|
|
|
|
|
|
|
/* new gpu have virtual address space support */
|
|
|
|
if (rdev->family >= CHIP_CAYMAN) {
|
|
|
|
struct radeon_fpriv *fpriv;
|
2012-10-09 05:31:18 -06:00
|
|
|
struct radeon_bo_va *bo_va;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
int r;
|
|
|
|
|
|
|
|
fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
|
|
|
|
if (unlikely(!fpriv)) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2012-10-09 05:31:18 -06:00
|
|
|
radeon_vm_init(rdev, &fpriv->vm);
|
|
|
|
|
|
|
|
/* map the ib pool buffer read only into
|
|
|
|
* virtual address space */
|
|
|
|
bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
|
|
|
|
rdev->ring_tmp_bo.bo);
|
|
|
|
r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
|
|
|
|
RADEON_VM_PAGE_READABLE |
|
|
|
|
RADEON_VM_PAGE_SNOOPED);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
if (r) {
|
|
|
|
radeon_vm_fini(rdev, &fpriv->vm);
|
|
|
|
kfree(fpriv);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
file_priv->driver_priv = fpriv;
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_driver_postclose_kms - drm callback for post close
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @file_priv: drm file
|
|
|
|
*
|
|
|
|
* On device post close, tear down vm on cayman+ (all asics).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_driver_postclose_kms(struct drm_device *dev,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
|
|
|
/* new gpu have virtual address space support */
|
|
|
|
if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
|
|
|
|
struct radeon_fpriv *fpriv = file_priv->driver_priv;
|
2012-10-09 05:31:18 -06:00
|
|
|
struct radeon_bo_va *bo_va;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
|
|
|
if (!r) {
|
|
|
|
bo_va = radeon_vm_bo_find(&fpriv->vm,
|
|
|
|
rdev->ring_tmp_bo.bo);
|
|
|
|
if (bo_va)
|
|
|
|
radeon_vm_bo_rmv(rdev, bo_va);
|
|
|
|
radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
|
|
|
|
}
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
|
|
|
|
radeon_vm_fini(rdev, &fpriv->vm);
|
|
|
|
kfree(fpriv);
|
|
|
|
file_priv->driver_priv = NULL;
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_driver_preclose_kms - drm callback for pre close
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @file_priv: drm file
|
|
|
|
*
|
|
|
|
* On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
|
|
|
|
* (all asics).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_driver_preclose_kms(struct drm_device *dev,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
2010-07-12 19:11:11 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
if (rdev->hyperz_filp == file_priv)
|
|
|
|
rdev->hyperz_filp = NULL;
|
2011-01-27 14:46:15 -07:00
|
|
|
if (rdev->cmask_filp == file_priv)
|
|
|
|
rdev->cmask_filp = NULL;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* VBlank related functions.
|
|
|
|
*/
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_get_vblank_counter_kms - get frame count
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @crtc: crtc to get the frame count from
|
|
|
|
*
|
|
|
|
* Gets the frame count on the requested crtc (all asics).
|
|
|
|
* Returns frame count on success, -EINVAL on failure.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
|
|
|
|
{
|
2009-08-13 03:10:51 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
2010-04-22 21:21:58 -06:00
|
|
|
if (crtc < 0 || crtc >= rdev->num_crtc) {
|
2009-08-13 03:10:51 -06:00
|
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return radeon_get_vblank_counter(rdev, crtc);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_enable_vblank_kms - enable vblank interrupt
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @crtc: crtc to enable vblank interrupt for
|
|
|
|
*
|
|
|
|
* Enable the interrupt on the requested crtc (all asics).
|
|
|
|
* Returns 0 on success, -EINVAL on failure.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
|
|
|
|
{
|
2009-08-13 03:10:51 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2012-05-16 17:33:30 -06:00
|
|
|
unsigned long irqflags;
|
|
|
|
int r;
|
2009-08-13 03:10:51 -06:00
|
|
|
|
2010-04-22 21:21:58 -06:00
|
|
|
if (crtc < 0 || crtc >= rdev->num_crtc) {
|
2009-08-13 03:10:51 -06:00
|
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2012-05-16 17:33:30 -06:00
|
|
|
spin_lock_irqsave(&rdev->irq.lock, irqflags);
|
2009-08-13 03:10:51 -06:00
|
|
|
rdev->irq.crtc_vblank_int[crtc] = true;
|
2012-05-16 17:33:30 -06:00
|
|
|
r = radeon_irq_set(rdev);
|
|
|
|
spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
|
|
|
|
return r;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_disable_vblank_kms - disable vblank interrupt
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @crtc: crtc to disable vblank interrupt for
|
|
|
|
*
|
|
|
|
* Disable the interrupt on the requested crtc (all asics).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
|
|
|
|
{
|
2009-08-13 03:10:51 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2012-05-16 17:33:30 -06:00
|
|
|
unsigned long irqflags;
|
2009-08-13 03:10:51 -06:00
|
|
|
|
2010-04-22 21:21:58 -06:00
|
|
|
if (crtc < 0 || crtc >= rdev->num_crtc) {
|
2009-08-13 03:10:51 -06:00
|
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-05-16 17:33:30 -06:00
|
|
|
spin_lock_irqsave(&rdev->irq.lock, irqflags);
|
2009-08-13 03:10:51 -06:00
|
|
|
rdev->irq.crtc_vblank_int[crtc] = false;
|
|
|
|
radeon_irq_set(rdev);
|
2012-05-16 17:33:30 -06:00
|
|
|
spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_get_vblank_timestamp_kms - get vblank timestamp
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @crtc: crtc to get the timestamp for
|
|
|
|
* @max_error: max error
|
|
|
|
* @vblank_time: time value
|
|
|
|
* @flags: flags passed to the driver
|
|
|
|
*
|
|
|
|
* Gets the timestamp on the requested crtc based on the
|
|
|
|
* scanout position. (all asics).
|
|
|
|
* Returns postive status flags on success, negative error on failure.
|
|
|
|
*/
|
2010-10-22 20:42:17 -06:00
|
|
|
int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
|
|
|
|
int *max_error,
|
|
|
|
struct timeval *vblank_time,
|
|
|
|
unsigned flags)
|
|
|
|
{
|
|
|
|
struct drm_crtc *drmcrtc;
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
|
|
|
if (crtc < 0 || crtc >= dev->num_crtcs) {
|
|
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Get associated drm_crtc: */
|
|
|
|
drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
|
|
|
|
|
|
|
|
/* Helper routine in DRM core does all the work: */
|
|
|
|
return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
|
|
|
|
vblank_time, flags,
|
|
|
|
drmcrtc);
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* IOCTL.
|
|
|
|
*/
|
|
|
|
int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
|
|
|
/* Not valid in KMS. */
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define KMS_INVALID_IOCTL(name) \
|
|
|
|
int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
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{ \
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DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
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return -EINVAL; \
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}
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/*
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* All these ioctls are invalid in kms world.
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*/
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KMS_INVALID_IOCTL(radeon_cp_init_kms)
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KMS_INVALID_IOCTL(radeon_cp_start_kms)
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KMS_INVALID_IOCTL(radeon_cp_stop_kms)
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KMS_INVALID_IOCTL(radeon_cp_reset_kms)
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KMS_INVALID_IOCTL(radeon_cp_idle_kms)
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KMS_INVALID_IOCTL(radeon_cp_resume_kms)
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KMS_INVALID_IOCTL(radeon_engine_reset_kms)
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KMS_INVALID_IOCTL(radeon_fullscreen_kms)
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KMS_INVALID_IOCTL(radeon_cp_swap_kms)
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KMS_INVALID_IOCTL(radeon_cp_clear_kms)
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KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
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KMS_INVALID_IOCTL(radeon_cp_indices_kms)
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KMS_INVALID_IOCTL(radeon_cp_texture_kms)
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KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
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KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
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KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
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KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
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KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
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KMS_INVALID_IOCTL(radeon_cp_flip_kms)
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KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
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KMS_INVALID_IOCTL(radeon_mem_free_kms)
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KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
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KMS_INVALID_IOCTL(radeon_irq_emit_kms)
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KMS_INVALID_IOCTL(radeon_irq_wait_kms)
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KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
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KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
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KMS_INVALID_IOCTL(radeon_surface_free_kms)
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struct drm_ioctl_desc radeon_ioctls_kms[] = {
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2010-08-14 04:20:34 -06:00
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DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
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DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
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DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
|
2009-06-05 06:42:42 -06:00
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/* KMS */
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2010-08-14 04:20:34 -06:00
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DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
|
2009-06-05 06:42:42 -06:00
|
|
|
};
|
|
|
|
int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);
|