2005-09-26 21:51:59 -06:00
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#ifndef _ASM_POWERPC_MPIC_H
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#define _ASM_POWERPC_MPIC_H
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2005-12-16 14:43:46 -07:00
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#ifdef __KERNEL__
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2005-09-26 21:51:59 -06:00
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2005-09-26 00:04:21 -06:00
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#include <linux/irq.h>
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2007-05-02 00:33:41 -06:00
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#include <linux/sysdev.h>
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2006-11-10 23:24:55 -07:00
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#include <asm/dcr.h>
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2005-09-26 00:04:21 -06:00
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/*
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* Global registers
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*/
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#define MPIC_GREG_BASE 0x01000
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#define MPIC_GREG_FEATURE_0 0x00000
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#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
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#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
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#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
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#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
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#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
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#define MPIC_GREG_FEATURE_1 0x00010
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#define MPIC_GREG_GLOBAL_CONF_0 0x00020
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#define MPIC_GREG_GCONF_RESET 0x80000000
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#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
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#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
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#define MPIC_GREG_GLOBAL_CONF_1 0x00030
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#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
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#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
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#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
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(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
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2005-09-26 00:04:21 -06:00
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#define MPIC_GREG_VENDOR_0 0x00040
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#define MPIC_GREG_VENDOR_1 0x00050
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#define MPIC_GREG_VENDOR_2 0x00060
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#define MPIC_GREG_VENDOR_3 0x00070
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#define MPIC_GREG_VENDOR_ID 0x00080
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#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
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#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
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#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
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#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
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#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
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#define MPIC_GREG_PROCESSOR_INIT 0x00090
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#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
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#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
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#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
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#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
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#define MPIC_GREG_IPI_STRIDE 0x10
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#define MPIC_GREG_SPURIOUS 0x000e0
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#define MPIC_GREG_TIMER_FREQ 0x000f0
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/*
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*
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* Timer registers
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*/
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#define MPIC_TIMER_BASE 0x01100
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#define MPIC_TIMER_STRIDE 0x40
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#define MPIC_TIMER_CURRENT_CNT 0x00000
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#define MPIC_TIMER_BASE_CNT 0x00010
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#define MPIC_TIMER_VECTOR_PRI 0x00020
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#define MPIC_TIMER_DESTINATION 0x00030
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/*
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* Per-Processor registers
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*/
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#define MPIC_CPU_THISBASE 0x00000
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#define MPIC_CPU_BASE 0x20000
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#define MPIC_CPU_STRIDE 0x01000
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#define MPIC_CPU_IPI_DISPATCH_0 0x00040
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#define MPIC_CPU_IPI_DISPATCH_1 0x00050
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#define MPIC_CPU_IPI_DISPATCH_2 0x00060
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#define MPIC_CPU_IPI_DISPATCH_3 0x00070
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#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
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#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
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#define MPIC_CPU_TASKPRI_MASK 0x0000000f
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#define MPIC_CPU_WHOAMI 0x00090
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#define MPIC_CPU_WHOAMI_MASK 0x0000001f
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#define MPIC_CPU_INTACK 0x000a0
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#define MPIC_CPU_EOI 0x000b0
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/*
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* Per-source registers
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*/
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#define MPIC_IRQ_BASE 0x10000
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#define MPIC_IRQ_STRIDE 0x00020
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#define MPIC_IRQ_VECTOR_PRI 0x00000
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#define MPIC_VECPRI_MASK 0x80000000
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#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
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#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
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#define MPIC_VECPRI_PRIORITY_SHIFT 16
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#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
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#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
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#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
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#define MPIC_VECPRI_POLARITY_MASK 0x00800000
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#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
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#define MPIC_VECPRI_SENSE_EDGE 0x00000000
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#define MPIC_VECPRI_SENSE_MASK 0x00400000
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#define MPIC_IRQ_DESTINATION 0x00010
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#define MPIC_MAX_IRQ_SOURCES 2048
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#define MPIC_MAX_CPUS 32
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#define MPIC_MAX_ISU 32
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2006-08-24 22:16:30 -06:00
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/*
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* Tsi108 implementation of MPIC has many differences from the original one
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*/
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/*
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* Global registers
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*/
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#define TSI108_GREG_BASE 0x00000
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#define TSI108_GREG_FEATURE_0 0x00000
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#define TSI108_GREG_GLOBAL_CONF_0 0x00004
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#define TSI108_GREG_VENDOR_ID 0x0000c
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#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
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#define TSI108_GREG_IPI_STRIDE 0x0c
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#define TSI108_GREG_SPURIOUS 0x00010
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#define TSI108_GREG_TIMER_FREQ 0x00014
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/*
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* Timer registers
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*/
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#define TSI108_TIMER_BASE 0x0030
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#define TSI108_TIMER_STRIDE 0x10
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#define TSI108_TIMER_CURRENT_CNT 0x00000
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#define TSI108_TIMER_BASE_CNT 0x00004
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#define TSI108_TIMER_VECTOR_PRI 0x00008
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#define TSI108_TIMER_DESTINATION 0x0000c
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/*
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* Per-Processor registers
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*/
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#define TSI108_CPU_BASE 0x00300
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#define TSI108_CPU_STRIDE 0x00040
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#define TSI108_CPU_IPI_DISPATCH_0 0x00200
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#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
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#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
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#define TSI108_CPU_WHOAMI 0xffffffff
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#define TSI108_CPU_INTACK 0x00004
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#define TSI108_CPU_EOI 0x00008
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/*
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* Per-source registers
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*/
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#define TSI108_IRQ_BASE 0x00100
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#define TSI108_IRQ_STRIDE 0x00008
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#define TSI108_IRQ_VECTOR_PRI 0x00000
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#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
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#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
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#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
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#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
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#define TSI108_VECPRI_SENSE_EDGE 0x00000000
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#define TSI108_VECPRI_POLARITY_MASK 0x01000000
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#define TSI108_VECPRI_SENSE_MASK 0x02000000
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#define TSI108_IRQ_DESTINATION 0x00004
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/* weird mpic register indices and mask bits in the HW info array */
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enum {
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MPIC_IDX_GREG_BASE = 0,
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MPIC_IDX_GREG_FEATURE_0,
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MPIC_IDX_GREG_GLOBAL_CONF_0,
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MPIC_IDX_GREG_VENDOR_ID,
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MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
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MPIC_IDX_GREG_IPI_STRIDE,
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MPIC_IDX_GREG_SPURIOUS,
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MPIC_IDX_GREG_TIMER_FREQ,
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MPIC_IDX_TIMER_BASE,
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MPIC_IDX_TIMER_STRIDE,
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MPIC_IDX_TIMER_CURRENT_CNT,
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MPIC_IDX_TIMER_BASE_CNT,
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MPIC_IDX_TIMER_VECTOR_PRI,
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MPIC_IDX_TIMER_DESTINATION,
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MPIC_IDX_CPU_BASE,
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MPIC_IDX_CPU_STRIDE,
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MPIC_IDX_CPU_IPI_DISPATCH_0,
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MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
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MPIC_IDX_CPU_CURRENT_TASK_PRI,
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MPIC_IDX_CPU_WHOAMI,
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MPIC_IDX_CPU_INTACK,
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MPIC_IDX_CPU_EOI,
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MPIC_IDX_IRQ_BASE,
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MPIC_IDX_IRQ_STRIDE,
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MPIC_IDX_IRQ_VECTOR_PRI,
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MPIC_IDX_VECPRI_VECTOR_MASK,
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MPIC_IDX_VECPRI_POLARITY_POSITIVE,
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MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
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MPIC_IDX_VECPRI_SENSE_LEVEL,
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MPIC_IDX_VECPRI_SENSE_EDGE,
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MPIC_IDX_VECPRI_POLARITY_MASK,
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MPIC_IDX_VECPRI_SENSE_MASK,
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MPIC_IDX_IRQ_DESTINATION,
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MPIC_IDX_END
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};
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2007-04-23 02:47:08 -06:00
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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/* Fixup table entry */
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struct mpic_irq_fixup
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{
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u8 __iomem *base;
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u8 __iomem *applebase;
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u32 data;
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unsigned int index;
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};
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#endif /* CONFIG_MPIC_U3_HT_IRQS */
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2005-09-26 00:04:21 -06:00
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2006-11-10 23:24:55 -07:00
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enum mpic_reg_type {
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mpic_access_mmio_le,
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mpic_access_mmio_be,
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#ifdef CONFIG_PPC_DCR
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mpic_access_dcr
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#endif
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};
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struct mpic_reg_bank {
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u32 __iomem *base;
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#ifdef CONFIG_PPC_DCR
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dcr_host_t dhost;
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unsigned int dbase;
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unsigned int doff;
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#endif /* CONFIG_PPC_DCR */
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};
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2007-05-02 00:33:41 -06:00
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struct mpic_irq_save {
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u32 vecprio,
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dest;
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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u32 fixup_data;
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#endif
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};
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2005-09-26 00:04:21 -06:00
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/* The instance data of a given MPIC */
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struct mpic
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{
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2006-07-03 05:36:01 -06:00
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/* The remapper for this MPIC */
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struct irq_host *irqhost;
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2005-09-26 00:04:21 -06:00
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/* The "linux" controller struct */
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2006-07-03 03:32:51 -06:00
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struct irq_chip hc_irq;
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2007-04-23 02:47:08 -06:00
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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2006-07-03 03:32:51 -06:00
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struct irq_chip hc_ht_irq;
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#endif
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2005-09-26 00:04:21 -06:00
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#ifdef CONFIG_SMP
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2006-07-03 03:32:51 -06:00
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struct irq_chip hc_ipi;
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2005-09-26 00:04:21 -06:00
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#endif
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const char *name;
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/* Flags */
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unsigned int flags;
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/* How many irq sources in a given ISU */
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unsigned int isu_size;
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unsigned int isu_shift;
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unsigned int isu_mask;
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unsigned int irq_count;
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/* Number of sources */
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unsigned int num_sources;
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/* Number of CPUs */
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unsigned int num_cpus;
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2006-07-03 05:36:01 -06:00
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/* default senses array */
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2005-09-26 00:04:21 -06:00
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unsigned char *senses;
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unsigned int senses_count;
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2007-01-28 22:33:18 -07:00
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/* vector numbers used for internal sources (ipi/timers) */
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unsigned int ipi_vecs[4];
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unsigned int timer_vecs[4];
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/* Spurious vector to program into unused sources */
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unsigned int spurious_vec;
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2007-04-23 02:47:08 -06:00
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#ifdef CONFIG_MPIC_U3_HT_IRQS
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2005-09-26 00:04:21 -06:00
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/* The fixup table */
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struct mpic_irq_fixup *fixups;
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spinlock_t fixup_lock;
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#endif
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2006-11-10 23:24:55 -07:00
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/* Register access method */
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enum mpic_reg_type reg_type;
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2005-09-26 00:04:21 -06:00
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/* The various ioremap'ed bases */
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2006-11-10 23:24:55 -07:00
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struct mpic_reg_bank gregs;
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struct mpic_reg_bank tmregs;
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struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
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struct mpic_reg_bank isus[MPIC_MAX_ISU];
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#ifdef CONFIG_PPC_DCR
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unsigned int dcr_base;
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#endif
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2005-09-26 00:04:21 -06:00
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2007-07-20 17:55:21 -06:00
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/* Protected sources */
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unsigned long *protected;
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2006-08-24 22:16:30 -06:00
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#ifdef CONFIG_MPIC_WEIRD
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/* Pointer to HW info array */
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u32 *hw_set;
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#endif
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2007-05-07 20:58:36 -06:00
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#ifdef CONFIG_PCI_MSI
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spinlock_t bitmap_lock;
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unsigned long *hwirq_bitmap;
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#endif
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2005-09-26 00:04:21 -06:00
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/* link */
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struct mpic *next;
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2007-05-02 00:33:41 -06:00
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struct sys_device sysdev;
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#ifdef CONFIG_PM
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struct mpic_irq_save *save_data;
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#endif
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2005-09-26 00:04:21 -06:00
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};
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2006-08-24 22:16:30 -06:00
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/*
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* MPIC flags (passed to mpic_alloc)
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*
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* The top 4 bits contain an MPIC bhw id that is used to index the
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* register offsets and some masks when CONFIG_MPIC_WEIRD is set.
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* Note setting any ID (leaving those bits to 0) means standard MPIC
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*/
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2005-09-26 00:04:21 -06:00
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/* This is the primary controller, only that one has IPIs and
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* has afinity control. A non-primary MPIC always uses CPU0
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* registers only
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*/
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#define MPIC_PRIMARY 0x00000001
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2006-08-24 22:16:30 -06:00
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2005-09-26 00:04:21 -06:00
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/* Set this for a big-endian MPIC */
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#define MPIC_BIG_ENDIAN 0x00000002
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/* Broken U3 MPIC */
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2007-04-23 02:47:08 -06:00
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#define MPIC_U3_HT_IRQS 0x00000004
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2005-09-26 00:04:21 -06:00
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/* Broken IPI registers (autodetected) */
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#define MPIC_BROKEN_IPI 0x00000008
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/* MPIC wants a reset */
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#define MPIC_WANTS_RESET 0x00000010
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2006-08-24 22:16:30 -06:00
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/* Spurious vector requires EOI */
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#define MPIC_SPV_EOI 0x00000020
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/* No passthrough disable */
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#define MPIC_NO_PTHROU_DIS 0x00000040
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2006-11-10 23:24:55 -07:00
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/* DCR based MPIC */
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#define MPIC_USES_DCR 0x00000080
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2007-01-28 22:33:18 -07:00
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/* MPIC has 11-bit vector fields (or larger) */
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#define MPIC_LARGE_VECTORS 0x00000100
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2006-08-24 22:16:30 -06:00
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/* MPIC HW modification ID */
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#define MPIC_REGSET_MASK 0xf0000000
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#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
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#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
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#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
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#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
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2005-09-26 00:04:21 -06:00
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/* Allocate the controller structure and setup the linux irq descs
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* for the range if interrupts passed in. No HW initialization is
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* actually performed.
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*
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* @phys_addr: physial base address of the MPIC
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* @flags: flags, see constants above
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* @isu_size: number of interrupts in an ISU. Use 0 to use a
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* standard ISU-less setup (aka powermac)
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* @irq_offset: first irq number to assign to this mpic
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* @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
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* to match the number of sources
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* @ipi_offset: first irq number to assign to this mpic IPI sources,
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* used only on primary mpic
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* @senses: array of sense values
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* @senses_num: number of entries in the array
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*
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* Note about the sense array. If none is passed, all interrupts are
|
2007-04-23 02:47:08 -06:00
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* setup to be level negative unless MPIC_U3_HT_IRQS is set in which
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2005-09-26 00:04:21 -06:00
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* case they are edge positive (and the array is ignored anyway).
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* The values in the array start at the first source of the MPIC,
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* that is senses[0] correspond to linux irq "irq_offset".
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*/
|
2006-07-03 05:36:01 -06:00
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extern struct mpic *mpic_alloc(struct device_node *node,
|
2006-11-10 23:24:56 -07:00
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phys_addr_t phys_addr,
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2005-09-26 00:04:21 -06:00
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unsigned int flags,
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unsigned int isu_size,
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unsigned int irq_count,
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const char *name);
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/* Assign ISUs, to call before mpic_init()
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*
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* @mpic: controller structure as returned by mpic_alloc()
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* @isu_num: ISU number
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* @phys_addr: physical address of the ISU
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*/
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extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
|
2006-11-10 23:24:56 -07:00
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phys_addr_t phys_addr);
|
2005-09-26 00:04:21 -06:00
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2006-07-03 05:36:01 -06:00
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/* Set default sense codes
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*
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* @mpic: controller
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* @senses: array of sense codes
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* @count: size of above array
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*
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|
* Optionally provide an array (indexed on hardware interrupt numbers
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* for this MPIC) of default sense codes for the chip. Those are linux
|
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|
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* sense codes IRQ_TYPE_*
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|
*
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|
* The driver gets ownership of the pointer, don't dispose of it or
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|
* anything like that. __init only.
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*/
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extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
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|
2005-09-26 00:04:21 -06:00
|
|
|
/* Initialize the controller. After this has been called, none of the above
|
|
|
|
* should be called again for this mpic
|
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|
|
*/
|
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|
|
extern void mpic_init(struct mpic *mpic);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* All of the following functions must only be used after the
|
|
|
|
* ISUs have been assigned and the controller fully initialized
|
|
|
|
* with mpic_init()
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|
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|
*/
|
|
|
|
|
|
|
|
|
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|
|
/* Change/Read the priority of an interrupt. Default is 8 for irqs and
|
|
|
|
* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
|
|
|
|
* IPI number is then the offset'ed (linux irq number mapped to the IPI)
|
|
|
|
*/
|
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|
|
extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
|
|
|
|
extern unsigned int mpic_irq_get_priority(unsigned int irq);
|
|
|
|
|
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|
|
/* Setup a non-boot CPU */
|
|
|
|
extern void mpic_setup_this_cpu(void);
|
|
|
|
|
|
|
|
/* Clean up for kexec (or cpu offline or ...) */
|
|
|
|
extern void mpic_teardown_this_cpu(int secondary);
|
|
|
|
|
|
|
|
/* Get the current cpu priority for this cpu (0..15) */
|
|
|
|
extern int mpic_cpu_get_priority(void);
|
|
|
|
|
|
|
|
/* Set the current cpu priority for this cpu */
|
|
|
|
extern void mpic_cpu_set_priority(int prio);
|
|
|
|
|
|
|
|
/* Request IPIs on primary mpic */
|
|
|
|
extern void mpic_request_ipis(void);
|
|
|
|
|
|
|
|
/* Send an IPI (non offseted number 0..3) */
|
|
|
|
extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
|
|
|
|
|
2005-10-20 01:09:51 -06:00
|
|
|
/* Send a message (IPI) to a given target (cpu number or MSG_*) */
|
|
|
|
void smp_mpic_message_pass(int target, int msg);
|
|
|
|
|
2005-09-26 00:04:21 -06:00
|
|
|
/* Fetch interrupt from a given mpic */
|
2006-10-07 06:08:26 -06:00
|
|
|
extern unsigned int mpic_get_one_irq(struct mpic *mpic);
|
2005-09-26 00:04:21 -06:00
|
|
|
/* This one gets to the primary mpic */
|
2006-10-07 06:08:26 -06:00
|
|
|
extern unsigned int mpic_get_irq(void);
|
2005-09-26 00:04:21 -06:00
|
|
|
|
2006-06-20 15:15:36 -06:00
|
|
|
/* Set the EPIC clock ratio */
|
|
|
|
void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
|
|
|
|
|
|
|
|
/* Enable/Disable EPIC serial interrupt mode */
|
|
|
|
void mpic_set_serial_int(struct mpic *mpic, int enable);
|
|
|
|
|
2005-12-16 14:43:46 -07:00
|
|
|
#endif /* __KERNEL__ */
|
2005-09-26 21:51:59 -06:00
|
|
|
#endif /* _ASM_POWERPC_MPIC_H */
|