2012-11-14 12:17:04 -07:00
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/*
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* Copyright 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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2014-12-16 14:59:54 -07:00
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#include "skeleton.dtsi"
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2012-11-14 12:17:04 -07:00
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2015-01-11 21:34:06 -07:00
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#include <dt-bindings/thermal/thermal.h>
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2014-12-16 14:59:56 -07:00
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#include <dt-bindings/dma/sun4i-a10.h>
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2014-12-16 14:59:57 -07:00
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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2012-11-14 12:17:04 -07:00
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/ {
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2013-03-13 13:07:37 -06:00
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interrupt-parent = <&intc>;
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2015-01-19 06:05:12 -07:00
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chosen {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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framebuffer@0 {
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
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status = "disabled";
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};
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};
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2013-03-13 13:07:37 -06:00
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cpus {
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2013-06-10 08:48:36 -06:00
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#address-cells = <1>;
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#size-cells = <0>;
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2015-01-05 19:35:20 -07:00
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cpu0: cpu@0 {
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2013-04-18 11:41:57 -06:00
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device_type = "cpu";
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2013-03-13 13:07:37 -06:00
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compatible = "arm,cortex-a8";
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2013-04-18 11:41:57 -06:00
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reg = <0x0>;
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2015-01-05 19:35:20 -07:00
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clocks = <&cpu>;
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clock-latency = <244144>; /* 8 32k periods */
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operating-points = <
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/* kHz uV */
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1008000 1400000
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912000 1350000
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864000 1300000
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624000 1200000
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576000 1200000
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432000 1200000
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>;
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#cooling-cells = <2>;
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cooling-min-level = <0>;
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2015-03-24 10:53:27 -06:00
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cooling-max-level = <5>;
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2013-03-13 13:07:37 -06:00
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};
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};
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2015-01-11 21:34:06 -07:00
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thermal-zones {
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cpu_thermal {
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/* milliseconds */
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&rtp>;
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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trips {
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cpu_alert0: cpu_alert0 {
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/* milliCelsius */
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temperature = <850000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit: cpu_crit {
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/* milliCelsius */
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temperature = <100000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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2013-03-13 13:07:37 -06:00
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};
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};
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2012-11-14 12:17:04 -07:00
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memory {
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reg = <0x40000000 0x20000000>;
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};
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2013-01-18 14:30:36 -07:00
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2013-03-13 13:07:37 -06:00
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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2014-02-02 18:51:42 -07:00
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osc24M: clk@01c20050 {
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2013-03-13 13:07:37 -06:00
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-osc-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20050 0x4>;
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2013-04-09 07:48:04 -06:00
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clock-frequency = <24000000>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "osc24M";
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2013-03-13 13:07:37 -06:00
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};
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2014-02-02 18:51:42 -07:00
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osc32k: clk@0 {
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2013-03-13 13:07:37 -06:00
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "osc32k";
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2013-03-13 13:07:37 -06:00
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};
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2014-02-02 18:51:42 -07:00
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pll1: clk@01c20000 {
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2013-03-13 13:07:37 -06:00
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-pll1-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "pll1";
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2013-03-13 13:07:37 -06:00
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};
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2014-02-02 18:51:42 -07:00
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pll4: clk@01c20018 {
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2013-12-22 20:32:35 -07:00
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-pll1-clk";
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2013-12-22 20:32:35 -07:00
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "pll4";
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2013-12-22 20:32:35 -07:00
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};
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2014-02-02 18:51:42 -07:00
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pll5: clk@01c20020 {
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2013-12-22 20:32:38 -07:00
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#clock-cells = <1>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-pll5-clk";
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2013-12-22 20:32:38 -07:00
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reg = <0x01c20020 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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2014-02-02 18:51:42 -07:00
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pll6: clk@01c20028 {
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2013-12-22 20:32:38 -07:00
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#clock-cells = <1>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-pll6-clk";
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2013-12-22 20:32:38 -07:00
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6_sata", "pll6_other", "pll6";
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};
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2013-03-13 13:07:37 -06:00
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-cpu-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "cpu";
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2013-03-13 13:07:37 -06:00
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-axi-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "axi";
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2013-03-13 13:07:37 -06:00
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};
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2014-02-02 18:51:42 -07:00
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axi_gates: clk@01c2005c {
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2013-03-13 13:07:37 -06:00
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#clock-cells = <1>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-axi-gates-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-output-names = "axi_dram";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-ahb-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "ahb";
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2013-03-13 13:07:37 -06:00
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};
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2014-02-02 18:51:42 -07:00
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ahb_gates: clk@01c20060 {
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2013-03-13 13:07:37 -06:00
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#clock-cells = <1>;
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2013-04-19 14:14:41 -06:00
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compatible = "allwinner,sun5i-a13-ahb-gates-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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2013-04-19 14:14:41 -06:00
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clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
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"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
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"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
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"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
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"ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
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"ahb_de_fe", "ahb_iep", "ahb_mali400";
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2013-03-13 13:07:37 -06:00
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-apb0-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "apb0";
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2013-03-13 13:07:37 -06:00
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};
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2014-02-02 18:51:42 -07:00
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apb0_gates: clk@01c20068 {
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2013-03-13 13:07:37 -06:00
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#clock-cells = <1>;
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2013-04-19 14:14:41 -06:00
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compatible = "allwinner,sun5i-a13-apb0-gates-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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2013-04-19 14:14:41 -06:00
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clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
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2013-03-13 13:07:37 -06:00
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};
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2014-11-05 20:40:30 -07:00
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apb1: clk@01c20058 {
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2013-03-13 13:07:37 -06:00
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-apb1-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c20058 0x4>;
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2014-11-05 20:40:30 -07:00
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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2014-02-02 18:51:42 -07:00
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clock-output-names = "apb1";
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2013-03-13 13:07:37 -06:00
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};
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2014-02-02 18:51:42 -07:00
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apb1_gates: clk@01c2006c {
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2013-03-13 13:07:37 -06:00
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#clock-cells = <1>;
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2013-04-19 14:14:41 -06:00
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compatible = "allwinner,sun5i-a13-apb1-gates-clk";
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2013-03-13 13:07:37 -06:00
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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2013-04-19 14:14:41 -06:00
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"apb1_i2c2", "apb1_uart1", "apb1_uart3";
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2013-03-13 13:07:37 -06:00
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};
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2013-12-22 20:32:42 -07:00
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nand_clk: clk@01c20080 {
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-mod0-clk";
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2013-12-22 20:32:42 -07:00
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reg = <0x01c20080 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "nand";
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};
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ms_clk: clk@01c20084 {
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#clock-cells = <0>;
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2014-02-06 01:55:58 -07:00
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compatible = "allwinner,sun4i-a10-mod0-clk";
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2013-12-22 20:32:42 -07:00
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reg = <0x01c20084 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ms";
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};
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mmc0_clk: clk@01c20088 {
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2014-07-11 11:39:06 -06:00
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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2013-12-22 20:32:42 -07:00
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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2014-07-11 11:39:06 -06:00
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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2013-12-22 20:32:42 -07:00
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};
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mmc1_clk: clk@01c2008c {
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2014-07-11 11:39:06 -06:00
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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2013-12-22 20:32:42 -07:00
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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2014-07-11 11:39:06 -06:00
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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2013-12-22 20:32:42 -07:00
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};
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mmc2_clk: clk@01c20090 {
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2014-07-11 11:39:06 -06:00
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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2013-12-22 20:32:42 -07:00
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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2014-07-11 11:39:06 -06:00
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clock-output-names = "mmc2",
|
|
|
|
"mmc2_output",
|
|
|
|
"mmc2_sample";
|
2013-12-22 20:32:42 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
ts_clk: clk@01c20098 {
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 01:55:58 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-22 20:32:42 -07:00
|
|
|
reg = <0x01c20098 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
clock-output-names = "ts";
|
|
|
|
};
|
|
|
|
|
|
|
|
ss_clk: clk@01c2009c {
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 01:55:58 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-22 20:32:42 -07:00
|
|
|
reg = <0x01c2009c 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
clock-output-names = "ss";
|
|
|
|
};
|
|
|
|
|
|
|
|
spi0_clk: clk@01c200a0 {
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 01:55:58 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-22 20:32:42 -07:00
|
|
|
reg = <0x01c200a0 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
clock-output-names = "spi0";
|
|
|
|
};
|
|
|
|
|
|
|
|
spi1_clk: clk@01c200a4 {
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 01:55:58 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-22 20:32:42 -07:00
|
|
|
reg = <0x01c200a4 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
clock-output-names = "spi1";
|
|
|
|
};
|
|
|
|
|
|
|
|
spi2_clk: clk@01c200a8 {
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 01:55:58 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-22 20:32:42 -07:00
|
|
|
reg = <0x01c200a8 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
clock-output-names = "spi2";
|
|
|
|
};
|
|
|
|
|
|
|
|
ir0_clk: clk@01c200b0 {
|
|
|
|
#clock-cells = <0>;
|
2014-02-06 01:55:58 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-mod0-clk";
|
2013-12-22 20:32:42 -07:00
|
|
|
reg = <0x01c200b0 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
clock-output-names = "ir0";
|
|
|
|
};
|
2013-12-22 20:32:44 -07:00
|
|
|
|
2014-02-07 08:21:52 -07:00
|
|
|
usb_clk: clk@01c200cc {
|
|
|
|
#clock-cells = <1>;
|
|
|
|
#reset-cells = <1>;
|
|
|
|
compatible = "allwinner,sun5i-a13-usb-clk";
|
|
|
|
reg = <0x01c200cc 0x4>;
|
|
|
|
clocks = <&pll6 1>;
|
|
|
|
clock-output-names = "usb_ohci0", "usb_phy";
|
|
|
|
};
|
|
|
|
|
2013-12-22 20:32:44 -07:00
|
|
|
mbus_clk: clk@01c2015c {
|
|
|
|
#clock-cells = <0>;
|
2014-07-16 15:45:48 -06:00
|
|
|
compatible = "allwinner,sun5i-a13-mbus-clk";
|
2013-12-22 20:32:44 -07:00
|
|
|
reg = <0x01c2015c 0x4>;
|
|
|
|
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
|
|
|
clock-output-names = "mbus";
|
|
|
|
};
|
2013-03-13 13:07:37 -06:00
|
|
|
};
|
|
|
|
|
2013-08-03 08:07:36 -06:00
|
|
|
soc@01c00000 {
|
2013-03-13 13:07:37 -06:00
|
|
|
compatible = "simple-bus";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
ranges;
|
|
|
|
|
2014-08-04 14:09:58 -06:00
|
|
|
dma: dma-controller@01c02000 {
|
|
|
|
compatible = "allwinner,sun4i-a10-dma";
|
|
|
|
reg = <0x01c02000 0x1000>;
|
|
|
|
interrupts = <27>;
|
|
|
|
clocks = <&ahb_gates 6>;
|
|
|
|
#dma-cells = <2>;
|
|
|
|
};
|
|
|
|
|
2014-02-22 14:35:57 -07:00
|
|
|
spi0: spi@01c05000 {
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
reg = <0x01c05000 0x1000>;
|
|
|
|
interrupts = <10>;
|
|
|
|
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
|
|
|
clock-names = "ahb", "mod";
|
2014-12-16 14:59:56 -07:00
|
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
|
|
|
|
<&dma SUN4I_DMA_DEDICATED 26>;
|
2014-08-04 14:10:01 -06:00
|
|
|
dma-names = "rx", "tx";
|
2014-02-22 14:35:57 -07:00
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
};
|
|
|
|
|
|
|
|
spi1: spi@01c06000 {
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
reg = <0x01c06000 0x1000>;
|
|
|
|
interrupts = <11>;
|
|
|
|
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
|
|
|
clock-names = "ahb", "mod";
|
2014-12-16 14:59:56 -07:00
|
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
|
|
|
|
<&dma SUN4I_DMA_DEDICATED 8>;
|
2014-08-04 14:10:01 -06:00
|
|
|
dma-names = "rx", "tx";
|
2014-02-22 14:35:57 -07:00
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
};
|
|
|
|
|
2014-05-02 09:57:21 -06:00
|
|
|
mmc0: mmc@01c0f000 {
|
|
|
|
compatible = "allwinner,sun5i-a13-mmc";
|
|
|
|
reg = <0x01c0f000 0x1000>;
|
2014-07-11 11:39:06 -06:00
|
|
|
clocks = <&ahb_gates 8>,
|
|
|
|
<&mmc0_clk 0>,
|
|
|
|
<&mmc0_clk 1>,
|
|
|
|
<&mmc0_clk 2>;
|
|
|
|
clock-names = "ahb",
|
|
|
|
"mmc",
|
|
|
|
"output",
|
|
|
|
"sample";
|
2014-05-02 09:57:21 -06:00
|
|
|
interrupts = <32>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
mmc2: mmc@01c11000 {
|
|
|
|
compatible = "allwinner,sun5i-a13-mmc";
|
|
|
|
reg = <0x01c11000 0x1000>;
|
2014-07-11 11:39:06 -06:00
|
|
|
clocks = <&ahb_gates 10>,
|
|
|
|
<&mmc2_clk 0>,
|
|
|
|
<&mmc2_clk 1>,
|
|
|
|
<&mmc2_clk 2>;
|
|
|
|
clock-names = "ahb",
|
|
|
|
"mmc",
|
|
|
|
"output",
|
|
|
|
"sample";
|
2014-05-02 09:57:21 -06:00
|
|
|
interrupts = <34>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2014-03-01 12:26:24 -07:00
|
|
|
usbphy: phy@01c13400 {
|
|
|
|
#phy-cells = <1>;
|
|
|
|
compatible = "allwinner,sun5i-a13-usb-phy";
|
|
|
|
reg = <0x01c13400 0x10 0x01c14800 0x4>;
|
|
|
|
reg-names = "phy_ctrl", "pmu1";
|
|
|
|
clocks = <&usb_clk 8>;
|
|
|
|
clock-names = "usb_phy";
|
2014-12-18 04:10:35 -07:00
|
|
|
resets = <&usb_clk 0>, <&usb_clk 1>;
|
|
|
|
reset-names = "usb0_reset", "usb1_reset";
|
2014-03-01 12:26:24 -07:00
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
ehci0: usb@01c14000 {
|
|
|
|
compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
|
|
|
|
reg = <0x01c14000 0x100>;
|
|
|
|
interrupts = <39>;
|
|
|
|
clocks = <&ahb_gates 1>;
|
|
|
|
phys = <&usbphy 1>;
|
|
|
|
phy-names = "usb";
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
ohci0: usb@01c14400 {
|
|
|
|
compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
|
|
|
|
reg = <0x01c14400 0x100>;
|
|
|
|
interrupts = <40>;
|
|
|
|
clocks = <&usb_clk 6>, <&ahb_gates 2>;
|
|
|
|
phys = <&usbphy 1>;
|
|
|
|
phy-names = "usb";
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2014-02-22 14:35:57 -07:00
|
|
|
spi2: spi@01c17000 {
|
|
|
|
compatible = "allwinner,sun4i-a10-spi";
|
|
|
|
reg = <0x01c17000 0x1000>;
|
|
|
|
interrupts = <12>;
|
|
|
|
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
|
|
|
clock-names = "ahb", "mod";
|
2014-12-16 14:59:56 -07:00
|
|
|
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
|
|
|
|
<&dma SUN4I_DMA_DEDICATED 28>;
|
2014-08-04 14:10:01 -06:00
|
|
|
dma-names = "rx", "tx";
|
2014-02-22 14:35:57 -07:00
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
};
|
|
|
|
|
2013-03-13 13:07:37 -06:00
|
|
|
intc: interrupt-controller@01c20400 {
|
2014-02-07 13:50:26 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-ic";
|
2013-03-13 13:07:37 -06:00
|
|
|
reg = <0x01c20400 0x400>;
|
|
|
|
interrupt-controller;
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
};
|
|
|
|
|
2013-01-27 11:26:05 -07:00
|
|
|
pio: pinctrl@01c20800 {
|
2013-01-18 14:30:36 -07:00
|
|
|
compatible = "allwinner,sun5i-a13-pinctrl";
|
|
|
|
reg = <0x01c20800 0x400>;
|
2013-04-06 07:00:48 -06:00
|
|
|
interrupts = <28>;
|
2013-03-27 15:20:41 -06:00
|
|
|
clocks = <&apb0_gates 5>;
|
2013-01-27 11:26:05 -07:00
|
|
|
gpio-controller;
|
2013-04-06 07:00:48 -06:00
|
|
|
interrupt-controller;
|
2014-06-30 15:57:51 -06:00
|
|
|
#interrupt-cells = <2>;
|
2013-01-18 14:30:36 -07:00
|
|
|
#size-cells = <0>;
|
2013-01-27 11:26:05 -07:00
|
|
|
#gpio-cells = <3>;
|
2013-01-18 14:30:37 -07:00
|
|
|
|
|
|
|
uart1_pins_a: uart1@0 {
|
|
|
|
allwinner,pins = "PE10", "PE11";
|
|
|
|
allwinner,function = "uart1";
|
2014-12-16 14:59:57 -07:00
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
2013-01-18 14:30:37 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
uart1_pins_b: uart1@1 {
|
|
|
|
allwinner,pins = "PG3", "PG4";
|
|
|
|
allwinner,function = "uart1";
|
2014-12-16 14:59:57 -07:00
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
2013-01-18 14:30:37 -07:00
|
|
|
};
|
2013-03-10 06:36:02 -06:00
|
|
|
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
|
|
allwinner,pins = "PB0", "PB1";
|
|
|
|
allwinner,function = "i2c0";
|
2014-12-16 14:59:57 -07:00
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
2013-03-10 06:36:02 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
|
|
allwinner,pins = "PB15", "PB16";
|
|
|
|
allwinner,function = "i2c1";
|
2014-12-16 14:59:57 -07:00
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
2013-03-10 06:36:02 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
|
|
allwinner,pins = "PB17", "PB18";
|
|
|
|
allwinner,function = "i2c2";
|
2014-12-16 14:59:57 -07:00
|
|
|
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
2013-03-10 06:36:02 -06:00
|
|
|
};
|
2014-04-26 04:16:12 -06:00
|
|
|
|
|
|
|
mmc0_pins_a: mmc0@0 {
|
|
|
|
allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
|
|
|
|
allwinner,function = "mmc0";
|
2014-12-16 14:59:57 -07:00
|
|
|
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
|
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
2014-04-26 04:16:12 -06:00
|
|
|
};
|
2013-01-18 14:30:36 -07:00
|
|
|
};
|
2013-03-13 13:07:37 -06:00
|
|
|
|
|
|
|
timer@01c20c00 {
|
2014-02-06 02:40:32 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-timer";
|
2013-03-13 13:07:37 -06:00
|
|
|
reg = <0x01c20c00 0x90>;
|
|
|
|
interrupts = <22>;
|
|
|
|
clocks = <&osc24M>;
|
|
|
|
};
|
|
|
|
|
|
|
|
wdt: watchdog@01c20c90 {
|
2014-02-07 14:29:26 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-wdt";
|
2013-03-13 13:07:37 -06:00
|
|
|
reg = <0x01c20c90 0x10>;
|
|
|
|
};
|
|
|
|
|
2014-12-23 03:13:21 -07:00
|
|
|
lradc: lradc@01c22800 {
|
|
|
|
compatible = "allwinner,sun4i-a10-lradc-keys";
|
|
|
|
reg = <0x01c22800 0x100>;
|
|
|
|
interrupts = <31>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
2013-09-03 04:33:28 -06:00
|
|
|
sid: eeprom@01c23800 {
|
2014-02-07 14:20:40 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-sid";
|
2013-09-03 04:33:28 -06:00
|
|
|
reg = <0x01c23800 0x10>;
|
|
|
|
};
|
|
|
|
|
2013-12-31 09:20:51 -07:00
|
|
|
rtp: rtp@01c25000 {
|
2014-02-02 06:52:40 -07:00
|
|
|
compatible = "allwinner,sun4i-a10-ts";
|
2013-12-31 09:20:51 -07:00
|
|
|
reg = <0x01c25000 0x100>;
|
|
|
|
interrupts = <29>;
|
2015-01-05 19:35:15 -07:00
|
|
|
#thermal-sensor-cells = <0>;
|
2013-12-31 09:20:51 -07:00
|
|
|
};
|
|
|
|
|
2013-03-13 13:07:37 -06:00
|
|
|
uart1: serial@01c28400 {
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
reg = <0x01c28400 0x400>;
|
|
|
|
interrupts = <2>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
reg-io-width = <4>;
|
|
|
|
clocks = <&apb1_gates 17>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
|
|
|
|
|
|
|
uart3: serial@01c28c00 {
|
|
|
|
compatible = "snps,dw-apb-uart";
|
|
|
|
reg = <0x01c28c00 0x400>;
|
|
|
|
interrupts = <4>;
|
|
|
|
reg-shift = <2>;
|
|
|
|
reg-io-width = <4>;
|
|
|
|
clocks = <&apb1_gates 19>;
|
|
|
|
status = "disabled";
|
|
|
|
};
|
2013-03-10 06:34:36 -06:00
|
|
|
|
|
|
|
i2c0: i2c@01c2ac00 {
|
2014-03-31 06:54:58 -06:00
|
|
|
compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
|
2013-03-10 06:34:36 -06:00
|
|
|
reg = <0x01c2ac00 0x400>;
|
|
|
|
interrupts = <7>;
|
|
|
|
clocks = <&apb1_gates 0>;
|
|
|
|
status = "disabled";
|
2014-04-13 05:41:04 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2013-03-10 06:34:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
i2c1: i2c@01c2b000 {
|
2014-03-31 06:54:58 -06:00
|
|
|
compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
|
2013-03-10 06:34:36 -06:00
|
|
|
reg = <0x01c2b000 0x400>;
|
|
|
|
interrupts = <8>;
|
|
|
|
clocks = <&apb1_gates 1>;
|
|
|
|
status = "disabled";
|
2014-04-13 05:41:04 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2013-03-10 06:34:36 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
i2c2: i2c@01c2b400 {
|
2014-03-31 06:54:58 -06:00
|
|
|
compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
|
2013-03-10 06:34:36 -06:00
|
|
|
reg = <0x01c2b400 0x400>;
|
|
|
|
interrupts = <9>;
|
|
|
|
clocks = <&apb1_gates 2>;
|
|
|
|
status = "disabled";
|
2014-04-13 05:41:04 -06:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <0>;
|
2013-03-10 06:34:36 -06:00
|
|
|
};
|
2013-11-07 04:01:48 -07:00
|
|
|
|
|
|
|
timer@01c60000 {
|
|
|
|
compatible = "allwinner,sun5i-a13-hstimer";
|
|
|
|
reg = <0x01c60000 0x1000>;
|
|
|
|
interrupts = <82>, <83>;
|
|
|
|
clocks = <&ahb_gates 28>;
|
|
|
|
};
|
2013-01-18 14:30:36 -07:00
|
|
|
};
|
2012-11-14 12:17:04 -07:00
|
|
|
};
|