2012-04-15 22:13:29 -06:00
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/*
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2010-01-13 16:13:37 -07:00
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* Copyright 2009 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5P - Common clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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2011-12-21 17:26:03 -07:00
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#include <linux/device.h>
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2010-01-13 16:13:37 -07:00
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#include <linux/io.h>
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#include <asm/div64.h>
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2010-10-13 19:39:08 -06:00
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#include <mach/regs-clock.h>
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2010-01-13 16:13:37 -07:00
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#include <plat/clock.h>
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#include <plat/clock-clksrc.h>
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#include <plat/s5p-clock.h>
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/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
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* clk_ext_xtal_mux.
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*/
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struct clk clk_ext_xtal_mux = {
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.name = "ext_xtal",
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.id = -1,
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};
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2010-04-19 05:05:08 -06:00
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struct clk clk_xusbxti = {
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.name = "xusbxti",
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.id = -1,
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2012-07-12 03:06:28 -06:00
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.rate = 24000000,
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2010-04-19 05:05:08 -06:00
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};
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2010-05-14 01:27:28 -06:00
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struct clk s5p_clk_27m = {
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2010-02-24 00:40:36 -07:00
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.name = "clk_27m",
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.id = -1,
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.rate = 27000000,
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};
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2010-01-13 16:13:37 -07:00
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/* 48MHz USB Phy clock output */
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struct clk clk_48m = {
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.name = "clk_48m",
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.id = -1,
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.rate = 48000000,
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};
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/* APLL clock output
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* No need .ctrlbit, this is always on
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*/
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struct clk clk_fout_apll = {
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.name = "fout_apll",
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.id = -1,
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};
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2012-01-22 05:46:13 -07:00
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/* BPLL clock output */
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struct clk clk_fout_bpll = {
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.name = "fout_bpll",
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.id = -1,
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};
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2012-04-24 15:54:15 -06:00
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struct clk clk_fout_bpll_div2 = {
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.name = "fout_bpll_div2",
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.id = -1,
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};
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2012-01-22 05:46:13 -07:00
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/* CPLL clock output */
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struct clk clk_fout_cpll = {
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.name = "fout_cpll",
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.id = -1,
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};
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2010-01-13 16:13:37 -07:00
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/* MPLL clock output
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* No need .ctrlbit, this is always on
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*/
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struct clk clk_fout_mpll = {
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.name = "fout_mpll",
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.id = -1,
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};
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2012-04-24 15:54:15 -06:00
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struct clk clk_fout_mpll_div2 = {
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.name = "fout_mpll_div2",
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.id = -1,
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};
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2010-01-13 16:13:37 -07:00
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/* EPLL clock output */
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struct clk clk_fout_epll = {
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.name = "fout_epll",
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.id = -1,
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.ctrlbit = (1 << 31),
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};
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2010-09-01 00:35:30 -06:00
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/* DPLL clock output */
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struct clk clk_fout_dpll = {
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.name = "fout_dpll",
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.id = -1,
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.ctrlbit = (1 << 31),
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};
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2010-05-16 18:38:52 -06:00
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/* VPLL clock output */
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struct clk clk_fout_vpll = {
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.name = "fout_vpll",
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.id = -1,
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.ctrlbit = (1 << 31),
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};
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2010-01-13 16:13:37 -07:00
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/* Possible clock sources for APLL Mux */
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static struct clk *clk_src_apll_list[] = {
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[0] = &clk_fin_apll,
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[1] = &clk_fout_apll,
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};
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struct clksrc_sources clk_src_apll = {
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.sources = clk_src_apll_list,
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.nr_sources = ARRAY_SIZE(clk_src_apll_list),
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};
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2012-01-22 05:46:13 -07:00
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/* Possible clock sources for BPLL Mux */
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static struct clk *clk_src_bpll_list[] = {
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[0] = &clk_fin_bpll,
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[1] = &clk_fout_bpll,
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};
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struct clksrc_sources clk_src_bpll = {
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.sources = clk_src_bpll_list,
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.nr_sources = ARRAY_SIZE(clk_src_bpll_list),
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};
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2012-04-24 15:54:15 -06:00
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static struct clk *clk_src_bpll_fout_list[] = {
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[0] = &clk_fout_bpll_div2,
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[1] = &clk_fout_bpll,
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};
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struct clksrc_sources clk_src_bpll_fout = {
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.sources = clk_src_bpll_fout_list,
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.nr_sources = ARRAY_SIZE(clk_src_bpll_fout_list),
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};
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2012-01-22 05:46:13 -07:00
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/* Possible clock sources for CPLL Mux */
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static struct clk *clk_src_cpll_list[] = {
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[0] = &clk_fin_cpll,
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[1] = &clk_fout_cpll,
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};
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struct clksrc_sources clk_src_cpll = {
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.sources = clk_src_cpll_list,
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.nr_sources = ARRAY_SIZE(clk_src_cpll_list),
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};
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2010-01-13 16:13:37 -07:00
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/* Possible clock sources for MPLL Mux */
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static struct clk *clk_src_mpll_list[] = {
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[0] = &clk_fin_mpll,
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[1] = &clk_fout_mpll,
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};
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struct clksrc_sources clk_src_mpll = {
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.sources = clk_src_mpll_list,
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.nr_sources = ARRAY_SIZE(clk_src_mpll_list),
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};
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2012-04-24 15:54:15 -06:00
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static struct clk *clk_src_mpll_fout_list[] = {
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[0] = &clk_fout_mpll_div2,
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[1] = &clk_fout_mpll,
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};
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struct clksrc_sources clk_src_mpll_fout = {
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.sources = clk_src_mpll_fout_list,
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.nr_sources = ARRAY_SIZE(clk_src_mpll_fout_list),
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};
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2010-01-13 16:13:37 -07:00
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/* Possible clock sources for EPLL Mux */
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static struct clk *clk_src_epll_list[] = {
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[0] = &clk_fin_epll,
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[1] = &clk_fout_epll,
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};
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struct clksrc_sources clk_src_epll = {
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.sources = clk_src_epll_list,
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.nr_sources = ARRAY_SIZE(clk_src_epll_list),
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};
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2010-09-01 00:35:30 -06:00
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/* Possible clock sources for DPLL Mux */
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static struct clk *clk_src_dpll_list[] = {
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[0] = &clk_fin_dpll,
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[1] = &clk_fout_dpll,
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};
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struct clksrc_sources clk_src_dpll = {
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.sources = clk_src_dpll_list,
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.nr_sources = ARRAY_SIZE(clk_src_dpll_list),
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};
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2010-02-24 00:40:36 -07:00
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struct clk clk_vpll = {
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.name = "vpll",
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.id = -1,
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};
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2010-01-13 16:13:37 -07:00
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int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable)
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{
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unsigned int ctrlbit = clk->ctrlbit;
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u32 con;
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con = __raw_readl(reg);
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con = enable ? (con | ctrlbit) : (con & ~ctrlbit);
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__raw_writel(con, reg);
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return 0;
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}
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2010-10-13 19:39:08 -06:00
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int s5p_epll_enable(struct clk *clk, int enable)
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{
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unsigned int ctrlbit = clk->ctrlbit;
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unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
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if (enable)
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__raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
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else
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__raw_writel(epll_con, S5P_EPLL_CON);
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return 0;
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}
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unsigned long s5p_epll_get_rate(struct clk *clk)
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{
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return clk->rate;
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}
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2011-07-17 23:44:19 -06:00
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int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk *pclk;
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int ret;
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pclk = clk_get_parent(clk);
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if (IS_ERR(pclk))
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return -EINVAL;
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ret = pclk->ops->set_rate(pclk, rate);
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clk_put(pclk);
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return ret;
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}
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unsigned long s5p_spdif_get_rate(struct clk *clk)
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{
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struct clk *pclk;
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int rate;
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pclk = clk_get_parent(clk);
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if (IS_ERR(pclk))
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return -EINVAL;
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2011-08-19 05:52:29 -06:00
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rate = pclk->ops->get_rate(pclk);
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2011-07-17 23:44:19 -06:00
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clk_put(pclk);
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return rate;
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}
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struct clk_ops s5p_sclk_spdif_ops = {
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.set_rate = s5p_spdif_set_rate,
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.get_rate = s5p_spdif_get_rate,
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};
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2010-01-13 16:13:37 -07:00
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static struct clk *s5p_clks[] __initdata = {
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&clk_ext_xtal_mux,
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&clk_48m,
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2010-02-24 00:40:36 -07:00
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&s5p_clk_27m,
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2010-01-13 16:13:37 -07:00
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&clk_fout_apll,
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&clk_fout_mpll,
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&clk_fout_epll,
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2010-09-01 00:35:30 -06:00
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&clk_fout_dpll,
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2010-05-16 18:38:52 -06:00
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&clk_fout_vpll,
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2010-02-24 00:40:36 -07:00
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&clk_vpll,
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2010-05-27 20:41:16 -06:00
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&clk_xusbxti,
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2010-01-13 16:13:37 -07:00
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};
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void __init s5p_register_clocks(unsigned long xtal_freq)
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{
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int ret;
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clk_ext_xtal_mux.rate = xtal_freq;
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ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks));
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if (ret > 0)
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printk(KERN_ERR "Failed to register s5p clocks\n");
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}
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