2009-06-05 04:28:40 -06:00
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/*
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* ALSA SoC McASP Audio Layer for TI DAVINCI processor
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*
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* Multi-channel Audio Serial Port Driver
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*
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* Author: Nirmal Pandey <n-pandey@ti.com>,
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* Suresh Rajashekara <suresh.r@ti.com>
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* Steve Chen <schen@.mvista.com>
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*
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* Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
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* Copyright: (C) 2009 Texas Instruments, India
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2009-06-05 04:28:40 -06:00
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#include <linux/delay.h>
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#include <linux/io.h>
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2012-08-08 09:10:32 -06:00
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#include <linux/pm_runtime.h>
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2012-08-27 07:26:42 -06:00
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_device.h>
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2009-06-05 04:28:40 -06:00
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include "davinci-pcm.h"
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#include "davinci-mcasp.h"
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/*
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* McASP register definitions
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*/
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#define DAVINCI_MCASP_PID_REG 0x00
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#define DAVINCI_MCASP_PWREMUMGT_REG 0x04
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#define DAVINCI_MCASP_PFUNC_REG 0x10
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#define DAVINCI_MCASP_PDIR_REG 0x14
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#define DAVINCI_MCASP_PDOUT_REG 0x18
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#define DAVINCI_MCASP_PDSET_REG 0x1c
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#define DAVINCI_MCASP_PDCLR_REG 0x20
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#define DAVINCI_MCASP_TLGC_REG 0x30
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#define DAVINCI_MCASP_TLMR_REG 0x34
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#define DAVINCI_MCASP_GBLCTL_REG 0x44
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#define DAVINCI_MCASP_AMUTE_REG 0x48
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#define DAVINCI_MCASP_LBCTL_REG 0x4c
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#define DAVINCI_MCASP_TXDITCTL_REG 0x50
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#define DAVINCI_MCASP_GBLCTLR_REG 0x60
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#define DAVINCI_MCASP_RXMASK_REG 0x64
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#define DAVINCI_MCASP_RXFMT_REG 0x68
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#define DAVINCI_MCASP_RXFMCTL_REG 0x6c
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#define DAVINCI_MCASP_ACLKRCTL_REG 0x70
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#define DAVINCI_MCASP_AHCLKRCTL_REG 0x74
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#define DAVINCI_MCASP_RXTDM_REG 0x78
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#define DAVINCI_MCASP_EVTCTLR_REG 0x7c
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#define DAVINCI_MCASP_RXSTAT_REG 0x80
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#define DAVINCI_MCASP_RXTDMSLOT_REG 0x84
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#define DAVINCI_MCASP_RXCLKCHK_REG 0x88
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#define DAVINCI_MCASP_REVTCTL_REG 0x8c
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#define DAVINCI_MCASP_GBLCTLX_REG 0xa0
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#define DAVINCI_MCASP_TXMASK_REG 0xa4
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#define DAVINCI_MCASP_TXFMT_REG 0xa8
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#define DAVINCI_MCASP_TXFMCTL_REG 0xac
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#define DAVINCI_MCASP_ACLKXCTL_REG 0xb0
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#define DAVINCI_MCASP_AHCLKXCTL_REG 0xb4
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#define DAVINCI_MCASP_TXTDM_REG 0xb8
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#define DAVINCI_MCASP_EVTCTLX_REG 0xbc
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#define DAVINCI_MCASP_TXSTAT_REG 0xc0
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#define DAVINCI_MCASP_TXTDMSLOT_REG 0xc4
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#define DAVINCI_MCASP_TXCLKCHK_REG 0xc8
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#define DAVINCI_MCASP_XEVTCTL_REG 0xcc
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/* Left(even TDM Slot) Channel Status Register File */
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#define DAVINCI_MCASP_DITCSRA_REG 0x100
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/* Right(odd TDM slot) Channel Status Register File */
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#define DAVINCI_MCASP_DITCSRB_REG 0x118
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/* Left(even TDM slot) User Data Register File */
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#define DAVINCI_MCASP_DITUDRA_REG 0x130
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/* Right(odd TDM Slot) User Data Register File */
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#define DAVINCI_MCASP_DITUDRB_REG 0x148
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/* Serializer n Control Register */
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#define DAVINCI_MCASP_XRSRCTL_BASE_REG 0x180
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#define DAVINCI_MCASP_XRSRCTL_REG(n) (DAVINCI_MCASP_XRSRCTL_BASE_REG + \
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(n << 2))
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/* Transmit Buffer for Serializer n */
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#define DAVINCI_MCASP_TXBUF_REG 0x200
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/* Receive Buffer for Serializer n */
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#define DAVINCI_MCASP_RXBUF_REG 0x280
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2009-08-11 14:58:52 -06:00
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/* McASP FIFO Registers */
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#define DAVINCI_MCASP_WFIFOCTL (0x1010)
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#define DAVINCI_MCASP_WFIFOSTS (0x1014)
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#define DAVINCI_MCASP_RFIFOCTL (0x1018)
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#define DAVINCI_MCASP_RFIFOSTS (0x101C)
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#define MCASP_VER3_WFIFOCTL (0x1000)
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#define MCASP_VER3_WFIFOSTS (0x1004)
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#define MCASP_VER3_RFIFOCTL (0x1008)
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#define MCASP_VER3_RFIFOSTS (0x100C)
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2009-06-05 04:28:40 -06:00
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/*
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* DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
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* Register Bits
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*/
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#define MCASP_FREE BIT(0)
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#define MCASP_SOFT BIT(1)
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/*
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* DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
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*/
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#define AXR(n) (1<<n)
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#define PFUNC_AMUTE BIT(25)
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#define ACLKX BIT(26)
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#define AHCLKX BIT(27)
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#define AFSX BIT(28)
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#define ACLKR BIT(29)
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#define AHCLKR BIT(30)
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#define AFSR BIT(31)
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/*
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* DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
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*/
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#define AXR(n) (1<<n)
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#define PDIR_AMUTE BIT(25)
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#define ACLKX BIT(26)
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#define AHCLKX BIT(27)
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#define AFSX BIT(28)
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#define ACLKR BIT(29)
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#define AHCLKR BIT(30)
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#define AFSR BIT(31)
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/*
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* DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
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*/
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#define DITEN BIT(0) /* Transmit DIT mode enable/disable */
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#define VA BIT(2)
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#define VB BIT(3)
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/*
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* DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
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*/
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#define TXROT(val) (val)
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#define TXSEL BIT(3)
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#define TXSSZ(val) (val<<4)
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#define TXPBIT(val) (val<<8)
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#define TXPAD(val) (val<<13)
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#define TXORD BIT(15)
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#define FSXDLY(val) (val<<16)
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/*
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* DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
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*/
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#define RXROT(val) (val)
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#define RXSEL BIT(3)
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#define RXSSZ(val) (val<<4)
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#define RXPBIT(val) (val<<8)
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#define RXPAD(val) (val<<13)
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#define RXORD BIT(15)
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#define FSRDLY(val) (val<<16)
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/*
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* DAVINCI_MCASP_TXFMCTL_REG - Transmit Frame Control Register Bits
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*/
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#define FSXPOL BIT(0)
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#define AFSXE BIT(1)
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#define FSXDUR BIT(4)
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#define FSXMOD(val) (val<<7)
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/*
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* DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
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*/
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#define FSRPOL BIT(0)
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#define AFSRE BIT(1)
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#define FSRDUR BIT(4)
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#define FSRMOD(val) (val<<7)
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/*
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* DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
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*/
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#define ACLKXDIV(val) (val)
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#define ACLKXE BIT(5)
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#define TX_ASYNC BIT(6)
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#define ACLKXPOL BIT(7)
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2012-10-04 07:08:39 -06:00
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#define ACLKXDIV_MASK 0x1f
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2009-06-05 04:28:40 -06:00
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/*
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* DAVINCI_MCASP_ACLKRCTL_REG Receive Clock Control Register Bits
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*/
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#define ACLKRDIV(val) (val)
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#define ACLKRE BIT(5)
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#define RX_ASYNC BIT(6)
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#define ACLKRPOL BIT(7)
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2012-10-04 07:08:39 -06:00
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#define ACLKRDIV_MASK 0x1f
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2009-06-05 04:28:40 -06:00
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/*
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* DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
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* Register Bits
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*/
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#define AHCLKXDIV(val) (val)
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#define AHCLKXPOL BIT(14)
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#define AHCLKXE BIT(15)
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#define AHCLKXDIV_MASK 0xfff
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2009-06-05 04:28:40 -06:00
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/*
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* DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
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* Register Bits
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*/
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#define AHCLKRDIV(val) (val)
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#define AHCLKRPOL BIT(14)
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#define AHCLKRE BIT(15)
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2012-10-04 07:08:39 -06:00
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#define AHCLKRDIV_MASK 0xfff
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2009-06-05 04:28:40 -06:00
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/*
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* DAVINCI_MCASP_XRSRCTL_BASE_REG - Serializer Control Register Bits
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*/
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#define MODE(val) (val)
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#define DISMOD (val)(val<<2)
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#define TXSTATE BIT(4)
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#define RXSTATE BIT(5)
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#define SRMOD_MASK 3
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#define SRMOD_INACTIVE 0
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2009-06-05 04:28:40 -06:00
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/*
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* DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
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*/
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#define LBEN BIT(0)
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#define LBORD BIT(1)
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#define LBGENMODE(val) (val<<2)
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/*
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* DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
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*/
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#define TXTDMS(n) (1<<n)
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/*
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* DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
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*/
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#define RXTDMS(n) (1<<n)
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/*
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* DAVINCI_MCASP_GBLCTL_REG - Global Control Register Bits
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*/
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#define RXCLKRST BIT(0) /* Receiver Clock Divider Reset */
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#define RXHCLKRST BIT(1) /* Receiver High Frequency Clock Divider */
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#define RXSERCLR BIT(2) /* Receiver Serializer Clear */
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#define RXSMRST BIT(3) /* Receiver State Machine Reset */
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#define RXFSRST BIT(4) /* Frame Sync Generator Reset */
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#define TXCLKRST BIT(8) /* Transmitter Clock Divider Reset */
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#define TXHCLKRST BIT(9) /* Transmitter High Frequency Clock Divider*/
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#define TXSERCLR BIT(10) /* Transmit Serializer Clear */
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#define TXSMRST BIT(11) /* Transmitter State Machine Reset */
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#define TXFSRST BIT(12) /* Frame Sync Generator Reset */
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/*
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* DAVINCI_MCASP_AMUTE_REG - Mute Control Register Bits
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*/
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#define MUTENA(val) (val)
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#define MUTEINPOL BIT(2)
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#define MUTEINENA BIT(3)
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#define MUTEIN BIT(4)
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#define MUTER BIT(5)
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#define MUTEX BIT(6)
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#define MUTEFSR BIT(7)
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#define MUTEFSX BIT(8)
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#define MUTEBADCLKR BIT(9)
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#define MUTEBADCLKX BIT(10)
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#define MUTERXDMAERR BIT(11)
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#define MUTETXDMAERR BIT(12)
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|
|
|
|
|
/*
|
|
|
|
* DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
|
|
|
|
*/
|
|
|
|
#define RXDATADMADIS BIT(0)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
|
|
|
|
*/
|
|
|
|
#define TXDATADMADIS BIT(0)
|
|
|
|
|
2009-08-11 14:58:52 -06:00
|
|
|
/*
|
|
|
|
* DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
|
|
|
|
*/
|
|
|
|
#define FIFO_ENABLE BIT(16)
|
|
|
|
#define NUMEVT_MASK (0xFF << 8)
|
|
|
|
#define NUMDMA_MASK (0xFF)
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
#define DAVINCI_MCASP_NUM_SERIALIZER 16
|
|
|
|
|
|
|
|
static inline void mcasp_set_bits(void __iomem *reg, u32 val)
|
|
|
|
{
|
|
|
|
__raw_writel(__raw_readl(reg) | val, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void mcasp_clr_bits(void __iomem *reg, u32 val)
|
|
|
|
{
|
|
|
|
__raw_writel((__raw_readl(reg) & ~(val)), reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void mcasp_mod_bits(void __iomem *reg, u32 val, u32 mask)
|
|
|
|
{
|
|
|
|
__raw_writel((__raw_readl(reg) & ~mask) | val, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void mcasp_set_reg(void __iomem *reg, u32 val)
|
|
|
|
{
|
|
|
|
__raw_writel(val, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline u32 mcasp_get_reg(void __iomem *reg)
|
|
|
|
{
|
|
|
|
return (unsigned int)__raw_readl(reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
|
|
|
|
{
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
mcasp_set_bits(regs, val);
|
|
|
|
|
|
|
|
/* programming GBLCTL needs to read back from GBLCTL and verfiy */
|
|
|
|
/* loop count is to avoid the lock-up */
|
|
|
|
for (i = 0; i < 1000; i++) {
|
|
|
|
if ((mcasp_get_reg(regs) & val) == val)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
|
|
|
|
printk(KERN_ERR "GBLCTL write error\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mcasp_start_rx(struct davinci_audio_dev *dev)
|
|
|
|
{
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
|
|
|
|
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0);
|
|
|
|
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mcasp_start_tx(struct davinci_audio_dev *dev)
|
|
|
|
{
|
2009-08-11 14:58:52 -06:00
|
|
|
u8 offset = 0, i;
|
|
|
|
u32 cnt;
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
|
|
|
|
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
|
|
|
|
mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
|
2009-08-11 14:58:52 -06:00
|
|
|
for (i = 0; i < dev->num_serializer; i++) {
|
|
|
|
if (dev->serial_dir[i] == TX_MODE) {
|
|
|
|
offset = i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* wait for TX ready */
|
|
|
|
cnt = 0;
|
|
|
|
while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
|
|
|
|
TXSTATE) && (cnt < 100000))
|
|
|
|
cnt++;
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream)
|
|
|
|
{
|
2009-09-23 08:12:08 -06:00
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
2012-08-08 09:10:31 -06:00
|
|
|
if (dev->txnumevt) { /* enable FIFO */
|
2012-09-03 02:10:40 -06:00
|
|
|
switch (dev->version) {
|
|
|
|
case MCASP_VERSION_3:
|
|
|
|
mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
|
2012-08-08 09:10:31 -06:00
|
|
|
FIFO_ENABLE);
|
2012-09-03 02:10:40 -06:00
|
|
|
mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL,
|
2009-09-23 08:12:08 -06:00
|
|
|
FIFO_ENABLE);
|
2012-09-03 02:10:40 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
mcasp_clr_bits(dev->base +
|
|
|
|
DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
|
|
|
|
mcasp_set_bits(dev->base +
|
|
|
|
DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
|
|
|
|
}
|
2012-08-08 09:10:31 -06:00
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_start_tx(dev);
|
2009-09-23 08:12:08 -06:00
|
|
|
} else {
|
2012-08-08 09:10:31 -06:00
|
|
|
if (dev->rxnumevt) { /* enable FIFO */
|
2012-09-03 02:10:40 -06:00
|
|
|
switch (dev->version) {
|
|
|
|
case MCASP_VERSION_3:
|
|
|
|
mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
|
2012-08-08 09:10:31 -06:00
|
|
|
FIFO_ENABLE);
|
2012-09-03 02:10:40 -06:00
|
|
|
mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL,
|
2009-09-23 08:12:08 -06:00
|
|
|
FIFO_ENABLE);
|
2012-09-03 02:10:40 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
mcasp_clr_bits(dev->base +
|
|
|
|
DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
|
|
|
|
mcasp_set_bits(dev->base +
|
|
|
|
DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
|
|
|
|
}
|
2012-08-08 09:10:31 -06:00
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_start_rx(dev);
|
2009-09-23 08:12:08 -06:00
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void mcasp_stop_rx(struct davinci_audio_dev *dev)
|
|
|
|
{
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void mcasp_stop_tx(struct davinci_audio_dev *dev)
|
|
|
|
{
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream)
|
|
|
|
{
|
2009-09-23 08:12:08 -06:00
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
2012-09-03 02:10:40 -06:00
|
|
|
if (dev->txnumevt) { /* disable FIFO */
|
|
|
|
switch (dev->version) {
|
|
|
|
case MCASP_VERSION_3:
|
|
|
|
mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL,
|
2009-09-23 08:12:08 -06:00
|
|
|
FIFO_ENABLE);
|
2012-09-03 02:10:40 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
mcasp_clr_bits(dev->base +
|
|
|
|
DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
|
|
|
|
}
|
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_stop_tx(dev);
|
2009-09-23 08:12:08 -06:00
|
|
|
} else {
|
2012-09-03 02:10:40 -06:00
|
|
|
if (dev->rxnumevt) { /* disable FIFO */
|
|
|
|
switch (dev->version) {
|
|
|
|
case MCASP_VERSION_3:
|
|
|
|
mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL,
|
2009-09-23 08:12:08 -06:00
|
|
|
FIFO_ENABLE);
|
2012-09-03 02:10:40 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
mcasp_clr_bits(dev->base +
|
|
|
|
DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
|
|
|
|
}
|
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_stop_rx(dev);
|
2009-09-23 08:12:08 -06:00
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
|
|
|
|
unsigned int fmt)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
|
2009-06-05 04:28:40 -06:00
|
|
|
void __iomem *base = dev->base;
|
|
|
|
|
2012-10-04 07:08:42 -06:00
|
|
|
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_DSP_B:
|
|
|
|
case SND_SOC_DAIFMT_AC97:
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* configure a full-word SYNC pulse (LRCLK) */
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
|
|
|
|
|
|
|
|
/* make 1st data bit occur one ACLK cycle after the frame sync */
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_CBS_CFS:
|
|
|
|
/* codec is clock and frame slave */
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
|
|
|
|
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
|
|
|
|
|
2013-04-26 06:38:11 -06:00
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
|
|
|
|
ACLKX | ACLKR);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
|
|
|
|
AFSX | AFSR);
|
2009-06-05 04:28:40 -06:00
|
|
|
break;
|
2009-08-11 14:59:12 -06:00
|
|
|
case SND_SOC_DAIFMT_CBM_CFS:
|
|
|
|
/* codec is clock master and frame slave */
|
2011-04-21 12:19:03 -06:00
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
|
2009-08-11 14:59:12 -06:00
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
|
|
|
|
|
2011-04-21 12:19:03 -06:00
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
|
2009-08-11 14:59:12 -06:00
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
|
|
|
|
|
2011-04-21 12:19:04 -06:00
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
|
|
|
|
ACLKX | ACLKR);
|
2011-04-21 12:19:02 -06:00
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG,
|
2011-04-21 12:19:04 -06:00
|
|
|
AFSX | AFSR);
|
2009-08-11 14:59:12 -06:00
|
|
|
break;
|
2009-06-05 04:28:40 -06:00
|
|
|
case SND_SOC_DAIFMT_CBM_CFM:
|
|
|
|
/* codec is clock and frame master */
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
|
|
|
|
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
|
|
|
|
|
2011-04-21 12:19:02 -06:00
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_PDIR_REG,
|
|
|
|
ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
|
2009-06-05 04:28:40 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
|
|
|
|
case SND_SOC_DAIFMT_IB_NF:
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
|
|
|
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_DAIFMT_NB_IF:
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
|
|
|
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_DAIFMT_IB_IF:
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
|
|
|
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SND_SOC_DAIFMT_NB_NF:
|
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
|
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
|
|
|
|
|
2013-05-02 23:37:36 -06:00
|
|
|
mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-04 07:08:39 -06:00
|
|
|
static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
|
|
|
|
{
|
|
|
|
struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
|
|
|
|
|
|
|
|
switch (div_id) {
|
|
|
|
case 0: /* MCLK divider */
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
|
|
|
|
AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
|
|
|
|
AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case 1: /* BCLK divider */
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
|
|
|
|
ACLKXDIV(div - 1), ACLKXDIV_MASK);
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG,
|
|
|
|
ACLKRDIV(div - 1), ACLKRDIV_MASK);
|
|
|
|
break;
|
|
|
|
|
2012-12-05 10:20:38 -07:00
|
|
|
case 2: /* BCLK/LRCLK ratio */
|
|
|
|
dev->bclk_lrclk_ratio = div;
|
|
|
|
break;
|
|
|
|
|
2012-10-04 07:08:39 -06:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-04 07:08:41 -06:00
|
|
|
static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
|
|
|
|
unsigned int freq, int dir)
|
|
|
|
{
|
|
|
|
struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
|
|
|
|
|
|
|
|
if (dir == SND_SOC_CLOCK_OUT) {
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
|
|
|
|
} else {
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
static int davinci_config_channel_size(struct davinci_audio_dev *dev,
|
2012-12-05 10:20:37 -07:00
|
|
|
int word_length)
|
2009-06-05 04:28:40 -06:00
|
|
|
{
|
2012-12-05 10:20:37 -07:00
|
|
|
u32 fmt;
|
2013-05-16 07:25:01 -06:00
|
|
|
u32 tx_rotate = (word_length / 4) & 0x7;
|
|
|
|
u32 rx_rotate = (32 - word_length) / 4;
|
2012-12-05 10:20:37 -07:00
|
|
|
u32 mask = (1ULL << word_length) - 1;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
2012-12-05 10:20:38 -07:00
|
|
|
/*
|
|
|
|
* if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
|
|
|
|
* callback, take it into account here. That allows us to for example
|
|
|
|
* send 32 bits per channel to the codec, while only 16 of them carry
|
|
|
|
* audio payload.
|
2013-04-19 07:28:44 -06:00
|
|
|
* The clock ratio is given for a full period of data (for I2S format
|
|
|
|
* both left and right channels), so it has to be divided by number of
|
|
|
|
* tdm-slots (for I2S - divided by 2).
|
2012-12-05 10:20:38 -07:00
|
|
|
*/
|
|
|
|
if (dev->bclk_lrclk_ratio)
|
2013-04-19 07:28:44 -06:00
|
|
|
word_length = dev->bclk_lrclk_ratio / dev->tdm_slots;
|
2012-12-05 10:20:38 -07:00
|
|
|
|
2012-12-05 10:20:37 -07:00
|
|
|
/* mapping of the XSSZ bit-field as described in the datasheet */
|
|
|
|
fmt = (word_length >> 1) - 1;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
2013-04-04 08:13:20 -06:00
|
|
|
if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) {
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
|
|
|
|
RXSSZ(fmt), RXSSZ(0x0F));
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
|
|
|
|
TXSSZ(fmt), TXSSZ(0x0F));
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
|
2013-05-16 07:25:01 -06:00
|
|
|
TXROT(tx_rotate), TXROT(7));
|
2013-04-04 08:13:20 -06:00
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG,
|
2013-05-16 07:25:01 -06:00
|
|
|
RXROT(rx_rotate), RXROT(7));
|
2013-04-04 08:13:20 -06:00
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG,
|
|
|
|
mask);
|
|
|
|
}
|
|
|
|
|
2009-09-15 16:13:29 -06:00
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask);
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-02-28 08:07:08 -07:00
|
|
|
static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
|
|
|
|
int channels)
|
2009-06-05 04:28:40 -06:00
|
|
|
{
|
|
|
|
int i;
|
2009-08-11 14:58:52 -06:00
|
|
|
u8 tx_ser = 0;
|
|
|
|
u8 rx_ser = 0;
|
2013-02-28 08:07:08 -07:00
|
|
|
u8 ser;
|
|
|
|
u8 slots = dev->tdm_slots;
|
|
|
|
u8 max_active_serializers = (channels + slots - 1) / slots;
|
2009-06-05 04:28:40 -06:00
|
|
|
/* Default configuration */
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
|
|
|
|
|
|
|
|
/* All PINS as McASP */
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
|
|
|
|
|
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG,
|
|
|
|
TXDATADMADIS);
|
|
|
|
} else {
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG,
|
|
|
|
RXDATADMADIS);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < dev->num_serializer; i++) {
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
|
|
|
|
dev->serial_dir[i]);
|
2013-02-28 08:07:08 -07:00
|
|
|
if (dev->serial_dir[i] == TX_MODE &&
|
|
|
|
tx_ser < max_active_serializers) {
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
|
|
|
|
AXR(i));
|
2009-08-11 14:58:52 -06:00
|
|
|
tx_ser++;
|
2013-02-28 08:07:08 -07:00
|
|
|
} else if (dev->serial_dir[i] == RX_MODE &&
|
|
|
|
rx_ser < max_active_serializers) {
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG,
|
|
|
|
AXR(i));
|
2009-08-11 14:58:52 -06:00
|
|
|
rx_ser++;
|
2013-02-28 08:07:08 -07:00
|
|
|
} else {
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i),
|
|
|
|
SRMOD_INACTIVE, SRMOD_MASK);
|
2009-08-11 14:58:52 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-03-08 06:19:38 -07:00
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK)
|
|
|
|
ser = tx_ser;
|
|
|
|
else
|
|
|
|
ser = rx_ser;
|
|
|
|
|
|
|
|
if (ser < max_active_serializers) {
|
|
|
|
dev_warn(dev->dev, "stream has more channels (%d) than are "
|
|
|
|
"enabled in mcasp (%d)\n", channels, ser * slots);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2009-08-11 14:58:52 -06:00
|
|
|
if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
|
if (dev->txnumevt * tx_ser > 64)
|
|
|
|
dev->txnumevt = 1;
|
|
|
|
|
2012-09-03 02:10:40 -06:00
|
|
|
switch (dev->version) {
|
|
|
|
case MCASP_VERSION_3:
|
|
|
|
mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser,
|
2009-08-11 14:58:52 -06:00
|
|
|
NUMDMA_MASK);
|
2012-09-03 02:10:40 -06:00
|
|
|
mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL,
|
2009-08-11 14:58:52 -06:00
|
|
|
((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
|
2012-09-03 02:10:40 -06:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
|
|
|
|
tx_ser, NUMDMA_MASK);
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL,
|
|
|
|
((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK);
|
|
|
|
}
|
2009-08-11 14:58:52 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
|
|
|
|
if (dev->rxnumevt * rx_ser > 64)
|
|
|
|
dev->rxnumevt = 1;
|
2012-09-03 02:10:40 -06:00
|
|
|
switch (dev->version) {
|
|
|
|
case MCASP_VERSION_3:
|
|
|
|
mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser,
|
2009-08-11 14:58:52 -06:00
|
|
|
NUMDMA_MASK);
|
2012-09-03 02:10:40 -06:00
|
|
|
mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL,
|
|
|
|
((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
|
|
|
|
rx_ser, NUMDMA_MASK);
|
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL,
|
2009-08-11 14:58:52 -06:00
|
|
|
((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
|
2012-09-03 02:10:40 -06:00
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
}
|
2013-02-28 08:07:08 -07:00
|
|
|
|
|
|
|
return 0;
|
2009-06-05 04:28:40 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
|
|
|
|
{
|
|
|
|
int i, active_slots;
|
|
|
|
u32 mask = 0;
|
|
|
|
|
|
|
|
active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
|
|
|
|
for (i = 0; i < active_slots; i++)
|
|
|
|
mask |= (1 << i);
|
|
|
|
|
2009-08-11 14:58:52 -06:00
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
|
|
/* bit stream is MSB first with no delay */
|
|
|
|
/* DSP_B mode */
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask);
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
|
|
|
|
|
2011-04-21 12:19:01 -06:00
|
|
|
if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
|
|
|
|
FSXMOD(dev->tdm_slots), FSXMOD(0x1FF));
|
|
|
|
else
|
|
|
|
printk(KERN_ERR "playback tdm slot %d not supported\n",
|
|
|
|
dev->tdm_slots);
|
|
|
|
} else {
|
|
|
|
/* bit stream is MSB first with no delay */
|
|
|
|
/* DSP_B mode */
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask);
|
|
|
|
|
2011-04-21 12:19:01 -06:00
|
|
|
if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32))
|
2009-06-05 04:28:40 -06:00
|
|
|
mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG,
|
|
|
|
FSRMOD(dev->tdm_slots), FSRMOD(0x1FF));
|
|
|
|
else
|
|
|
|
printk(KERN_ERR "capture tdm slot %d not supported\n",
|
|
|
|
dev->tdm_slots);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* S/PDIF */
|
|
|
|
static void davinci_hw_dit_param(struct davinci_audio_dev *dev)
|
|
|
|
{
|
|
|
|
/* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
|
|
|
|
and LSB first */
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG,
|
|
|
|
TXROT(6) | TXSSZ(15));
|
|
|
|
|
|
|
|
/* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG,
|
|
|
|
AFSXE | FSXMOD(0x180));
|
|
|
|
|
|
|
|
/* Set the TX tdm : for all the slots */
|
|
|
|
mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
|
|
|
|
|
|
|
|
/* Set the TX clock controls : div = 1 and internal */
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG,
|
|
|
|
ACLKXE | TX_ASYNC);
|
|
|
|
|
|
|
|
mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
|
|
|
|
|
|
|
|
/* Only 44100 and 48000 are valid, both have the same setting */
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
|
|
|
|
|
|
|
|
/* Enable the DIT */
|
|
|
|
mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_pcm_hw_params *params,
|
|
|
|
struct snd_soc_dai *cpu_dai)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
|
2009-06-05 04:28:40 -06:00
|
|
|
struct davinci_pcm_dma_params *dma_params =
|
2009-09-11 15:29:03 -06:00
|
|
|
&dev->dma_params[substream->stream];
|
2009-06-05 04:28:40 -06:00
|
|
|
int word_length;
|
2009-09-30 15:32:27 -06:00
|
|
|
u8 fifo_level;
|
2013-02-28 08:07:08 -07:00
|
|
|
u8 slots = dev->tdm_slots;
|
2013-04-19 07:28:03 -06:00
|
|
|
u8 active_serializers;
|
2013-02-28 08:07:08 -07:00
|
|
|
int channels;
|
|
|
|
struct snd_interval *pcm_channels = hw_param_interval(params,
|
|
|
|
SNDRV_PCM_HW_PARAM_CHANNELS);
|
|
|
|
channels = pcm_channels->min;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
2013-04-19 07:28:03 -06:00
|
|
|
active_serializers = (channels + slots - 1) / slots;
|
|
|
|
|
2013-02-28 08:07:08 -07:00
|
|
|
if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL)
|
|
|
|
return -EINVAL;
|
2009-08-11 14:58:52 -06:00
|
|
|
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
|
2013-04-19 07:28:03 -06:00
|
|
|
fifo_level = dev->txnumevt * active_serializers;
|
2009-08-11 14:58:52 -06:00
|
|
|
else
|
2013-04-19 07:28:03 -06:00
|
|
|
fifo_level = dev->rxnumevt * active_serializers;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
|
|
|
if (dev->op_mode == DAVINCI_MCASP_DIT_MODE)
|
|
|
|
davinci_hw_dit_param(dev);
|
|
|
|
else
|
|
|
|
davinci_hw_param(dev, substream->stream);
|
|
|
|
|
|
|
|
switch (params_format(params)) {
|
2011-08-26 10:02:44 -06:00
|
|
|
case SNDRV_PCM_FORMAT_U8:
|
2009-06-05 04:28:40 -06:00
|
|
|
case SNDRV_PCM_FORMAT_S8:
|
|
|
|
dma_params->data_type = 1;
|
2012-12-05 10:20:37 -07:00
|
|
|
word_length = 8;
|
2009-06-05 04:28:40 -06:00
|
|
|
break;
|
|
|
|
|
2011-08-26 10:02:44 -06:00
|
|
|
case SNDRV_PCM_FORMAT_U16_LE:
|
2009-06-05 04:28:40 -06:00
|
|
|
case SNDRV_PCM_FORMAT_S16_LE:
|
|
|
|
dma_params->data_type = 2;
|
2012-12-05 10:20:37 -07:00
|
|
|
word_length = 16;
|
2009-06-05 04:28:40 -06:00
|
|
|
break;
|
|
|
|
|
2012-10-09 01:35:16 -06:00
|
|
|
case SNDRV_PCM_FORMAT_U24_3LE:
|
|
|
|
case SNDRV_PCM_FORMAT_S24_3LE:
|
|
|
|
dma_params->data_type = 3;
|
2012-12-05 10:20:37 -07:00
|
|
|
word_length = 24;
|
2012-10-09 01:35:16 -06:00
|
|
|
break;
|
|
|
|
|
2012-10-09 03:56:40 -06:00
|
|
|
case SNDRV_PCM_FORMAT_U24_LE:
|
|
|
|
case SNDRV_PCM_FORMAT_S24_LE:
|
2011-08-26 10:02:44 -06:00
|
|
|
case SNDRV_PCM_FORMAT_U32_LE:
|
2009-06-05 04:28:40 -06:00
|
|
|
case SNDRV_PCM_FORMAT_S32_LE:
|
|
|
|
dma_params->data_type = 4;
|
2012-12-05 10:20:37 -07:00
|
|
|
word_length = 32;
|
2009-06-05 04:28:40 -06:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2009-08-11 14:58:52 -06:00
|
|
|
|
2009-09-30 15:32:27 -06:00
|
|
|
if (dev->version == MCASP_VERSION_2 && !fifo_level)
|
|
|
|
dma_params->acnt = 4;
|
|
|
|
else
|
2009-08-11 14:58:52 -06:00
|
|
|
dma_params->acnt = dma_params->data_type;
|
|
|
|
|
2009-09-30 15:32:27 -06:00
|
|
|
dma_params->fifo_level = fifo_level;
|
2009-06-05 04:28:40 -06:00
|
|
|
davinci_config_channel_size(dev, word_length);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
|
|
|
|
int cmd, struct snd_soc_dai *cpu_dai)
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
|
2009-06-05 04:28:40 -06:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
switch (cmd) {
|
|
|
|
case SNDRV_PCM_TRIGGER_RESUME:
|
2010-01-20 04:36:33 -07:00
|
|
|
case SNDRV_PCM_TRIGGER_START:
|
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
|
2012-08-08 09:10:32 -06:00
|
|
|
ret = pm_runtime_get_sync(dev->dev);
|
|
|
|
if (IS_ERR_VALUE(ret))
|
|
|
|
dev_err(dev->dev, "pm_runtime_get_sync() failed\n");
|
2009-06-05 04:28:40 -06:00
|
|
|
davinci_mcasp_start(dev, substream->stream);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_SUSPEND:
|
2009-12-03 06:26:56 -07:00
|
|
|
davinci_mcasp_stop(dev, substream->stream);
|
2012-08-08 09:10:32 -06:00
|
|
|
ret = pm_runtime_put_sync(dev->dev);
|
|
|
|
if (IS_ERR_VALUE(ret))
|
|
|
|
dev_err(dev->dev, "pm_runtime_put_sync() failed\n");
|
2009-12-03 06:26:56 -07:00
|
|
|
break;
|
|
|
|
|
|
|
|
case SNDRV_PCM_TRIGGER_STOP:
|
2009-06-05 04:28:40 -06:00
|
|
|
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
|
|
|
|
davinci_mcasp_stop(dev, substream->stream);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
ASoC: davinci: fixes for multi-component
Multi-component commit f0fba2ad broke a few things which this patch should
fix. Tested on the DM355 EVM. I've been as careful as I can, but it would be
good if those with access to other Davinci boards could test.
--
The multi-component commit put the initialisation of
snd_soc_dai.[capture|playback]_dma_data into snd_soc_dai_ops.hw_params of the
McBSP, McASP & VCIF drivers (davinci-i2s.c, davinci-mcasp.c & davinci-vcif.c).
The initialisation had to be moved from the probe function in these drivers
because davinci_*_dai changed from snd_soc_dai to snd_soc_dai_driver.
Unfortunately, the DMA params pointer is needed by davinci_pcm_open (in
davinci-pcm.c) before hw_params is called. I have moved the initialisation to
a new snd_soc_dai_ops.startup function in each of these drivers. This fix
indicates that all platforms that use davinci-pcm must have been broken and
need to test with this fix.
--
The multi-component commit also changed the McBSP driver name from
"davinci-asp" to "davinci-i2s" in davinci-i2s.c without updating the board
level references to the driver name. This change is understandable, as there
is a similarly named "davinci-mcasp" driver in davinci-mcasp.c.
There is probably no 'correct' name for this driver. The DM6446 datasheet
calls it the "ASP" and describes it as a "specialised McBSP". The DM355
datasheet calls it the "ASP" and describes it as a "specialised ASP". The
DM365 datasheet calls it the "McBSP". Rather than fix this problem by
reverting to "davinci-asp", I've elected to avoid future confusion with the
"davinci-mcasp" driver by changing it to "davinci-mcbsp", which is also
consistent with the names of the functions in the driver. There are other
fixes required, so it was never going to be as simple as a revert anyway.
--
The DM365 only has one McBSP port (of the McBSP platforms, only the DM355 has
2 ports), so I've changed the the id of the platform_device from 0 to -1.
--
In davinci-evm.c, the DM6446 EVM can no longer share a snd_soc_dai_link
structure with the DM355 EVM as they use different cpu DAI names (the DM355
has 2 ports and the EVM uses the second port, but the DM6446 only has 1 port).
This also means that the 2 boards need different snd_soc_card structures.
--
The codec_name entries in davinci-evm.c didn't match the i2c ids in the board
files. I have only checked and fixed the details of the names used for the
McBSP based platforms. Someone with a McASP based platform (eg DA8xx) should
check the others.
Signed-off-by: Chris Paulson-Ellis <chris@edesix.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-11-16 05:27:09 -07:00
|
|
|
static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
|
|
|
|
struct snd_soc_dai *dai)
|
|
|
|
{
|
|
|
|
struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai);
|
|
|
|
|
|
|
|
snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-23 03:40:40 -07:00
|
|
|
static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
|
ASoC: davinci: fixes for multi-component
Multi-component commit f0fba2ad broke a few things which this patch should
fix. Tested on the DM355 EVM. I've been as careful as I can, but it would be
good if those with access to other Davinci boards could test.
--
The multi-component commit put the initialisation of
snd_soc_dai.[capture|playback]_dma_data into snd_soc_dai_ops.hw_params of the
McBSP, McASP & VCIF drivers (davinci-i2s.c, davinci-mcasp.c & davinci-vcif.c).
The initialisation had to be moved from the probe function in these drivers
because davinci_*_dai changed from snd_soc_dai to snd_soc_dai_driver.
Unfortunately, the DMA params pointer is needed by davinci_pcm_open (in
davinci-pcm.c) before hw_params is called. I have moved the initialisation to
a new snd_soc_dai_ops.startup function in each of these drivers. This fix
indicates that all platforms that use davinci-pcm must have been broken and
need to test with this fix.
--
The multi-component commit also changed the McBSP driver name from
"davinci-asp" to "davinci-i2s" in davinci-i2s.c without updating the board
level references to the driver name. This change is understandable, as there
is a similarly named "davinci-mcasp" driver in davinci-mcasp.c.
There is probably no 'correct' name for this driver. The DM6446 datasheet
calls it the "ASP" and describes it as a "specialised McBSP". The DM355
datasheet calls it the "ASP" and describes it as a "specialised ASP". The
DM365 datasheet calls it the "McBSP". Rather than fix this problem by
reverting to "davinci-asp", I've elected to avoid future confusion with the
"davinci-mcasp" driver by changing it to "davinci-mcbsp", which is also
consistent with the names of the functions in the driver. There are other
fixes required, so it was never going to be as simple as a revert anyway.
--
The DM365 only has one McBSP port (of the McBSP platforms, only the DM355 has
2 ports), so I've changed the the id of the platform_device from 0 to -1.
--
In davinci-evm.c, the DM6446 EVM can no longer share a snd_soc_dai_link
structure with the DM355 EVM as they use different cpu DAI names (the DM355
has 2 ports and the EVM uses the second port, but the DM6446 only has 1 port).
This also means that the 2 boards need different snd_soc_card structures.
--
The codec_name entries in davinci-evm.c didn't match the i2c ids in the board
files. I have only checked and fixed the details of the names used for the
McBSP based platforms. Someone with a McASP based platform (eg DA8xx) should
check the others.
Signed-off-by: Chris Paulson-Ellis <chris@edesix.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2010-11-16 05:27:09 -07:00
|
|
|
.startup = davinci_mcasp_startup,
|
2009-06-05 04:28:40 -06:00
|
|
|
.trigger = davinci_mcasp_trigger,
|
|
|
|
.hw_params = davinci_mcasp_hw_params,
|
|
|
|
.set_fmt = davinci_mcasp_set_dai_fmt,
|
2012-10-04 07:08:39 -06:00
|
|
|
.set_clkdiv = davinci_mcasp_set_clkdiv,
|
2012-10-04 07:08:41 -06:00
|
|
|
.set_sysclk = davinci_mcasp_set_sysclk,
|
2009-06-05 04:28:40 -06:00
|
|
|
};
|
|
|
|
|
2011-08-26 10:02:44 -06:00
|
|
|
#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
|
|
|
|
SNDRV_PCM_FMTBIT_U8 | \
|
|
|
|
SNDRV_PCM_FMTBIT_S16_LE | \
|
|
|
|
SNDRV_PCM_FMTBIT_U16_LE | \
|
2012-10-09 01:35:16 -06:00
|
|
|
SNDRV_PCM_FMTBIT_S24_LE | \
|
|
|
|
SNDRV_PCM_FMTBIT_U24_LE | \
|
|
|
|
SNDRV_PCM_FMTBIT_S24_3LE | \
|
|
|
|
SNDRV_PCM_FMTBIT_U24_3LE | \
|
2011-08-26 10:02:44 -06:00
|
|
|
SNDRV_PCM_FMTBIT_S32_LE | \
|
|
|
|
SNDRV_PCM_FMTBIT_U32_LE)
|
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
|
2009-06-05 04:28:40 -06:00
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
.name = "davinci-mcasp.0",
|
2009-06-05 04:28:40 -06:00
|
|
|
.playback = {
|
|
|
|
.channels_min = 2,
|
2013-02-28 08:07:08 -07:00
|
|
|
.channels_max = 32 * 16,
|
2009-06-05 04:28:40 -06:00
|
|
|
.rates = DAVINCI_MCASP_RATES,
|
2011-08-26 10:02:44 -06:00
|
|
|
.formats = DAVINCI_MCASP_PCM_FMTS,
|
2009-06-05 04:28:40 -06:00
|
|
|
},
|
|
|
|
.capture = {
|
|
|
|
.channels_min = 2,
|
2013-02-28 08:07:08 -07:00
|
|
|
.channels_max = 32 * 16,
|
2009-06-05 04:28:40 -06:00
|
|
|
.rates = DAVINCI_MCASP_RATES,
|
2011-08-26 10:02:44 -06:00
|
|
|
.formats = DAVINCI_MCASP_PCM_FMTS,
|
2009-06-05 04:28:40 -06:00
|
|
|
},
|
|
|
|
.ops = &davinci_mcasp_dai_ops,
|
|
|
|
|
|
|
|
},
|
|
|
|
{
|
2010-03-17 14:15:21 -06:00
|
|
|
"davinci-mcasp.1",
|
2009-06-05 04:28:40 -06:00
|
|
|
.playback = {
|
|
|
|
.channels_min = 1,
|
|
|
|
.channels_max = 384,
|
|
|
|
.rates = DAVINCI_MCASP_RATES,
|
2011-08-26 10:02:44 -06:00
|
|
|
.formats = DAVINCI_MCASP_PCM_FMTS,
|
2009-06-05 04:28:40 -06:00
|
|
|
},
|
|
|
|
.ops = &davinci_mcasp_dai_ops,
|
|
|
|
},
|
|
|
|
|
|
|
|
};
|
|
|
|
|
2013-03-21 04:31:19 -06:00
|
|
|
static const struct snd_soc_component_driver davinci_mcasp_component = {
|
|
|
|
.name = "davinci-mcasp",
|
|
|
|
};
|
|
|
|
|
2013-10-18 09:37:42 -06:00
|
|
|
/* Some HW specific values and defaults. The rest is filled in from DT. */
|
|
|
|
static struct snd_platform_data dm646x_mcasp_pdata = {
|
|
|
|
.tx_dma_offset = 0x400,
|
|
|
|
.rx_dma_offset = 0x400,
|
|
|
|
.asp_chan_q = EVENTQ_0,
|
|
|
|
.version = MCASP_VERSION_1,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct snd_platform_data da830_mcasp_pdata = {
|
|
|
|
.tx_dma_offset = 0x2000,
|
|
|
|
.rx_dma_offset = 0x2000,
|
|
|
|
.asp_chan_q = EVENTQ_0,
|
|
|
|
.version = MCASP_VERSION_2,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct snd_platform_data omap2_mcasp_pdata = {
|
|
|
|
.tx_dma_offset = 0,
|
|
|
|
.rx_dma_offset = 0,
|
|
|
|
.asp_chan_q = EVENTQ_0,
|
|
|
|
.version = MCASP_VERSION_3,
|
|
|
|
};
|
|
|
|
|
2012-08-27 07:26:42 -06:00
|
|
|
static const struct of_device_id mcasp_dt_ids[] = {
|
|
|
|
{
|
|
|
|
.compatible = "ti,dm646x-mcasp-audio",
|
2013-10-18 09:37:42 -06:00
|
|
|
.data = &dm646x_mcasp_pdata,
|
2012-08-27 07:26:42 -06:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "ti,da830-mcasp-audio",
|
2013-10-18 09:37:42 -06:00
|
|
|
.data = &da830_mcasp_pdata,
|
2012-08-27 07:26:42 -06:00
|
|
|
},
|
2012-09-03 02:10:40 -06:00
|
|
|
{
|
|
|
|
.compatible = "ti,omap2-mcasp-audio",
|
2013-10-18 09:37:42 -06:00
|
|
|
.data = &omap2_mcasp_pdata,
|
2012-09-03 02:10:40 -06:00
|
|
|
},
|
2012-08-27 07:26:42 -06:00
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
|
|
|
|
|
|
|
|
static struct snd_platform_data *davinci_mcasp_set_pdata_from_of(
|
|
|
|
struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
struct snd_platform_data *pdata = NULL;
|
|
|
|
const struct of_device_id *match =
|
2013-05-22 05:23:37 -06:00
|
|
|
of_match_device(mcasp_dt_ids, &pdev->dev);
|
2013-10-18 09:37:43 -06:00
|
|
|
struct of_phandle_args dma_spec;
|
2012-08-27 07:26:42 -06:00
|
|
|
|
|
|
|
const u32 *of_serial_dir32;
|
|
|
|
u8 *of_serial_dir;
|
|
|
|
u32 val;
|
|
|
|
int i, ret = 0;
|
|
|
|
|
|
|
|
if (pdev->dev.platform_data) {
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
|
|
return pdata;
|
|
|
|
} else if (match) {
|
2013-10-18 09:37:42 -06:00
|
|
|
pdata = (struct snd_platform_data *) match->data;
|
2012-08-27 07:26:42 -06:00
|
|
|
} else {
|
|
|
|
/* control shouldn't reach here. something is wrong */
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto nodata;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "op-mode", &val);
|
|
|
|
if (ret >= 0)
|
|
|
|
pdata->op_mode = val;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "tdm-slots", &val);
|
2013-02-28 08:07:08 -07:00
|
|
|
if (ret >= 0) {
|
|
|
|
if (val < 2 || val > 32) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"tdm-slots must be in rage [2-32]\n");
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto nodata;
|
|
|
|
}
|
|
|
|
|
2012-08-27 07:26:42 -06:00
|
|
|
pdata->tdm_slots = val;
|
2013-02-28 08:07:08 -07:00
|
|
|
}
|
2012-08-27 07:26:42 -06:00
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "num-serializer", &val);
|
|
|
|
if (ret >= 0)
|
|
|
|
pdata->num_serializer = val;
|
|
|
|
|
|
|
|
of_serial_dir32 = of_get_property(np, "serial-dir", &val);
|
|
|
|
val /= sizeof(u32);
|
|
|
|
if (val != pdata->num_serializer) {
|
|
|
|
dev_err(&pdev->dev,
|
|
|
|
"num-serializer(%d) != serial-dir size(%d)\n",
|
|
|
|
pdata->num_serializer, val);
|
|
|
|
ret = -EINVAL;
|
|
|
|
goto nodata;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_serial_dir32) {
|
|
|
|
of_serial_dir = devm_kzalloc(&pdev->dev,
|
|
|
|
(sizeof(*of_serial_dir) * val),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!of_serial_dir) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto nodata;
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < pdata->num_serializer; i++)
|
|
|
|
of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
|
|
|
|
|
|
|
|
pdata->serial_dir = of_serial_dir;
|
|
|
|
}
|
|
|
|
|
2013-10-18 09:37:43 -06:00
|
|
|
ret = of_property_match_string(np, "dma-names", "tx");
|
|
|
|
if (ret < 0)
|
|
|
|
goto nodata;
|
|
|
|
|
|
|
|
ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
|
|
|
|
&dma_spec);
|
|
|
|
if (ret < 0)
|
|
|
|
goto nodata;
|
|
|
|
|
|
|
|
pdata->tx_dma_channel = dma_spec.args[0];
|
|
|
|
|
|
|
|
ret = of_property_match_string(np, "dma-names", "rx");
|
|
|
|
if (ret < 0)
|
|
|
|
goto nodata;
|
|
|
|
|
|
|
|
ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
|
|
|
|
&dma_spec);
|
|
|
|
if (ret < 0)
|
|
|
|
goto nodata;
|
|
|
|
|
|
|
|
pdata->rx_dma_channel = dma_spec.args[0];
|
|
|
|
|
2012-08-27 07:26:42 -06:00
|
|
|
ret = of_property_read_u32(np, "tx-num-evt", &val);
|
|
|
|
if (ret >= 0)
|
|
|
|
pdata->txnumevt = val;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "rx-num-evt", &val);
|
|
|
|
if (ret >= 0)
|
|
|
|
pdata->rxnumevt = val;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "sram-size-playback", &val);
|
|
|
|
if (ret >= 0)
|
|
|
|
pdata->sram_size_playback = val;
|
|
|
|
|
|
|
|
ret = of_property_read_u32(np, "sram-size-capture", &val);
|
|
|
|
if (ret >= 0)
|
|
|
|
pdata->sram_size_capture = val;
|
|
|
|
|
|
|
|
return pdata;
|
|
|
|
|
|
|
|
nodata:
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_err(&pdev->dev, "Error populating platform data, err %d\n",
|
|
|
|
ret);
|
|
|
|
pdata = NULL;
|
|
|
|
}
|
|
|
|
return pdata;
|
|
|
|
}
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
static int davinci_mcasp_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct davinci_pcm_dma_params *dma_data;
|
2013-10-18 09:37:42 -06:00
|
|
|
struct resource *mem, *ioarea, *res, *dat;
|
2009-06-05 04:28:40 -06:00
|
|
|
struct snd_platform_data *pdata;
|
|
|
|
struct davinci_audio_dev *dev;
|
2011-12-29 09:51:21 -07:00
|
|
|
int ret;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
2012-08-27 07:26:42 -06:00
|
|
|
if (!pdev->dev.platform_data && !pdev->dev.of_node) {
|
|
|
|
dev_err(&pdev->dev, "No platform data supplied\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2011-12-29 09:51:21 -07:00
|
|
|
dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev),
|
|
|
|
GFP_KERNEL);
|
2009-06-05 04:28:40 -06:00
|
|
|
if (!dev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2012-08-27 07:26:42 -06:00
|
|
|
pdata = davinci_mcasp_set_pdata_from_of(pdev);
|
|
|
|
if (!pdata) {
|
|
|
|
dev_err(&pdev->dev, "no platform data\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2013-10-18 09:37:42 -06:00
|
|
|
mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
|
2009-06-05 04:28:40 -06:00
|
|
|
if (!mem) {
|
2013-10-18 09:37:42 -06:00
|
|
|
dev_warn(dev->dev,
|
|
|
|
"\"mpu\" mem resource not found, using index 0\n");
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!mem) {
|
|
|
|
dev_err(&pdev->dev, "no mem resource?\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
}
|
|
|
|
|
2011-12-29 09:51:21 -07:00
|
|
|
ioarea = devm_request_mem_region(&pdev->dev, mem->start,
|
2011-02-09 06:09:52 -07:00
|
|
|
resource_size(mem), pdev->name);
|
2009-06-05 04:28:40 -06:00
|
|
|
if (!ioarea) {
|
|
|
|
dev_err(&pdev->dev, "Audio region already claimed\n");
|
2011-12-29 09:51:21 -07:00
|
|
|
return -EBUSY;
|
2009-06-05 04:28:40 -06:00
|
|
|
}
|
|
|
|
|
2012-08-08 09:10:32 -06:00
|
|
|
pm_runtime_enable(&pdev->dev);
|
2009-06-05 04:28:40 -06:00
|
|
|
|
2012-08-08 09:10:32 -06:00
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
|
|
if (IS_ERR_VALUE(ret)) {
|
|
|
|
dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
|
|
|
|
return ret;
|
|
|
|
}
|
2009-06-05 04:28:40 -06:00
|
|
|
|
2011-12-29 09:51:21 -07:00
|
|
|
dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
|
2011-02-09 06:09:54 -07:00
|
|
|
if (!dev->base) {
|
|
|
|
dev_err(&pdev->dev, "ioremap failed\n");
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err_release_clk;
|
|
|
|
}
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
dev->op_mode = pdata->op_mode;
|
|
|
|
dev->tdm_slots = pdata->tdm_slots;
|
|
|
|
dev->num_serializer = pdata->num_serializer;
|
|
|
|
dev->serial_dir = pdata->serial_dir;
|
2009-08-11 14:58:52 -06:00
|
|
|
dev->version = pdata->version;
|
|
|
|
dev->txnumevt = pdata->txnumevt;
|
|
|
|
dev->rxnumevt = pdata->rxnumevt;
|
2012-08-08 09:10:32 -06:00
|
|
|
dev->dev = &pdev->dev;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
2013-10-18 09:37:42 -06:00
|
|
|
dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
|
|
|
|
if (!dat)
|
|
|
|
dat = mem;
|
|
|
|
|
2009-09-11 15:29:03 -06:00
|
|
|
dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
|
2010-07-19 01:01:16 -06:00
|
|
|
dma_data->asp_chan_q = pdata->asp_chan_q;
|
|
|
|
dma_data->ram_chan_q = pdata->ram_chan_q;
|
2012-10-17 08:08:03 -06:00
|
|
|
dma_data->sram_pool = pdata->sram_pool;
|
2011-05-18 07:27:45 -06:00
|
|
|
dma_data->sram_size = pdata->sram_size_playback;
|
2013-10-18 09:37:42 -06:00
|
|
|
dma_data->dma_addr = dat->start + pdata->tx_dma_offset;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
|
2013-10-18 09:37:43 -06:00
|
|
|
if (res)
|
|
|
|
dma_data->channel = res->start;
|
|
|
|
else
|
|
|
|
dma_data->channel = pdata->tx_dma_channel;
|
2009-09-11 15:29:03 -06:00
|
|
|
|
|
|
|
dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE];
|
2010-07-19 01:01:16 -06:00
|
|
|
dma_data->asp_chan_q = pdata->asp_chan_q;
|
|
|
|
dma_data->ram_chan_q = pdata->ram_chan_q;
|
2012-10-17 08:08:03 -06:00
|
|
|
dma_data->sram_pool = pdata->sram_pool;
|
2011-05-18 07:27:45 -06:00
|
|
|
dma_data->sram_size = pdata->sram_size_capture;
|
2013-10-18 09:37:42 -06:00
|
|
|
dma_data->dma_addr = dat->start + pdata->rx_dma_offset;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
|
2013-10-18 09:37:43 -06:00
|
|
|
if (res)
|
|
|
|
dma_data->channel = res->start;
|
|
|
|
else
|
|
|
|
dma_data->channel = pdata->rx_dma_channel;
|
2009-06-05 04:28:40 -06:00
|
|
|
|
2010-03-17 14:15:21 -06:00
|
|
|
dev_set_drvdata(&pdev->dev, dev);
|
2013-03-21 04:31:19 -06:00
|
|
|
ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
|
|
|
|
&davinci_mcasp_dai[pdata->op_mode], 1);
|
2009-06-05 04:28:40 -06:00
|
|
|
|
|
|
|
if (ret != 0)
|
2011-12-29 09:51:21 -07:00
|
|
|
goto err_release_clk;
|
2012-08-27 07:26:39 -06:00
|
|
|
|
|
|
|
ret = davinci_soc_platform_register(&pdev->dev);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
|
2013-03-21 04:31:19 -06:00
|
|
|
goto err_unregister_component;
|
2012-08-27 07:26:39 -06:00
|
|
|
}
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
return 0;
|
|
|
|
|
2013-03-21 04:31:19 -06:00
|
|
|
err_unregister_component:
|
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
2011-02-09 06:09:53 -07:00
|
|
|
err_release_clk:
|
2012-08-08 09:10:32 -06:00
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2009-06-05 04:28:40 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int davinci_mcasp_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
|
2013-03-21 04:31:19 -06:00
|
|
|
snd_soc_unregister_component(&pdev->dev);
|
2012-08-27 07:26:39 -06:00
|
|
|
davinci_soc_platform_unregister(&pdev->dev);
|
2012-08-08 09:10:32 -06:00
|
|
|
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2009-06-05 04:28:40 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-10-01 06:50:02 -06:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
static int davinci_mcasp_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct davinci_audio_dev *a = dev_get_drvdata(dev);
|
|
|
|
void __iomem *base = a->base;
|
|
|
|
|
|
|
|
a->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG);
|
|
|
|
a->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG);
|
|
|
|
a->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG);
|
|
|
|
a->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG);
|
|
|
|
a->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG);
|
|
|
|
a->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG);
|
|
|
|
a->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int davinci_mcasp_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct davinci_audio_dev *a = dev_get_drvdata(dev);
|
|
|
|
void __iomem *base = a->base;
|
|
|
|
|
|
|
|
mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, a->context.txfmtctl);
|
|
|
|
mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, a->context.rxfmtctl);
|
|
|
|
mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, a->context.txfmt);
|
|
|
|
mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, a->context.rxfmt);
|
|
|
|
mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, a->context.aclkxctl);
|
|
|
|
mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, a->context.aclkrctl);
|
|
|
|
mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, a->context.pdir);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
SIMPLE_DEV_PM_OPS(davinci_mcasp_pm_ops,
|
|
|
|
davinci_mcasp_suspend,
|
|
|
|
davinci_mcasp_resume);
|
|
|
|
|
2009-06-05 04:28:40 -06:00
|
|
|
static struct platform_driver davinci_mcasp_driver = {
|
|
|
|
.probe = davinci_mcasp_probe,
|
|
|
|
.remove = davinci_mcasp_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "davinci-mcasp",
|
|
|
|
.owner = THIS_MODULE,
|
2013-10-01 06:50:02 -06:00
|
|
|
.pm = &davinci_mcasp_pm_ops,
|
2013-05-22 05:23:37 -06:00
|
|
|
.of_match_table = mcasp_dt_ids,
|
2009-06-05 04:28:40 -06:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2011-11-24 19:09:27 -07:00
|
|
|
module_platform_driver(davinci_mcasp_driver);
|
2009-06-05 04:28:40 -06:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Steve Chen");
|
|
|
|
MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
|
|
|
|
MODULE_LICENSE("GPL");
|