License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 08:07:57 -06:00
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// SPDX-License-Identifier: GPL-2.0
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2016-06-29 08:01:51 -06:00
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/* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */
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2016-02-10 02:55:17 -07:00
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#include "uncore.h"
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2014-07-30 01:22:13 -06:00
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2015-04-21 13:33:11 -06:00
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/* Uncore IMC PCI IDs */
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2019-05-10 18:03:10 -06:00
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#define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
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#define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
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#define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150
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#define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
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#define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04
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#define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604
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#define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904
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#define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c
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#define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900
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#define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910
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#define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f
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#define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f
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2020-01-10 13:15:11 -07:00
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#define PCI_DEVICE_ID_INTEL_SKL_E3_IMC 0x1918
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2019-05-10 18:03:10 -06:00
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#define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c
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#define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904
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#define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914
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#define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f
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#define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f
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2019-05-10 18:03:11 -06:00
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#define PCI_DEVICE_ID_INTEL_KBL_HQ_IMC 0x5910
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#define PCI_DEVICE_ID_INTEL_KBL_WQ_IMC 0x5918
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2019-05-10 18:03:10 -06:00
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#define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc
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#define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0
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#define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10
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#define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4
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2018-10-19 11:04:18 -06:00
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#define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC 0x3e0f
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#define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC 0x3e1f
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#define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC 0x3ec2
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#define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC 0x3e30
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#define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC 0x3e18
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#define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC 0x3ec6
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#define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC 0x3e31
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#define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC 0x3e33
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#define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC 0x3eca
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#define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC 0x3e32
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2019-05-10 18:03:11 -06:00
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#define PCI_DEVICE_ID_INTEL_AML_YD_IMC 0x590c
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#define PCI_DEVICE_ID_INTEL_AML_YQ_IMC 0x590d
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#define PCI_DEVICE_ID_INTEL_WHL_UQ_IMC 0x3ed0
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#define PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC 0x3e34
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#define PCI_DEVICE_ID_INTEL_WHL_UD_IMC 0x3e35
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2019-04-02 13:45:09 -06:00
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#define PCI_DEVICE_ID_INTEL_ICL_U_IMC 0x8a02
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#define PCI_DEVICE_ID_INTEL_ICL_U2_IMC 0x8a12
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2015-04-20 16:34:07 -06:00
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2019-05-10 18:03:11 -06:00
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2014-07-30 01:22:13 -06:00
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/* SNB event control */
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#define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff
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#define SNB_UNC_CTL_UMASK_MASK 0x0000ff00
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#define SNB_UNC_CTL_EDGE_DET (1 << 18)
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#define SNB_UNC_CTL_EN (1 << 22)
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#define SNB_UNC_CTL_INVERT (1 << 23)
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#define SNB_UNC_CTL_CMASK_MASK 0x1f000000
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#define NHM_UNC_CTL_CMASK_MASK 0xff000000
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#define NHM_UNC_FIXED_CTR_CTL_EN (1 << 0)
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#define SNB_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \
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SNB_UNC_CTL_UMASK_MASK | \
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SNB_UNC_CTL_EDGE_DET | \
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SNB_UNC_CTL_INVERT | \
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SNB_UNC_CTL_CMASK_MASK)
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#define NHM_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \
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SNB_UNC_CTL_UMASK_MASK | \
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SNB_UNC_CTL_EDGE_DET | \
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SNB_UNC_CTL_INVERT | \
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NHM_UNC_CTL_CMASK_MASK)
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/* SNB global control register */
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#define SNB_UNC_PERF_GLOBAL_CTL 0x391
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#define SNB_UNC_FIXED_CTR_CTRL 0x394
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#define SNB_UNC_FIXED_CTR 0x395
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/* SNB uncore global control */
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#define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1)
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#define SNB_UNC_GLOBAL_CTL_EN (1 << 29)
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/* SNB Cbo register */
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#define SNB_UNC_CBO_0_PERFEVTSEL0 0x700
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#define SNB_UNC_CBO_0_PER_CTR0 0x706
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#define SNB_UNC_CBO_MSR_OFFSET 0x10
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2015-06-14 23:57:40 -06:00
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/* SNB ARB register */
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#define SNB_UNC_ARB_PER_CTR0 0x3b0
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#define SNB_UNC_ARB_PERFEVTSEL0 0x3b2
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#define SNB_UNC_ARB_MSR_OFFSET 0x10
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2014-07-30 01:22:13 -06:00
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/* NHM global control register */
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#define NHM_UNC_PERF_GLOBAL_CTL 0x391
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#define NHM_UNC_FIXED_CTR 0x394
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#define NHM_UNC_FIXED_CTR_CTRL 0x395
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/* NHM uncore global control */
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#define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1)
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#define NHM_UNC_GLOBAL_CTL_EN_FC (1ULL << 32)
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/* NHM uncore register */
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#define NHM_UNC_PERFEVTSEL0 0x3c0
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#define NHM_UNC_UNCORE_PMC0 0x3b0
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2016-06-29 08:01:51 -06:00
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/* SKL uncore global control */
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#define SKL_UNC_PERF_GLOBAL_CTL 0xe01
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#define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1)
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2019-04-02 13:45:09 -06:00
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/* ICL Cbo register */
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#define ICL_UNC_CBO_CONFIG 0x396
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#define ICL_UNC_NUM_CBO_MASK 0xf
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#define ICL_UNC_CBO_0_PER_CTR0 0x702
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#define ICL_UNC_CBO_MSR_OFFSET 0x8
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2020-09-25 07:49:04 -06:00
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/* ICL ARB register */
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#define ICL_UNC_ARB_PER_CTR 0x3b1
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#define ICL_UNC_ARB_PERFEVTSEL 0x3b3
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2014-07-30 01:22:13 -06:00
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DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
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DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
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DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
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DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
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DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
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/* Sandy Bridge uncore support */
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static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (hwc->idx < UNCORE_PMC_IDX_FIXED)
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wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
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else
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wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
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}
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static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
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{
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wrmsrl(event->hw.config_base, 0);
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}
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static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
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{
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if (box->pmu->pmu_idx == 0) {
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wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
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SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
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}
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}
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2016-08-11 08:31:14 -06:00
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static void snb_uncore_msr_enable_box(struct intel_uncore_box *box)
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{
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wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
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SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
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}
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2016-02-22 15:19:11 -07:00
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static void snb_uncore_msr_exit_box(struct intel_uncore_box *box)
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{
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if (box->pmu->pmu_idx == 0)
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wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0);
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}
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2014-07-30 01:22:13 -06:00
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static struct uncore_event_desc snb_uncore_events[] = {
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INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
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{ /* end: all zeroes */ },
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};
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static struct attribute *snb_uncore_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
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&format_attr_inv.attr,
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&format_attr_cmask5.attr,
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NULL,
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};
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2017-07-20 05:30:32 -06:00
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static const struct attribute_group snb_uncore_format_group = {
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2014-07-30 01:22:13 -06:00
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.name = "format",
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.attrs = snb_uncore_formats_attr,
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};
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static struct intel_uncore_ops snb_uncore_msr_ops = {
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.init_box = snb_uncore_msr_init_box,
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2016-08-11 08:31:14 -06:00
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.enable_box = snb_uncore_msr_enable_box,
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2016-02-22 15:19:11 -07:00
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.exit_box = snb_uncore_msr_exit_box,
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2014-07-30 01:22:13 -06:00
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.disable_event = snb_uncore_msr_disable_event,
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.enable_event = snb_uncore_msr_enable_event,
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.read_counter = uncore_msr_read_counter,
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};
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2015-06-14 23:57:40 -06:00
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static struct event_constraint snb_uncore_arb_constraints[] = {
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2014-07-30 01:22:13 -06:00
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UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
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UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
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EVENT_CONSTRAINT_END
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};
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static struct intel_uncore_type snb_uncore_cbox = {
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|
.name = "cbox",
|
|
|
|
|
.num_counters = 2,
|
|
|
|
|
.num_boxes = 4,
|
|
|
|
|
.perf_ctr_bits = 44,
|
|
|
|
|
.fixed_ctr_bits = 48,
|
|
|
|
|
.perf_ctr = SNB_UNC_CBO_0_PER_CTR0,
|
|
|
|
|
.event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
|
|
|
|
|
.fixed_ctr = SNB_UNC_FIXED_CTR,
|
|
|
|
|
.fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
|
|
|
|
|
.single_fixed = 1,
|
|
|
|
|
.event_mask = SNB_UNC_RAW_EVENT_MASK,
|
|
|
|
|
.msr_offset = SNB_UNC_CBO_MSR_OFFSET,
|
|
|
|
|
.ops = &snb_uncore_msr_ops,
|
|
|
|
|
.format_group = &snb_uncore_format_group,
|
|
|
|
|
.event_descs = snb_uncore_events,
|
|
|
|
|
};
|
|
|
|
|
|
2015-06-14 23:57:40 -06:00
|
|
|
static struct intel_uncore_type snb_uncore_arb = {
|
|
|
|
|
.name = "arb",
|
|
|
|
|
.num_counters = 2,
|
|
|
|
|
.num_boxes = 1,
|
|
|
|
|
.perf_ctr_bits = 44,
|
|
|
|
|
.perf_ctr = SNB_UNC_ARB_PER_CTR0,
|
|
|
|
|
.event_ctl = SNB_UNC_ARB_PERFEVTSEL0,
|
|
|
|
|
.event_mask = SNB_UNC_RAW_EVENT_MASK,
|
|
|
|
|
.msr_offset = SNB_UNC_ARB_MSR_OFFSET,
|
|
|
|
|
.constraints = snb_uncore_arb_constraints,
|
|
|
|
|
.ops = &snb_uncore_msr_ops,
|
|
|
|
|
.format_group = &snb_uncore_format_group,
|
|
|
|
|
};
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
static struct intel_uncore_type *snb_msr_uncores[] = {
|
|
|
|
|
&snb_uncore_cbox,
|
2015-06-14 23:57:40 -06:00
|
|
|
&snb_uncore_arb,
|
2014-07-30 01:22:13 -06:00
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void snb_uncore_cpu_init(void)
|
|
|
|
|
{
|
|
|
|
|
uncore_msr_uncores = snb_msr_uncores;
|
|
|
|
|
if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
|
|
|
|
|
snb_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-29 08:01:51 -06:00
|
|
|
static void skl_uncore_msr_init_box(struct intel_uncore_box *box)
|
|
|
|
|
{
|
|
|
|
|
if (box->pmu->pmu_idx == 0) {
|
|
|
|
|
wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
|
|
|
|
|
SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
|
|
|
|
|
}
|
2018-10-19 11:04:19 -06:00
|
|
|
|
|
|
|
|
/* The 8th CBOX has different MSR space */
|
|
|
|
|
if (box->pmu->pmu_idx == 7)
|
|
|
|
|
__set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags);
|
2016-06-29 08:01:51 -06:00
|
|
|
}
|
|
|
|
|
|
2016-08-11 08:31:14 -06:00
|
|
|
static void skl_uncore_msr_enable_box(struct intel_uncore_box *box)
|
|
|
|
|
{
|
|
|
|
|
wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
|
|
|
|
|
SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-29 08:01:51 -06:00
|
|
|
static void skl_uncore_msr_exit_box(struct intel_uncore_box *box)
|
|
|
|
|
{
|
|
|
|
|
if (box->pmu->pmu_idx == 0)
|
|
|
|
|
wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_ops skl_uncore_msr_ops = {
|
|
|
|
|
.init_box = skl_uncore_msr_init_box,
|
2016-08-11 08:31:14 -06:00
|
|
|
.enable_box = skl_uncore_msr_enable_box,
|
2016-06-29 08:01:51 -06:00
|
|
|
.exit_box = skl_uncore_msr_exit_box,
|
|
|
|
|
.disable_event = snb_uncore_msr_disable_event,
|
|
|
|
|
.enable_event = snb_uncore_msr_enable_event,
|
|
|
|
|
.read_counter = uncore_msr_read_counter,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_type skl_uncore_cbox = {
|
|
|
|
|
.name = "cbox",
|
|
|
|
|
.num_counters = 4,
|
2018-10-19 11:04:19 -06:00
|
|
|
.num_boxes = 8,
|
2016-06-29 08:01:51 -06:00
|
|
|
.perf_ctr_bits = 44,
|
|
|
|
|
.fixed_ctr_bits = 48,
|
|
|
|
|
.perf_ctr = SNB_UNC_CBO_0_PER_CTR0,
|
|
|
|
|
.event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
|
|
|
|
|
.fixed_ctr = SNB_UNC_FIXED_CTR,
|
|
|
|
|
.fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
|
|
|
|
|
.single_fixed = 1,
|
|
|
|
|
.event_mask = SNB_UNC_RAW_EVENT_MASK,
|
|
|
|
|
.msr_offset = SNB_UNC_CBO_MSR_OFFSET,
|
|
|
|
|
.ops = &skl_uncore_msr_ops,
|
|
|
|
|
.format_group = &snb_uncore_format_group,
|
|
|
|
|
.event_descs = snb_uncore_events,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_type *skl_msr_uncores[] = {
|
|
|
|
|
&skl_uncore_cbox,
|
|
|
|
|
&snb_uncore_arb,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void skl_uncore_cpu_init(void)
|
|
|
|
|
{
|
|
|
|
|
uncore_msr_uncores = skl_msr_uncores;
|
|
|
|
|
if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
|
|
|
|
|
skl_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
|
|
|
|
|
snb_uncore_arb.ops = &skl_uncore_msr_ops;
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-25 07:49:04 -06:00
|
|
|
static struct intel_uncore_ops icl_uncore_msr_ops = {
|
|
|
|
|
.disable_event = snb_uncore_msr_disable_event,
|
|
|
|
|
.enable_event = snb_uncore_msr_enable_event,
|
|
|
|
|
.read_counter = uncore_msr_read_counter,
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-02 13:45:09 -06:00
|
|
|
static struct intel_uncore_type icl_uncore_cbox = {
|
|
|
|
|
.name = "cbox",
|
2020-09-25 07:49:05 -06:00
|
|
|
.num_counters = 2,
|
2019-04-02 13:45:09 -06:00
|
|
|
.perf_ctr_bits = 44,
|
|
|
|
|
.perf_ctr = ICL_UNC_CBO_0_PER_CTR0,
|
|
|
|
|
.event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0,
|
|
|
|
|
.event_mask = SNB_UNC_RAW_EVENT_MASK,
|
|
|
|
|
.msr_offset = ICL_UNC_CBO_MSR_OFFSET,
|
2020-09-25 07:49:04 -06:00
|
|
|
.ops = &icl_uncore_msr_ops,
|
2019-04-02 13:45:09 -06:00
|
|
|
.format_group = &snb_uncore_format_group,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct uncore_event_desc icl_uncore_events[] = {
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff"),
|
|
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct attribute *icl_uncore_clock_formats_attr[] = {
|
|
|
|
|
&format_attr_event.attr,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct attribute_group icl_uncore_clock_format_group = {
|
|
|
|
|
.name = "format",
|
|
|
|
|
.attrs = icl_uncore_clock_formats_attr,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_type icl_uncore_clockbox = {
|
|
|
|
|
.name = "clock",
|
|
|
|
|
.num_counters = 1,
|
|
|
|
|
.num_boxes = 1,
|
|
|
|
|
.fixed_ctr_bits = 48,
|
|
|
|
|
.fixed_ctr = SNB_UNC_FIXED_CTR,
|
|
|
|
|
.fixed_ctl = SNB_UNC_FIXED_CTR_CTRL,
|
|
|
|
|
.single_fixed = 1,
|
|
|
|
|
.event_mask = SNB_UNC_CTL_EV_SEL_MASK,
|
|
|
|
|
.format_group = &icl_uncore_clock_format_group,
|
2020-09-25 07:49:04 -06:00
|
|
|
.ops = &icl_uncore_msr_ops,
|
2019-04-02 13:45:09 -06:00
|
|
|
.event_descs = icl_uncore_events,
|
|
|
|
|
};
|
|
|
|
|
|
2020-09-25 07:49:04 -06:00
|
|
|
static struct intel_uncore_type icl_uncore_arb = {
|
|
|
|
|
.name = "arb",
|
|
|
|
|
.num_counters = 1,
|
|
|
|
|
.num_boxes = 1,
|
|
|
|
|
.perf_ctr_bits = 44,
|
|
|
|
|
.perf_ctr = ICL_UNC_ARB_PER_CTR,
|
|
|
|
|
.event_ctl = ICL_UNC_ARB_PERFEVTSEL,
|
|
|
|
|
.event_mask = SNB_UNC_RAW_EVENT_MASK,
|
|
|
|
|
.ops = &icl_uncore_msr_ops,
|
|
|
|
|
.format_group = &snb_uncore_format_group,
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-02 13:45:09 -06:00
|
|
|
static struct intel_uncore_type *icl_msr_uncores[] = {
|
|
|
|
|
&icl_uncore_cbox,
|
2020-09-25 07:49:04 -06:00
|
|
|
&icl_uncore_arb,
|
2019-04-02 13:45:09 -06:00
|
|
|
&icl_uncore_clockbox,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int icl_get_cbox_num(void)
|
|
|
|
|
{
|
|
|
|
|
u64 num_boxes;
|
|
|
|
|
|
|
|
|
|
rdmsrl(ICL_UNC_CBO_CONFIG, num_boxes);
|
|
|
|
|
|
|
|
|
|
return num_boxes & ICL_UNC_NUM_CBO_MASK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void icl_uncore_cpu_init(void)
|
|
|
|
|
{
|
|
|
|
|
uncore_msr_uncores = icl_msr_uncores;
|
|
|
|
|
icl_uncore_cbox.num_boxes = icl_get_cbox_num();
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
enum {
|
|
|
|
|
SNB_PCI_UNCORE_IMC,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct uncore_event_desc snb_uncore_imc_events[] = {
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(data_reads, "event=0x01"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"),
|
|
|
|
|
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
|
|
|
|
|
|
|
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#define SNB_UNCORE_PCI_IMC_EVENT_MASK 0xff
|
|
|
|
|
#define SNB_UNCORE_PCI_IMC_BAR_OFFSET 0x48
|
|
|
|
|
|
|
|
|
|
/* page size multiple covering all config regs */
|
|
|
|
|
#define SNB_UNCORE_PCI_IMC_MAP_SIZE 0x6000
|
|
|
|
|
|
|
|
|
|
#define SNB_UNCORE_PCI_IMC_DATA_READS 0x1
|
|
|
|
|
#define SNB_UNCORE_PCI_IMC_DATA_READS_BASE 0x5050
|
|
|
|
|
#define SNB_UNCORE_PCI_IMC_DATA_WRITES 0x2
|
|
|
|
|
#define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
|
|
|
|
|
#define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
|
|
|
|
|
|
2018-05-03 12:25:13 -06:00
|
|
|
enum perf_snb_uncore_imc_freerunning_types {
|
|
|
|
|
SNB_PCI_UNCORE_IMC_DATA = 0,
|
|
|
|
|
SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct freerunning_counters snb_uncore_imc_freerunning[] = {
|
|
|
|
|
[SNB_PCI_UNCORE_IMC_DATA] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x4, 0x0, 2, 32 },
|
|
|
|
|
};
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
static struct attribute *snb_uncore_imc_formats_attr[] = {
|
|
|
|
|
&format_attr_event.attr,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
2017-07-20 05:30:32 -06:00
|
|
|
static const struct attribute_group snb_uncore_imc_format_group = {
|
2014-07-30 01:22:13 -06:00
|
|
|
.name = "format",
|
|
|
|
|
.attrs = snb_uncore_imc_formats_attr,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
|
|
|
|
|
{
|
|
|
|
|
struct pci_dev *pdev = box->pci_dev;
|
|
|
|
|
int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET;
|
|
|
|
|
resource_size_t addr;
|
|
|
|
|
u32 pci_dword;
|
|
|
|
|
|
|
|
|
|
pci_read_config_dword(pdev, where, &pci_dword);
|
|
|
|
|
addr = pci_dword;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PHYS_ADDR_T_64BIT
|
|
|
|
|
pci_read_config_dword(pdev, where + 4, &pci_dword);
|
|
|
|
|
addr |= ((resource_size_t)pci_dword << 32);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
addr &= ~(PAGE_SIZE - 1);
|
|
|
|
|
|
|
|
|
|
box->io_addr = ioremap(addr, SNB_UNCORE_PCI_IMC_MAP_SIZE);
|
|
|
|
|
box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
|
|
|
|
|
{}
|
|
|
|
|
|
|
|
|
|
static void snb_uncore_imc_disable_box(struct intel_uncore_box *box)
|
|
|
|
|
{}
|
|
|
|
|
|
|
|
|
|
static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event)
|
|
|
|
|
{}
|
|
|
|
|
|
|
|
|
|
static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event)
|
|
|
|
|
{}
|
|
|
|
|
|
|
|
|
|
/*
|
2018-05-03 12:25:13 -06:00
|
|
|
* Keep the custom event_init() function compatible with old event
|
|
|
|
|
* encoding for free running counters.
|
2014-07-30 01:22:13 -06:00
|
|
|
*/
|
|
|
|
|
static int snb_uncore_imc_event_init(struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
struct intel_uncore_pmu *pmu;
|
|
|
|
|
struct intel_uncore_box *box;
|
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
|
u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK;
|
|
|
|
|
int idx, base;
|
|
|
|
|
|
|
|
|
|
if (event->attr.type != event->pmu->type)
|
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
|
|
pmu = uncore_event_to_pmu(event);
|
|
|
|
|
/* no device found for this pmu */
|
|
|
|
|
if (pmu->func_id < 0)
|
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
|
|
/* Sampling not supported yet */
|
|
|
|
|
if (hwc->sample_period)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
/* unsupported modes and filters */
|
2019-01-10 06:53:32 -07:00
|
|
|
if (event->attr.sample_period) /* no sampling */
|
2014-07-30 01:22:13 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Place all uncore events for a particular physical package
|
|
|
|
|
* onto a single cpu
|
|
|
|
|
*/
|
|
|
|
|
if (event->cpu < 0)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
/* check only supported bits are set */
|
|
|
|
|
if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
box = uncore_pmu_to_box(pmu, event->cpu);
|
|
|
|
|
if (!box || box->cpu < 0)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
event->cpu = box->cpu;
|
2016-02-22 15:19:14 -07:00
|
|
|
event->pmu_private = box;
|
2014-07-30 01:22:13 -06:00
|
|
|
|
2016-08-17 14:55:07 -06:00
|
|
|
event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG;
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
event->hw.idx = -1;
|
|
|
|
|
event->hw.last_tag = ~0ULL;
|
|
|
|
|
event->hw.extra_reg.idx = EXTRA_REG_NONE;
|
|
|
|
|
event->hw.branch_reg.idx = EXTRA_REG_NONE;
|
|
|
|
|
/*
|
|
|
|
|
* check event is known (whitelist, determines counter)
|
|
|
|
|
*/
|
|
|
|
|
switch (cfg) {
|
|
|
|
|
case SNB_UNCORE_PCI_IMC_DATA_READS:
|
|
|
|
|
base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
|
2018-05-03 12:25:13 -06:00
|
|
|
idx = UNCORE_PMC_IDX_FREERUNNING;
|
2014-07-30 01:22:13 -06:00
|
|
|
break;
|
|
|
|
|
case SNB_UNCORE_PCI_IMC_DATA_WRITES:
|
|
|
|
|
base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
|
2018-05-03 12:25:13 -06:00
|
|
|
idx = UNCORE_PMC_IDX_FREERUNNING;
|
2014-07-30 01:22:13 -06:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* must be done before validate_group */
|
|
|
|
|
event->hw.event_base = base;
|
|
|
|
|
event->hw.idx = idx;
|
|
|
|
|
|
perf/x86/intel/uncore: Fix client IMC events return huge result
The client IMC bandwidth events currently return very large values:
$ perf stat -e uncore_imc/data_reads/ -e uncore_imc/data_writes/ -I 10000 -a
10.000117222 34,788.76 MiB uncore_imc/data_reads/
10.000117222 8.26 MiB uncore_imc/data_writes/
20.000374584 34,842.89 MiB uncore_imc/data_reads/
20.000374584 10.45 MiB uncore_imc/data_writes/
30.000633299 37,965.29 MiB uncore_imc/data_reads/
30.000633299 323.62 MiB uncore_imc/data_writes/
40.000891548 41,012.88 MiB uncore_imc/data_reads/
40.000891548 6.98 MiB uncore_imc/data_writes/
50.001142480 1,125,899,906,621,494.75 MiB uncore_imc/data_reads/
50.001142480 6.97 MiB uncore_imc/data_writes/
The client IMC events are freerunning counters. They still use the
old event encoding format (0x1 for data_read and 0x2 for data write).
The counter bit width is calculated by common code, which assume that
the standard encoding format is used for the freerunning counters.
Error bit width information is calculated.
The patch intends to convert the old client IMC event encoding to the
standard encoding format.
Current common code uses event->attr.config which directly copy from
user space. We should not implicitly modify it for a converted event.
The event->hw.config is used to replace the event->attr.config in
common code.
For client IMC events, the event->attr.config is used to calculate a
converted event with standard encoding format in the custom
event_init(). The converted event is stored in event->hw.config.
For other events of freerunning counters, they already use the standard
encoding format. The same value as event->attr.config is assigned to
event->hw.config in common event_init().
Reported-by: Jin Yao <yao.jin@linux.intel.com>
Tested-by: Jin Yao <yao.jin@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rik van Riel <riel@surriel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: stable@kernel.org # v4.18+
Fixes: 9aae1780e7e8 ("perf/x86/intel/uncore: Clean up client IMC uncore")
Link: https://lkml.kernel.org/r/20190227165729.1861-1-kan.liang@linux.intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-02-27 09:57:29 -07:00
|
|
|
/* Convert to standard encoding format for freerunning counters */
|
|
|
|
|
event->hw.config = ((cfg - 1) << 8) | 0x10ff;
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
/* no group validation needed, we have free running counters */
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
perf/x86/intel/uncore: Add Knights Landing uncore PMU support
Knights Landing uncore performance monitoring (perfmon) is derived from
Haswell-EP uncore perfmon with several differences. One notable difference
is in PCI device IDs. Knights Landing uses common PCI device ID for
multiple instances of an uncore PMU device type. In Haswell-EP, each
instance of a PMU device type has a unique device ID.
Knights Landing uncore components that have performance monitoring units
are UBOX, CHA, EDC, MC, M2PCIe, IRP and PCU. Perfmon registers in EDC, MC,
IRP, and M2PCIe reside in the PCIe configuration space. Perfmon registers
in UBOX, CHA and PCU are accessed via the MSR interface.
For more details, please refer to the public document:
https://software.intel.com/sites/default/files/managed/15/8d/IntelXeonPhi%E2%84%A2x200ProcessorPerformanceMonitoringReferenceManual_Volume1_Registers_v0%206.pdf
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andi Kleen <andi.kleen@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Harish Chegondi <harish.chegondi@gmail.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Lukasz Anaczkowski <lukasz.anaczkowski@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/8ac513981264c3eb10343a3f523f19cc5a2d12fe.1449470704.git.harish.chegondi@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-12-07 15:32:32 -07:00
|
|
|
int snb_pci2phy_map_init(int devid)
|
2014-07-30 01:22:13 -06:00
|
|
|
{
|
|
|
|
|
struct pci_dev *dev = NULL;
|
2015-09-24 06:10:21 -06:00
|
|
|
struct pci2phy_map *map;
|
|
|
|
|
int bus, segment;
|
2014-07-30 01:22:13 -06:00
|
|
|
|
|
|
|
|
dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev);
|
|
|
|
|
if (!dev)
|
|
|
|
|
return -ENOTTY;
|
|
|
|
|
|
|
|
|
|
bus = dev->bus->number;
|
2015-09-24 06:10:21 -06:00
|
|
|
segment = pci_domain_nr(dev->bus);
|
|
|
|
|
|
|
|
|
|
raw_spin_lock(&pci2phy_map_lock);
|
|
|
|
|
map = __find_pci2phy_map(segment);
|
|
|
|
|
if (!map) {
|
|
|
|
|
raw_spin_unlock(&pci2phy_map_lock);
|
|
|
|
|
pci_dev_put(dev);
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
}
|
|
|
|
|
map->pbus_to_physid[bus] = 0;
|
|
|
|
|
raw_spin_unlock(&pci2phy_map_lock);
|
2014-07-30 01:22:13 -06:00
|
|
|
|
|
|
|
|
pci_dev_put(dev);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct pmu snb_uncore_imc_pmu = {
|
|
|
|
|
.task_ctx_nr = perf_invalid_context,
|
|
|
|
|
.event_init = snb_uncore_imc_event_init,
|
2018-05-03 12:25:13 -06:00
|
|
|
.add = uncore_pmu_event_add,
|
|
|
|
|
.del = uncore_pmu_event_del,
|
|
|
|
|
.start = uncore_pmu_event_start,
|
|
|
|
|
.stop = uncore_pmu_event_stop,
|
|
|
|
|
.read = uncore_pmu_event_read,
|
2019-01-10 06:53:32 -07:00
|
|
|
.capabilities = PERF_PMU_CAP_NO_EXCLUDE,
|
2014-07-30 01:22:13 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_ops snb_uncore_imc_ops = {
|
|
|
|
|
.init_box = snb_uncore_imc_init_box,
|
2019-04-30 18:53:47 -06:00
|
|
|
.exit_box = uncore_mmio_exit_box,
|
2014-07-30 01:22:13 -06:00
|
|
|
.enable_box = snb_uncore_imc_enable_box,
|
|
|
|
|
.disable_box = snb_uncore_imc_disable_box,
|
|
|
|
|
.disable_event = snb_uncore_imc_disable_event,
|
|
|
|
|
.enable_event = snb_uncore_imc_enable_event,
|
|
|
|
|
.hw_config = snb_uncore_imc_hw_config,
|
2019-04-30 18:53:47 -06:00
|
|
|
.read_counter = uncore_mmio_read_counter,
|
2014-07-30 01:22:13 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_type snb_uncore_imc = {
|
|
|
|
|
.name = "imc",
|
|
|
|
|
.num_counters = 2,
|
|
|
|
|
.num_boxes = 1,
|
2018-05-03 12:25:13 -06:00
|
|
|
.num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
|
|
|
|
|
.freerunning = snb_uncore_imc_freerunning,
|
2014-07-30 01:22:13 -06:00
|
|
|
.event_descs = snb_uncore_imc_events,
|
|
|
|
|
.format_group = &snb_uncore_imc_format_group,
|
|
|
|
|
.ops = &snb_uncore_imc_ops,
|
|
|
|
|
.pmu = &snb_uncore_imc_pmu,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_type *snb_pci_uncores[] = {
|
|
|
|
|
[SNB_PCI_UNCORE_IMC] = &snb_uncore_imc,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-24 14:32:24 -06:00
|
|
|
static const struct pci_device_id snb_uncore_pci_ids[] = {
|
2014-07-30 01:22:13 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SNB_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-24 14:32:24 -06:00
|
|
|
static const struct pci_device_id ivb_uncore_pci_ids[] = {
|
2014-07-30 01:22:13 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2014-09-17 03:06:16 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_E3_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2014-07-30 01:22:13 -06:00
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-24 14:32:24 -06:00
|
|
|
static const struct pci_device_id hsw_uncore_pci_ids[] = {
|
2014-07-30 01:22:13 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2015-04-20 16:34:07 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_U_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2014-07-30 01:22:13 -06:00
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
2015-04-23 00:56:42 -06:00
|
|
|
static const struct pci_device_id bdw_uncore_pci_ids[] = {
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
2016-01-07 00:25:46 -07:00
|
|
|
static const struct pci_device_id skl_uncore_pci_ids[] = {
|
|
|
|
|
{ /* IMC */
|
2016-11-08 11:54:41 -07:00
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_Y_IMC),
|
2016-01-07 00:25:46 -07:00
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2016-06-29 08:01:51 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_U_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2016-11-08 11:54:41 -07:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HD_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_HQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SD_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_SQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2020-01-10 13:15:11 -07:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SKL_E3_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2018-10-19 11:04:18 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_Y_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_U_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_UQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SD_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_SQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2019-05-10 18:03:11 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_HQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBL_WQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2018-10-19 11:04:18 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2U_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4U_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4H_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6H_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2019-05-10 18:03:11 -06:00
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AML_YD_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AML_YQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WHL_UD_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
2016-01-07 00:25:46 -07:00
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-02 13:45:09 -06:00
|
|
|
static const struct pci_device_id icl_uncore_pci_ids[] = {
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICL_U_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* IMC */
|
|
|
|
|
PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICL_U2_IMC),
|
|
|
|
|
.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
|
|
|
|
|
},
|
|
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
static struct pci_driver snb_uncore_pci_driver = {
|
|
|
|
|
.name = "snb_uncore",
|
|
|
|
|
.id_table = snb_uncore_pci_ids,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct pci_driver ivb_uncore_pci_driver = {
|
|
|
|
|
.name = "ivb_uncore",
|
|
|
|
|
.id_table = ivb_uncore_pci_ids,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct pci_driver hsw_uncore_pci_driver = {
|
|
|
|
|
.name = "hsw_uncore",
|
|
|
|
|
.id_table = hsw_uncore_pci_ids,
|
|
|
|
|
};
|
|
|
|
|
|
2015-04-23 00:56:42 -06:00
|
|
|
static struct pci_driver bdw_uncore_pci_driver = {
|
|
|
|
|
.name = "bdw_uncore",
|
|
|
|
|
.id_table = bdw_uncore_pci_ids,
|
|
|
|
|
};
|
|
|
|
|
|
2016-01-07 00:25:46 -07:00
|
|
|
static struct pci_driver skl_uncore_pci_driver = {
|
|
|
|
|
.name = "skl_uncore",
|
|
|
|
|
.id_table = skl_uncore_pci_ids,
|
|
|
|
|
};
|
|
|
|
|
|
2019-04-02 13:45:09 -06:00
|
|
|
static struct pci_driver icl_uncore_pci_driver = {
|
|
|
|
|
.name = "icl_uncore",
|
|
|
|
|
.id_table = icl_uncore_pci_ids,
|
|
|
|
|
};
|
|
|
|
|
|
2014-09-17 03:06:16 -06:00
|
|
|
struct imc_uncore_pci_dev {
|
|
|
|
|
__u32 pci_id;
|
|
|
|
|
struct pci_driver *driver;
|
|
|
|
|
};
|
|
|
|
|
#define IMC_DEV(a, d) \
|
|
|
|
|
{ .pci_id = PCI_DEVICE_ID_INTEL_##a, .driver = (d) }
|
|
|
|
|
|
|
|
|
|
static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
|
|
|
|
|
IMC_DEV(SNB_IMC, &snb_uncore_pci_driver),
|
|
|
|
|
IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver), /* 3rd Gen Core processor */
|
|
|
|
|
IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */
|
|
|
|
|
IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core Processor */
|
2015-04-20 16:34:07 -06:00
|
|
|
IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver), /* 4th Gen Core ULT Mobile Processor */
|
2015-04-23 00:56:42 -06:00
|
|
|
IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver), /* 5th Gen Core U */
|
2016-11-08 11:54:41 -07:00
|
|
|
IMC_DEV(SKL_Y_IMC, &skl_uncore_pci_driver), /* 6th Gen Core Y */
|
2016-06-29 08:01:51 -06:00
|
|
|
IMC_DEV(SKL_U_IMC, &skl_uncore_pci_driver), /* 6th Gen Core U */
|
2016-11-08 11:54:41 -07:00
|
|
|
IMC_DEV(SKL_HD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Dual Core */
|
|
|
|
|
IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core H Quad Core */
|
|
|
|
|
IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Dual Core */
|
|
|
|
|
IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver), /* 6th Gen Core S Quad Core */
|
2020-01-10 13:15:11 -07:00
|
|
|
IMC_DEV(SKL_E3_IMC, &skl_uncore_pci_driver), /* Xeon E3 V5 Gen Core processor */
|
2018-10-19 11:04:18 -06:00
|
|
|
IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver), /* 7th Gen Core Y */
|
|
|
|
|
IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U */
|
|
|
|
|
IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core U Quad Core */
|
|
|
|
|
IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Dual Core */
|
|
|
|
|
IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S Quad Core */
|
2019-05-10 18:03:11 -06:00
|
|
|
IMC_DEV(KBL_HQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core H Quad Core */
|
|
|
|
|
IMC_DEV(KBL_WQ_IMC, &skl_uncore_pci_driver), /* 7th Gen Core S 4 cores Work Station */
|
2018-10-19 11:04:18 -06:00
|
|
|
IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 2 Cores */
|
|
|
|
|
IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U 4 Cores */
|
|
|
|
|
IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 4 Cores */
|
|
|
|
|
IMC_DEV(CFL_6H_IMC, &skl_uncore_pci_driver), /* 8th Gen Core H 6 Cores */
|
|
|
|
|
IMC_DEV(CFL_2S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 2 Cores Desktop */
|
|
|
|
|
IMC_DEV(CFL_4S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Desktop */
|
|
|
|
|
IMC_DEV(CFL_6S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Desktop */
|
|
|
|
|
IMC_DEV(CFL_8S_D_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Desktop */
|
|
|
|
|
IMC_DEV(CFL_4S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Work Station */
|
|
|
|
|
IMC_DEV(CFL_6S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Work Station */
|
|
|
|
|
IMC_DEV(CFL_8S_W_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Work Station */
|
|
|
|
|
IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 4 Cores Server */
|
|
|
|
|
IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 6 Cores Server */
|
|
|
|
|
IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver), /* 8th Gen Core S 8 Cores Server */
|
2019-05-10 18:03:11 -06:00
|
|
|
IMC_DEV(AML_YD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core Y Mobile Dual Core */
|
|
|
|
|
IMC_DEV(AML_YQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core Y Mobile Quad Core */
|
|
|
|
|
IMC_DEV(WHL_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */
|
|
|
|
|
IMC_DEV(WHL_4_UQ_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Quad Core */
|
|
|
|
|
IMC_DEV(WHL_UD_IMC, &skl_uncore_pci_driver), /* 8th Gen Core U Mobile Dual Core */
|
2019-04-02 13:45:09 -06:00
|
|
|
IMC_DEV(ICL_U_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
|
|
|
|
|
IMC_DEV(ICL_U2_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
|
2014-09-17 03:06:16 -06:00
|
|
|
{ /* end marker */ }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#define for_each_imc_pci_id(x, t) \
|
|
|
|
|
for (x = (t); (x)->pci_id; x++)
|
|
|
|
|
|
|
|
|
|
static struct pci_driver *imc_uncore_find_dev(void)
|
2014-07-30 01:22:13 -06:00
|
|
|
{
|
2014-09-17 03:06:16 -06:00
|
|
|
const struct imc_uncore_pci_dev *p;
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
for_each_imc_pci_id(p, desktop_imc_pci_ids) {
|
|
|
|
|
ret = snb_pci2phy_map_init(p->pci_id);
|
|
|
|
|
if (ret == 0)
|
|
|
|
|
return p->driver;
|
|
|
|
|
}
|
|
|
|
|
return NULL;
|
2014-07-30 01:22:13 -06:00
|
|
|
}
|
|
|
|
|
|
2014-09-17 03:06:16 -06:00
|
|
|
static int imc_uncore_pci_init(void)
|
2014-07-30 01:22:13 -06:00
|
|
|
{
|
2014-09-17 03:06:16 -06:00
|
|
|
struct pci_driver *imc_drv = imc_uncore_find_dev();
|
|
|
|
|
|
|
|
|
|
if (!imc_drv)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
uncore_pci_uncores = snb_pci_uncores;
|
2014-09-17 03:06:16 -06:00
|
|
|
uncore_pci_driver = imc_drv;
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2014-09-17 03:06:16 -06:00
|
|
|
int snb_uncore_pci_init(void)
|
|
|
|
|
{
|
|
|
|
|
return imc_uncore_pci_init();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int ivb_uncore_pci_init(void)
|
|
|
|
|
{
|
|
|
|
|
return imc_uncore_pci_init();
|
|
|
|
|
}
|
2014-07-30 01:22:13 -06:00
|
|
|
int hsw_uncore_pci_init(void)
|
|
|
|
|
{
|
2014-09-17 03:06:16 -06:00
|
|
|
return imc_uncore_pci_init();
|
2014-07-30 01:22:13 -06:00
|
|
|
}
|
|
|
|
|
|
2015-04-23 00:56:42 -06:00
|
|
|
int bdw_uncore_pci_init(void)
|
|
|
|
|
{
|
|
|
|
|
return imc_uncore_pci_init();
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-07 00:25:46 -07:00
|
|
|
int skl_uncore_pci_init(void)
|
|
|
|
|
{
|
|
|
|
|
return imc_uncore_pci_init();
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-30 01:22:13 -06:00
|
|
|
/* end of Sandy Bridge uncore support */
|
|
|
|
|
|
|
|
|
|
/* Nehalem uncore support */
|
|
|
|
|
static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
|
|
|
|
|
{
|
|
|
|
|
wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
|
|
|
|
|
{
|
|
|
|
|
wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
|
|
|
|
|
{
|
|
|
|
|
struct hw_perf_event *hwc = &event->hw;
|
|
|
|
|
|
|
|
|
|
if (hwc->idx < UNCORE_PMC_IDX_FIXED)
|
|
|
|
|
wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
|
|
|
|
|
else
|
|
|
|
|
wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct attribute *nhm_uncore_formats_attr[] = {
|
|
|
|
|
&format_attr_event.attr,
|
|
|
|
|
&format_attr_umask.attr,
|
|
|
|
|
&format_attr_edge.attr,
|
|
|
|
|
&format_attr_inv.attr,
|
|
|
|
|
&format_attr_cmask8.attr,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
2017-07-20 05:30:32 -06:00
|
|
|
static const struct attribute_group nhm_uncore_format_group = {
|
2014-07-30 01:22:13 -06:00
|
|
|
.name = "format",
|
|
|
|
|
.attrs = nhm_uncore_formats_attr,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct uncore_event_desc nhm_uncore_events[] = {
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"),
|
|
|
|
|
INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"),
|
|
|
|
|
{ /* end: all zeroes */ },
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_ops nhm_uncore_msr_ops = {
|
|
|
|
|
.disable_box = nhm_uncore_msr_disable_box,
|
|
|
|
|
.enable_box = nhm_uncore_msr_enable_box,
|
|
|
|
|
.disable_event = snb_uncore_msr_disable_event,
|
|
|
|
|
.enable_event = nhm_uncore_msr_enable_event,
|
|
|
|
|
.read_counter = uncore_msr_read_counter,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_type nhm_uncore = {
|
|
|
|
|
.name = "",
|
|
|
|
|
.num_counters = 8,
|
|
|
|
|
.num_boxes = 1,
|
|
|
|
|
.perf_ctr_bits = 48,
|
|
|
|
|
.fixed_ctr_bits = 48,
|
|
|
|
|
.event_ctl = NHM_UNC_PERFEVTSEL0,
|
|
|
|
|
.perf_ctr = NHM_UNC_UNCORE_PMC0,
|
|
|
|
|
.fixed_ctr = NHM_UNC_FIXED_CTR,
|
|
|
|
|
.fixed_ctl = NHM_UNC_FIXED_CTR_CTRL,
|
|
|
|
|
.event_mask = NHM_UNC_RAW_EVENT_MASK,
|
|
|
|
|
.event_descs = nhm_uncore_events,
|
|
|
|
|
.ops = &nhm_uncore_msr_ops,
|
|
|
|
|
.format_group = &nhm_uncore_format_group,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct intel_uncore_type *nhm_msr_uncores[] = {
|
|
|
|
|
&nhm_uncore,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
void nhm_uncore_cpu_init(void)
|
|
|
|
|
{
|
|
|
|
|
uncore_msr_uncores = nhm_msr_uncores;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* end of Nehalem uncore support */
|