2019-05-28 11:10:04 -06:00
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// SPDX-License-Identifier: GPL-2.0-only
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2014-06-12 09:36:37 -06:00
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/*
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* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Based on drivers/misc/eeprom/sunxi_sid.c
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*/
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#include <linux/device.h>
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#include <linux/clk.h>
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2014-06-12 09:36:40 -06:00
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#include <linux/completion.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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2014-06-12 09:36:37 -06:00
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/kobject.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/random.h>
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#include <soc/tegra/fuse.h>
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#include "fuse.h"
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#define FUSE_BEGIN 0x100
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#define FUSE_UID_LOW 0x08
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#define FUSE_UID_HIGH 0x0c
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2015-04-29 08:54:04 -06:00
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static u32 tegra20_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
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{
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return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
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}
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2014-06-12 09:36:40 -06:00
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static void apb_dma_complete(void *args)
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{
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2015-04-29 08:54:04 -06:00
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struct tegra_fuse *fuse = args;
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complete(&fuse->apbdma.wait);
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2014-06-12 09:36:40 -06:00
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}
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2015-04-29 08:54:04 -06:00
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static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
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{
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unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
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struct dma_async_tx_descriptor *dma_desc;
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2015-03-09 01:12:26 -06:00
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unsigned long time_left;
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u32 value = 0;
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int err;
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mutex_lock(&fuse->apbdma.lock);
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2014-06-12 09:36:40 -06:00
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2017-10-19 16:08:03 -06:00
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fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset;
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2014-06-12 09:36:40 -06:00
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2015-04-29 08:54:04 -06:00
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err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config);
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if (err)
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goto out;
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2015-04-29 08:54:04 -06:00
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dma_desc = dmaengine_prep_slave_single(fuse->apbdma.chan,
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fuse->apbdma.phys,
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sizeof(u32), DMA_DEV_TO_MEM,
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flags);
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2014-06-12 09:36:40 -06:00
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if (!dma_desc)
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goto out;
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dma_desc->callback = apb_dma_complete;
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2015-04-29 08:54:04 -06:00
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dma_desc->callback_param = fuse;
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2014-06-12 09:36:40 -06:00
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2015-04-29 08:54:04 -06:00
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reinit_completion(&fuse->apbdma.wait);
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2014-06-12 09:36:37 -06:00
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2015-04-29 08:54:04 -06:00
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clk_prepare_enable(fuse->clk);
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2014-06-12 09:36:37 -06:00
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2014-06-12 09:36:40 -06:00
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dmaengine_submit(dma_desc);
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2015-04-29 08:54:04 -06:00
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dma_async_issue_pending(fuse->apbdma.chan);
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time_left = wait_for_completion_timeout(&fuse->apbdma.wait,
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2015-03-09 01:12:26 -06:00
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msecs_to_jiffies(50));
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2014-06-12 09:36:40 -06:00
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2015-03-09 01:12:26 -06:00
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if (WARN(time_left == 0, "apb read dma timed out"))
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2015-04-29 08:54:04 -06:00
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dmaengine_terminate_all(fuse->apbdma.chan);
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2014-06-12 09:36:40 -06:00
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else
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2015-04-29 08:54:04 -06:00
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value = *fuse->apbdma.virt;
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2014-06-12 09:36:37 -06:00
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2015-04-29 08:54:04 -06:00
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clk_disable_unprepare(fuse->clk);
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2014-06-12 09:36:37 -06:00
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2015-04-29 08:54:04 -06:00
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out:
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mutex_unlock(&fuse->apbdma.lock);
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return value;
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2014-06-12 09:36:37 -06:00
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}
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2017-10-19 16:08:04 -06:00
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static bool dma_filter(struct dma_chan *chan, void *filter_param)
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{
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struct device_node *np = chan->device->dev->of_node;
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return of_device_is_compatible(np, "nvidia,tegra20-apbdma");
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}
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2015-04-29 08:54:04 -06:00
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static int tegra20_fuse_probe(struct tegra_fuse *fuse)
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{
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dma_cap_mask_t mask;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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2015-04-29 08:54:04 -06:00
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2019-05-20 05:32:15 -06:00
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fuse->apbdma.chan = dma_request_channel(mask, dma_filter, NULL);
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2015-04-29 08:54:04 -06:00
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if (!fuse->apbdma.chan)
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2014-06-12 09:36:40 -06:00
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return -EPROBE_DEFER;
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2015-04-29 08:54:04 -06:00
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fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32),
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&fuse->apbdma.phys,
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GFP_KERNEL);
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if (!fuse->apbdma.virt) {
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dma_release_channel(fuse->apbdma.chan);
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2014-06-12 09:36:40 -06:00
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return -ENOMEM;
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}
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2015-04-29 08:54:04 -06:00
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fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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fuse->apbdma.config.src_maxburst = 1;
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fuse->apbdma.config.dst_maxburst = 1;
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2017-10-19 16:08:03 -06:00
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fuse->apbdma.config.direction = DMA_DEV_TO_MEM;
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fuse->apbdma.config.device_fc = false;
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2014-06-12 09:36:40 -06:00
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2015-04-29 08:54:04 -06:00
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init_completion(&fuse->apbdma.wait);
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mutex_init(&fuse->apbdma.lock);
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fuse->read = tegra20_fuse_read;
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2014-06-12 09:36:37 -06:00
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return 0;
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}
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2015-04-29 08:54:04 -06:00
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static const struct tegra_fuse_info tegra20_fuse_info = {
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.read = tegra20_fuse_read,
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.size = 0x1f8,
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.spare = 0x100,
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};
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/* Early boot code. This code is called before the devices are created */
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static void __init tegra20_fuse_add_randomness(void)
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{
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u32 randomness[7];
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randomness[0] = tegra_sku_info.sku_id;
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randomness[1] = tegra_read_straps();
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randomness[2] = tegra_read_chipid();
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randomness[3] = tegra_sku_info.cpu_process_id << 16;
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2015-03-23 07:44:08 -06:00
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randomness[3] |= tegra_sku_info.soc_process_id;
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randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
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randomness[4] |= tegra_sku_info.soc_speedo_id;
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2015-04-29 08:54:04 -06:00
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randomness[5] = tegra_fuse_read_early(FUSE_UID_LOW);
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randomness[6] = tegra_fuse_read_early(FUSE_UID_HIGH);
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2014-06-12 09:36:37 -06:00
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add_device_randomness(randomness, sizeof(randomness));
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}
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2015-04-29 08:54:04 -06:00
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static void __init tegra20_fuse_init(struct tegra_fuse *fuse)
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{
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fuse->read_early = tegra20_fuse_read_early;
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2014-06-12 09:36:37 -06:00
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tegra_init_revision();
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2015-04-29 08:54:04 -06:00
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fuse->soc->speedo_init(&tegra_sku_info);
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2014-06-12 09:36:37 -06:00
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tegra20_fuse_add_randomness();
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}
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2015-04-29 08:54:04 -06:00
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const struct tegra_fuse_soc tegra20_fuse_soc = {
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.init = tegra20_fuse_init,
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.speedo_init = tegra20_init_speedo_data,
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.probe = tegra20_fuse_probe,
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.info = &tegra20_fuse_info,
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soc/tegra: fuse: Add custom SoC attributes
Add a custom SoC attribute for Tegra to expose the HIDREV register
fields to userspace via the sysfs. This register provides additional
details about the type of device (eg, silicon, FPGA, etc) as well as
revision. Exposing this information is useful for identifying the
exact device revision and device type.
For Tegra devices up until Tegra186, the majorrev and minorrev fields of
the HIDREV register are used to determine the device revision and device
type. For Tegra194, the majorrev and minorrev fields only determine the
revision. Starting with Tegra194, there is an additional field,
pre_si_platform (which occupies bits 20-23), that now determines device
type. Therefore, for all Tegra devices, add a custom SoC attribute for
the majorrev and minorrev fields and for Tegra194 add an additional
attribute for the pre_si_platform field.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-04-17 06:39:48 -06:00
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.soc_attr_group = &tegra_soc_attr_group,
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2015-04-29 08:54:04 -06:00
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};
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