2009-06-05 06:42:42 -06:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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2012-10-02 11:01:07 -06:00
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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2009-06-05 06:42:42 -06:00
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#include "radeon.h"
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void radeon_gem_object_free(struct drm_gem_object *gobj)
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{
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2011-02-18 09:59:17 -07:00
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struct radeon_bo *robj = gem_to_radeon_bo(gobj);
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2009-06-05 06:42:42 -06:00
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if (robj) {
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2012-05-10 16:33:13 -06:00
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if (robj->gem_base.import_attach)
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drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
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2015-07-14 07:58:30 -06:00
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radeon_mn_unregister(robj);
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2009-11-20 06:29:23 -07:00
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radeon_bo_unref(&robj);
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2009-06-05 06:42:42 -06:00
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}
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}
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2014-07-17 10:26:29 -06:00
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int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
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2009-11-20 06:29:23 -07:00
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int alignment, int initial_domain,
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2014-07-21 05:27:27 -06:00
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u32 flags, bool kernel,
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2009-11-20 06:29:23 -07:00
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struct drm_gem_object **obj)
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2009-06-05 06:42:42 -06:00
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{
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2009-11-20 06:29:23 -07:00
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struct radeon_bo *robj;
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2012-10-23 07:53:18 -06:00
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unsigned long max_size;
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2009-06-05 06:42:42 -06:00
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int r;
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*obj = NULL;
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/* At least align on page size */
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if (alignment < PAGE_SIZE) {
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alignment = PAGE_SIZE;
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}
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2012-10-23 07:53:18 -06:00
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2014-07-17 10:26:29 -06:00
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/* Maximum bo size is the unpinned gtt size since we use the gtt to
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* handle vram to system pool migrations.
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*/
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max_size = rdev->mc.gtt_size - rdev->gart_pin_size;
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2012-10-23 07:53:18 -06:00
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if (size > max_size) {
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2014-07-17 10:26:29 -06:00
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DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
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2014-07-16 03:40:32 -06:00
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size >> 20, max_size >> 20);
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2012-10-23 07:53:18 -06:00
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return -ENOMEM;
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}
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2012-10-23 07:53:19 -06:00
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retry:
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2014-07-17 04:01:08 -06:00
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r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain,
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2014-09-18 06:11:56 -06:00
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flags, NULL, NULL, &robj);
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2009-06-05 06:42:42 -06:00
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if (r) {
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2012-10-23 07:53:19 -06:00
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if (r != -ERESTARTSYS) {
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if (initial_domain == RADEON_GEM_DOMAIN_VRAM) {
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initial_domain |= RADEON_GEM_DOMAIN_GTT;
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goto retry;
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}
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2014-07-17 10:26:29 -06:00
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DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
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2009-12-14 17:39:48 -07:00
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size, initial_domain, alignment, r);
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2012-10-23 07:53:19 -06:00
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}
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2009-06-05 06:42:42 -06:00
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return r;
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}
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2011-02-18 09:59:16 -07:00
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*obj = &robj->gem_base;
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2013-04-25 20:29:27 -06:00
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robj->pid = task_pid_nr(current);
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2011-02-18 09:59:16 -07:00
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mutex_lock(&rdev->gem.mutex);
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list_add_tail(&robj->list, &rdev->gem.objects);
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mutex_unlock(&rdev->gem.mutex);
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2009-06-05 06:42:42 -06:00
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return 0;
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}
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2014-01-06 08:28:45 -07:00
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static int radeon_gem_set_domain(struct drm_gem_object *gobj,
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2009-06-05 06:42:42 -06:00
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uint32_t rdomain, uint32_t wdomain)
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{
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2009-11-20 06:29:23 -07:00
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struct radeon_bo *robj;
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2009-06-05 06:42:42 -06:00
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uint32_t domain;
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2014-05-14 07:40:49 -06:00
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long r;
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2009-06-05 06:42:42 -06:00
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/* FIXME: reeimplement */
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2011-02-18 09:59:17 -07:00
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robj = gem_to_radeon_bo(gobj);
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2009-06-05 06:42:42 -06:00
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/* work out where to validate the buffer to */
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domain = wdomain;
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if (!domain) {
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domain = rdomain;
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}
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if (!domain) {
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/* Do nothings */
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2017-02-28 05:55:52 -07:00
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pr_warn("Set domain without domain !\n");
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2009-06-05 06:42:42 -06:00
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return 0;
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}
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if (domain == RADEON_GEM_DOMAIN_CPU) {
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/* Asking for cpu access wait for object idle */
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2014-05-14 07:40:49 -06:00
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r = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
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if (!r)
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r = -EBUSY;
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if (r < 0 && r != -EINTR) {
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2017-02-28 05:55:52 -07:00
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pr_err("Failed to wait for object: %li\n", r);
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2009-06-05 06:42:42 -06:00
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return r;
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}
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}
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2017-04-02 21:35:23 -06:00
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if (domain == RADEON_GEM_DOMAIN_VRAM && robj->prime_shared_count) {
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/* A BO that is associated with a dma-buf cannot be sensibly migrated to VRAM */
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return -EINVAL;
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}
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2009-06-05 06:42:42 -06:00
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return 0;
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}
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int radeon_gem_init(struct radeon_device *rdev)
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{
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INIT_LIST_HEAD(&rdev->gem.objects);
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return 0;
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}
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void radeon_gem_fini(struct radeon_device *rdev)
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{
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2009-11-20 06:29:23 -07:00
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radeon_bo_force_delete(rdev);
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2009-06-05 06:42:42 -06:00
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}
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drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
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/*
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* Call from drm_gem_handle_create which appear in both new and open ioctl
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* case.
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*/
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int radeon_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
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{
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2012-09-11 08:10:04 -06:00
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struct radeon_bo *rbo = gem_to_radeon_bo(obj);
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struct radeon_device *rdev = rbo->rdev;
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struct radeon_fpriv *fpriv = file_priv->driver_priv;
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struct radeon_vm *vm = &fpriv->vm;
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struct radeon_bo_va *bo_va;
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int r;
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2015-01-28 12:36:26 -07:00
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if ((rdev->family < CHIP_CAYMAN) ||
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(!rdev->accel_working)) {
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2012-09-11 08:10:04 -06:00
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return 0;
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}
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r = radeon_bo_reserve(rbo, false);
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if (r) {
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return r;
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}
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bo_va = radeon_vm_bo_find(vm, rbo);
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if (!bo_va) {
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bo_va = radeon_vm_bo_add(rdev, vm, rbo);
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} else {
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++bo_va->ref_count;
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}
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radeon_bo_unreserve(rbo);
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drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
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return 0;
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}
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void radeon_gem_object_close(struct drm_gem_object *obj,
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struct drm_file *file_priv)
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{
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struct radeon_bo *rbo = gem_to_radeon_bo(obj);
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struct radeon_device *rdev = rbo->rdev;
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struct radeon_fpriv *fpriv = file_priv->driver_priv;
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struct radeon_vm *vm = &fpriv->vm;
|
2012-09-11 08:10:04 -06:00
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struct radeon_bo_va *bo_va;
|
2012-09-11 08:10:02 -06:00
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int r;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
|
2015-01-28 12:36:26 -07:00
|
|
|
if ((rdev->family < CHIP_CAYMAN) ||
|
|
|
|
(!rdev->accel_working)) {
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-09-11 08:10:02 -06:00
|
|
|
r = radeon_bo_reserve(rbo, true);
|
|
|
|
if (r) {
|
|
|
|
dev_err(rdev->dev, "leaking bo va because "
|
|
|
|
"we fail to reserve bo (%d)\n", r);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
return;
|
|
|
|
}
|
2012-09-11 08:10:04 -06:00
|
|
|
bo_va = radeon_vm_bo_find(vm, rbo);
|
|
|
|
if (bo_va) {
|
|
|
|
if (--bo_va->ref_count == 0) {
|
|
|
|
radeon_vm_bo_rmv(rdev, bo_va);
|
|
|
|
}
|
|
|
|
}
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
radeon_bo_unreserve(rbo);
|
|
|
|
}
|
|
|
|
|
2012-05-02 07:11:19 -06:00
|
|
|
static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r)
|
|
|
|
{
|
|
|
|
if (r == -EDEADLK) {
|
|
|
|
r = radeon_gpu_reset(rdev);
|
|
|
|
if (!r)
|
|
|
|
r = -EAGAIN;
|
|
|
|
}
|
|
|
|
return r;
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* GEM ioctls.
|
|
|
|
*/
|
|
|
|
int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
struct drm_radeon_gem_info *args = data;
|
2011-03-13 17:47:24 -06:00
|
|
|
struct ttm_mem_type_manager *man;
|
|
|
|
|
|
|
|
man = &rdev->mman.bdev.man[TTM_PL_VRAM];
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2017-01-29 20:06:35 -07:00
|
|
|
args->vram_size = (u64)man->size << PAGE_SHIFT;
|
|
|
|
args->vram_visible = rdev->mc.visible_vram_size;
|
2014-07-17 10:16:20 -06:00
|
|
|
args->vram_visible -= rdev->vram_pin_size;
|
|
|
|
args->gart_size = rdev->mc.gtt_size;
|
|
|
|
args->gart_size -= rdev->gart_pin_size;
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
/* TODO: implement */
|
|
|
|
DRM_ERROR("unimplemented %s\n", __func__);
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
/* TODO: implement */
|
|
|
|
DRM_ERROR("unimplemented %s\n", __func__);
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
struct drm_radeon_gem_create *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
|
|
|
uint32_t handle;
|
|
|
|
int r;
|
|
|
|
|
2012-07-02 10:45:19 -06:00
|
|
|
down_read(&rdev->exclusive_lock);
|
2009-06-05 06:42:42 -06:00
|
|
|
/* create a gem object to contain this object in */
|
|
|
|
args->size = roundup(args->size, PAGE_SIZE);
|
|
|
|
r = radeon_gem_object_create(rdev, args->size, args->alignment,
|
2014-07-17 04:01:08 -06:00
|
|
|
args->initial_domain, args->flags,
|
2014-07-21 05:27:27 -06:00
|
|
|
false, &gobj);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (r) {
|
2012-07-02 10:45:19 -06:00
|
|
|
up_read(&rdev->exclusive_lock);
|
2012-05-02 07:11:19 -06:00
|
|
|
r = radeon_gem_handle_lockup(rdev, r);
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
r = drm_gem_handle_create(filp, gobj, &handle);
|
2010-09-27 00:17:17 -06:00
|
|
|
/* drop reference from allocate - handle holds it now */
|
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (r) {
|
2012-07-02 10:45:19 -06:00
|
|
|
up_read(&rdev->exclusive_lock);
|
2012-05-02 07:11:19 -06:00
|
|
|
r = radeon_gem_handle_lockup(rdev, r);
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
args->handle = handle;
|
2012-07-02 10:45:19 -06:00
|
|
|
up_read(&rdev->exclusive_lock);
|
2009-06-05 06:42:42 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/radeon: add userptr support v8
This patch adds an IOCTL for turning a pointer supplied by
userspace into a buffer object.
It imposes several restrictions upon the memory being mapped:
1. It must be page aligned (both start/end addresses, i.e ptr and size).
2. It must be normal system memory, not a pointer into another map of IO
space (e.g. it must not be a GTT mmapping of another object).
3. The BO is mapped into GTT, so the maximum amount of memory mapped at
all times is still the GTT limit.
4. The BO is only mapped readonly for now, so no write support.
5. List of backing pages is only acquired once, so they represent a
snapshot of the first use.
Exporting and sharing as well as mapping of buffer objects created by
this function is forbidden and results in an -EPERM.
v2: squash all previous changes into first public version
v3: fix tabs, map readonly, don't use MM callback any more
v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages,
pin/unpin pages on bind/unbind instead of populate/unpopulate
v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown
flags, better handle READONLY flag, improve permission check
v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin
v7: add warning about it's availability in the API definition
v8: drop access_ok check, fix VM mapping bits
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v4)
Reviewed-by: Jérôme Glisse <jglisse@redhat.com> (v4)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-07 01:36:00 -06:00
|
|
|
int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
struct drm_radeon_gem_userptr *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
|
|
|
struct radeon_bo *bo;
|
|
|
|
uint32_t handle;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (offset_in_page(args->addr | args->size))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
/* reject unknown flag values */
|
2014-08-07 01:36:01 -06:00
|
|
|
if (args->flags & ~(RADEON_GEM_USERPTR_READONLY |
|
2014-08-07 01:36:03 -06:00
|
|
|
RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE |
|
|
|
|
RADEON_GEM_USERPTR_REGISTER))
|
drm/radeon: add userptr support v8
This patch adds an IOCTL for turning a pointer supplied by
userspace into a buffer object.
It imposes several restrictions upon the memory being mapped:
1. It must be page aligned (both start/end addresses, i.e ptr and size).
2. It must be normal system memory, not a pointer into another map of IO
space (e.g. it must not be a GTT mmapping of another object).
3. The BO is mapped into GTT, so the maximum amount of memory mapped at
all times is still the GTT limit.
4. The BO is only mapped readonly for now, so no write support.
5. List of backing pages is only acquired once, so they represent a
snapshot of the first use.
Exporting and sharing as well as mapping of buffer objects created by
this function is forbidden and results in an -EPERM.
v2: squash all previous changes into first public version
v3: fix tabs, map readonly, don't use MM callback any more
v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages,
pin/unpin pages on bind/unbind instead of populate/unpopulate
v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown
flags, better handle READONLY flag, improve permission check
v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin
v7: add warning about it's availability in the API definition
v8: drop access_ok check, fix VM mapping bits
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v4)
Reviewed-by: Jérôme Glisse <jglisse@redhat.com> (v4)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-07 01:36:00 -06:00
|
|
|
return -EINVAL;
|
|
|
|
|
2014-08-07 01:36:04 -06:00
|
|
|
if (args->flags & RADEON_GEM_USERPTR_READONLY) {
|
|
|
|
/* readonly pages not tested on older hardware */
|
|
|
|
if (rdev->family < CHIP_R600)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
} else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) ||
|
|
|
|
!(args->flags & RADEON_GEM_USERPTR_REGISTER)) {
|
|
|
|
|
|
|
|
/* if we want to write to it we must require anonymous
|
|
|
|
memory and install a MMU notifier */
|
|
|
|
return -EACCES;
|
|
|
|
}
|
drm/radeon: add userptr support v8
This patch adds an IOCTL for turning a pointer supplied by
userspace into a buffer object.
It imposes several restrictions upon the memory being mapped:
1. It must be page aligned (both start/end addresses, i.e ptr and size).
2. It must be normal system memory, not a pointer into another map of IO
space (e.g. it must not be a GTT mmapping of another object).
3. The BO is mapped into GTT, so the maximum amount of memory mapped at
all times is still the GTT limit.
4. The BO is only mapped readonly for now, so no write support.
5. List of backing pages is only acquired once, so they represent a
snapshot of the first use.
Exporting and sharing as well as mapping of buffer objects created by
this function is forbidden and results in an -EPERM.
v2: squash all previous changes into first public version
v3: fix tabs, map readonly, don't use MM callback any more
v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages,
pin/unpin pages on bind/unbind instead of populate/unpopulate
v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown
flags, better handle READONLY flag, improve permission check
v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin
v7: add warning about it's availability in the API definition
v8: drop access_ok check, fix VM mapping bits
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v4)
Reviewed-by: Jérôme Glisse <jglisse@redhat.com> (v4)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-07 01:36:00 -06:00
|
|
|
|
|
|
|
down_read(&rdev->exclusive_lock);
|
|
|
|
|
|
|
|
/* create a gem object to contain this object in */
|
|
|
|
r = radeon_gem_object_create(rdev, args->size, 0,
|
|
|
|
RADEON_GEM_DOMAIN_CPU, 0,
|
|
|
|
false, &gobj);
|
|
|
|
if (r)
|
|
|
|
goto handle_lockup;
|
|
|
|
|
|
|
|
bo = gem_to_radeon_bo(gobj);
|
|
|
|
r = radeon_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
|
|
|
|
if (r)
|
|
|
|
goto release_object;
|
|
|
|
|
2014-08-07 01:36:03 -06:00
|
|
|
if (args->flags & RADEON_GEM_USERPTR_REGISTER) {
|
|
|
|
r = radeon_mn_register(bo, args->addr);
|
|
|
|
if (r)
|
|
|
|
goto release_object;
|
|
|
|
}
|
|
|
|
|
2014-08-07 01:36:02 -06:00
|
|
|
if (args->flags & RADEON_GEM_USERPTR_VALIDATE) {
|
|
|
|
down_read(¤t->mm->mmap_sem);
|
|
|
|
r = radeon_bo_reserve(bo, true);
|
|
|
|
if (r) {
|
|
|
|
up_read(¤t->mm->mmap_sem);
|
|
|
|
goto release_object;
|
|
|
|
}
|
|
|
|
|
|
|
|
radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT);
|
|
|
|
r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
|
|
|
|
radeon_bo_unreserve(bo);
|
|
|
|
up_read(¤t->mm->mmap_sem);
|
|
|
|
if (r)
|
|
|
|
goto release_object;
|
|
|
|
}
|
|
|
|
|
drm/radeon: add userptr support v8
This patch adds an IOCTL for turning a pointer supplied by
userspace into a buffer object.
It imposes several restrictions upon the memory being mapped:
1. It must be page aligned (both start/end addresses, i.e ptr and size).
2. It must be normal system memory, not a pointer into another map of IO
space (e.g. it must not be a GTT mmapping of another object).
3. The BO is mapped into GTT, so the maximum amount of memory mapped at
all times is still the GTT limit.
4. The BO is only mapped readonly for now, so no write support.
5. List of backing pages is only acquired once, so they represent a
snapshot of the first use.
Exporting and sharing as well as mapping of buffer objects created by
this function is forbidden and results in an -EPERM.
v2: squash all previous changes into first public version
v3: fix tabs, map readonly, don't use MM callback any more
v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages,
pin/unpin pages on bind/unbind instead of populate/unpopulate
v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown
flags, better handle READONLY flag, improve permission check
v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin
v7: add warning about it's availability in the API definition
v8: drop access_ok check, fix VM mapping bits
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v4)
Reviewed-by: Jérôme Glisse <jglisse@redhat.com> (v4)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-07 01:36:00 -06:00
|
|
|
r = drm_gem_handle_create(filp, gobj, &handle);
|
|
|
|
/* drop reference from allocate - handle holds it now */
|
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
|
|
|
if (r)
|
|
|
|
goto handle_lockup;
|
|
|
|
|
|
|
|
args->handle = handle;
|
|
|
|
up_read(&rdev->exclusive_lock);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
release_object:
|
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
|
|
|
|
|
|
|
handle_lockup:
|
|
|
|
up_read(&rdev->exclusive_lock);
|
|
|
|
r = radeon_gem_handle_lockup(rdev, r);
|
|
|
|
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
/* transition the BO to a domain -
|
|
|
|
* just validate the BO into a certain domain */
|
2012-07-02 10:45:19 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2009-06-05 06:42:42 -06:00
|
|
|
struct drm_radeon_gem_set_domain *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
2009-11-20 06:29:23 -07:00
|
|
|
struct radeon_bo *robj;
|
2009-06-05 06:42:42 -06:00
|
|
|
int r;
|
|
|
|
|
|
|
|
/* for now if someone requests domain CPU -
|
|
|
|
* just make sure the buffer is finished with */
|
2012-07-02 10:45:19 -06:00
|
|
|
down_read(&rdev->exclusive_lock);
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/* just do a BO wait for now */
|
2016-05-09 04:04:54 -06:00
|
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (gobj == NULL) {
|
2012-07-02 10:45:19 -06:00
|
|
|
up_read(&rdev->exclusive_lock);
|
2010-08-04 07:19:46 -06:00
|
|
|
return -ENOENT;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2011-02-18 09:59:17 -07:00
|
|
|
robj = gem_to_radeon_bo(gobj);
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);
|
|
|
|
|
2010-02-08 22:49:12 -07:00
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
2012-07-02 10:45:19 -06:00
|
|
|
up_read(&rdev->exclusive_lock);
|
2012-05-02 07:11:19 -06:00
|
|
|
r = radeon_gem_handle_lockup(robj->rdev, r);
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2014-12-23 20:11:17 -07:00
|
|
|
int radeon_mode_dumb_mmap(struct drm_file *filp,
|
|
|
|
struct drm_device *dev,
|
|
|
|
uint32_t handle, uint64_t *offset_p)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
struct drm_gem_object *gobj;
|
2009-11-20 06:29:23 -07:00
|
|
|
struct radeon_bo *robj;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2016-05-09 04:04:54 -06:00
|
|
|
gobj = drm_gem_object_lookup(filp, handle);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (gobj == NULL) {
|
2010-08-04 07:19:46 -06:00
|
|
|
return -ENOENT;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2011-02-18 09:59:17 -07:00
|
|
|
robj = gem_to_radeon_bo(gobj);
|
drm/radeon: add userptr support v8
This patch adds an IOCTL for turning a pointer supplied by
userspace into a buffer object.
It imposes several restrictions upon the memory being mapped:
1. It must be page aligned (both start/end addresses, i.e ptr and size).
2. It must be normal system memory, not a pointer into another map of IO
space (e.g. it must not be a GTT mmapping of another object).
3. The BO is mapped into GTT, so the maximum amount of memory mapped at
all times is still the GTT limit.
4. The BO is only mapped readonly for now, so no write support.
5. List of backing pages is only acquired once, so they represent a
snapshot of the first use.
Exporting and sharing as well as mapping of buffer objects created by
this function is forbidden and results in an -EPERM.
v2: squash all previous changes into first public version
v3: fix tabs, map readonly, don't use MM callback any more
v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages,
pin/unpin pages on bind/unbind instead of populate/unpopulate
v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown
flags, better handle READONLY flag, improve permission check
v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin
v7: add warning about it's availability in the API definition
v8: drop access_ok check, fix VM mapping bits
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v4)
Reviewed-by: Jérôme Glisse <jglisse@redhat.com> (v4)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-07 01:36:00 -06:00
|
|
|
if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) {
|
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
|
|
|
return -EPERM;
|
|
|
|
}
|
2011-02-06 19:16:14 -07:00
|
|
|
*offset_p = radeon_bo_mmap_offset(robj);
|
2010-02-08 22:49:12 -07:00
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
2009-11-20 06:29:23 -07:00
|
|
|
return 0;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2011-02-06 19:16:14 -07:00
|
|
|
int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
struct drm_radeon_gem_mmap *args = data;
|
|
|
|
|
2014-12-23 20:11:17 -07:00
|
|
|
return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr);
|
2011-02-06 19:16:14 -07:00
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
2009-08-16 05:05:45 -06:00
|
|
|
struct drm_radeon_gem_busy *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
2009-11-20 06:29:23 -07:00
|
|
|
struct radeon_bo *robj;
|
2009-08-16 05:05:45 -06:00
|
|
|
int r;
|
2009-12-09 22:59:32 -07:00
|
|
|
uint32_t cur_placement = 0;
|
2009-08-16 05:05:45 -06:00
|
|
|
|
2016-05-09 04:04:54 -06:00
|
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
2009-08-16 05:05:45 -06:00
|
|
|
if (gobj == NULL) {
|
2010-08-04 07:19:46 -06:00
|
|
|
return -ENOENT;
|
2009-08-16 05:05:45 -06:00
|
|
|
}
|
2011-02-18 09:59:17 -07:00
|
|
|
robj = gem_to_radeon_bo(gobj);
|
2015-07-02 17:54:10 -06:00
|
|
|
|
|
|
|
r = reservation_object_test_signaled_rcu(robj->tbo.resv, true);
|
|
|
|
if (r == 0)
|
|
|
|
r = -EBUSY;
|
|
|
|
else
|
|
|
|
r = 0;
|
|
|
|
|
|
|
|
cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type);
|
2014-03-01 16:56:19 -07:00
|
|
|
args->domain = radeon_mem_type_to_domain(cur_placement);
|
2010-02-08 22:49:12 -07:00
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
2009-08-20 17:47:45 -06:00
|
|
|
return r;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
2012-07-02 10:40:54 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2009-06-05 06:42:42 -06:00
|
|
|
struct drm_radeon_gem_wait_idle *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
2009-11-20 06:29:23 -07:00
|
|
|
struct radeon_bo *robj;
|
2014-05-14 07:40:49 -06:00
|
|
|
int r = 0;
|
2014-08-01 02:22:09 -06:00
|
|
|
uint32_t cur_placement = 0;
|
2014-05-14 07:40:49 -06:00
|
|
|
long ret;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2016-05-09 04:04:54 -06:00
|
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
2009-06-05 06:42:42 -06:00
|
|
|
if (gobj == NULL) {
|
2010-08-04 07:19:46 -06:00
|
|
|
return -ENOENT;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2011-02-18 09:59:17 -07:00
|
|
|
robj = gem_to_radeon_bo(gobj);
|
2014-05-14 07:40:49 -06:00
|
|
|
|
|
|
|
ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
|
|
|
|
if (ret == 0)
|
|
|
|
r = -EBUSY;
|
|
|
|
else if (ret < 0)
|
|
|
|
r = ret;
|
|
|
|
|
2014-07-31 03:43:48 -06:00
|
|
|
/* Flush HDP cache via MMIO if necessary */
|
2015-07-02 17:54:11 -06:00
|
|
|
cur_placement = ACCESS_ONCE(robj->tbo.mem.mem_type);
|
2014-08-01 02:22:09 -06:00
|
|
|
if (rdev->asic->mmio_hdp_flush &&
|
|
|
|
radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM)
|
2014-07-31 03:43:48 -06:00
|
|
|
robj->rdev->asic->mmio_hdp_flush(rdev);
|
2010-02-08 22:49:12 -07:00
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
2012-07-02 10:40:54 -06:00
|
|
|
r = radeon_gem_handle_lockup(rdev, r);
|
2009-06-05 06:42:42 -06:00
|
|
|
return r;
|
|
|
|
}
|
2009-06-23 17:48:08 -06:00
|
|
|
|
|
|
|
int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
struct drm_radeon_gem_set_tiling *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
2009-11-20 06:29:23 -07:00
|
|
|
struct radeon_bo *robj;
|
2009-06-23 17:48:08 -06:00
|
|
|
int r = 0;
|
|
|
|
|
|
|
|
DRM_DEBUG("%d \n", args->handle);
|
2016-05-09 04:04:54 -06:00
|
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
2009-06-23 17:48:08 -06:00
|
|
|
if (gobj == NULL)
|
2010-08-04 07:19:46 -06:00
|
|
|
return -ENOENT;
|
2011-02-18 09:59:17 -07:00
|
|
|
robj = gem_to_radeon_bo(gobj);
|
2009-11-20 06:29:23 -07:00
|
|
|
r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
|
2010-02-08 22:49:12 -07:00
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
2009-06-23 17:48:08 -06:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
struct drm_radeon_gem_get_tiling *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
2009-11-20 06:29:23 -07:00
|
|
|
struct radeon_bo *rbo;
|
2009-06-23 17:48:08 -06:00
|
|
|
int r = 0;
|
|
|
|
|
|
|
|
DRM_DEBUG("\n");
|
2016-05-09 04:04:54 -06:00
|
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
2009-06-23 17:48:08 -06:00
|
|
|
if (gobj == NULL)
|
2010-08-04 07:19:46 -06:00
|
|
|
return -ENOENT;
|
2011-02-18 09:59:17 -07:00
|
|
|
rbo = gem_to_radeon_bo(gobj);
|
2009-11-20 06:29:23 -07:00
|
|
|
r = radeon_bo_reserve(rbo, false);
|
|
|
|
if (unlikely(r != 0))
|
2009-12-15 20:10:43 -07:00
|
|
|
goto out;
|
2009-11-20 06:29:23 -07:00
|
|
|
radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
|
|
|
|
radeon_bo_unreserve(rbo);
|
2009-12-15 20:10:43 -07:00
|
|
|
out:
|
2010-02-08 22:49:12 -07:00
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2014-09-12 04:25:45 -06:00
|
|
|
/**
|
|
|
|
* radeon_gem_va_update_vm -update the bo_va in its VM
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @bo_va: bo_va to update
|
|
|
|
*
|
|
|
|
* Update the bo_va directly after setting it's address. Errors are not
|
|
|
|
* vital here, so they are not reported back to userspace.
|
|
|
|
*/
|
|
|
|
static void radeon_gem_va_update_vm(struct radeon_device *rdev,
|
|
|
|
struct radeon_bo_va *bo_va)
|
|
|
|
{
|
|
|
|
struct ttm_validate_buffer tv, *entry;
|
2014-11-27 06:48:42 -07:00
|
|
|
struct radeon_bo_list *vm_bos;
|
2014-09-12 04:25:45 -06:00
|
|
|
struct ww_acquire_ctx ticket;
|
|
|
|
struct list_head list;
|
|
|
|
unsigned domain;
|
|
|
|
int r;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&list);
|
|
|
|
|
|
|
|
tv.bo = &bo_va->bo->tbo;
|
|
|
|
tv.shared = true;
|
|
|
|
list_add(&tv.head, &list);
|
|
|
|
|
|
|
|
vm_bos = radeon_vm_get_bos(rdev, bo_va->vm, &list);
|
|
|
|
if (!vm_bos)
|
|
|
|
return;
|
|
|
|
|
2014-12-03 07:46:48 -07:00
|
|
|
r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
|
2014-09-12 04:25:45 -06:00
|
|
|
if (r)
|
|
|
|
goto error_free;
|
|
|
|
|
|
|
|
list_for_each_entry(entry, &list, head) {
|
|
|
|
domain = radeon_mem_type_to_domain(entry->bo->mem.mem_type);
|
|
|
|
/* if anything is swapped out don't swap it in here,
|
|
|
|
just abort and wait for the next CS */
|
|
|
|
if (domain == RADEON_GEM_DOMAIN_CPU)
|
|
|
|
goto error_unreserve;
|
|
|
|
}
|
|
|
|
|
|
|
|
mutex_lock(&bo_va->vm->mutex);
|
|
|
|
r = radeon_vm_clear_freed(rdev, bo_va->vm);
|
|
|
|
if (r)
|
|
|
|
goto error_unlock;
|
|
|
|
|
|
|
|
if (bo_va->it.start)
|
|
|
|
r = radeon_vm_bo_update(rdev, bo_va, &bo_va->bo->tbo.mem);
|
|
|
|
|
|
|
|
error_unlock:
|
|
|
|
mutex_unlock(&bo_va->vm->mutex);
|
|
|
|
|
|
|
|
error_unreserve:
|
|
|
|
ttm_eu_backoff_reservation(&ticket, &list);
|
|
|
|
|
|
|
|
error_free:
|
2017-05-17 06:23:12 -06:00
|
|
|
kvfree(vm_bos);
|
2014-09-12 04:25:45 -06:00
|
|
|
|
2015-01-09 03:07:49 -07:00
|
|
|
if (r && r != -ERESTARTSYS)
|
2014-09-12 04:25:45 -06:00
|
|
|
DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
|
|
|
|
}
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
struct drm_radeon_gem_va *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
struct radeon_fpriv *fpriv = filp->driver_priv;
|
|
|
|
struct radeon_bo *rbo;
|
|
|
|
struct radeon_bo_va *bo_va;
|
|
|
|
u32 invalid_flags;
|
|
|
|
int r = 0;
|
|
|
|
|
2012-01-06 07:38:15 -07:00
|
|
|
if (!rdev->vm_manager.enabled) {
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
|
|
|
return -ENOTTY;
|
|
|
|
}
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
/* !! DONT REMOVE !!
|
|
|
|
* We don't support vm_id yet, to be sure we don't have have broken
|
|
|
|
* userspace, reject anyone trying to use non 0 value thus moving
|
|
|
|
* forward we can use those fields without breaking existant userspace
|
|
|
|
*/
|
|
|
|
if (args->vm_id) {
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (args->offset < RADEON_VA_RESERVED_SIZE) {
|
|
|
|
dev_err(&dev->pdev->dev,
|
|
|
|
"offset 0x%lX is in reserved area 0x%X\n",
|
|
|
|
(unsigned long)args->offset,
|
|
|
|
RADEON_VA_RESERVED_SIZE);
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* don't remove, we need to enforce userspace to set the snooped flag
|
|
|
|
* otherwise we will endup with broken userspace and we won't be able
|
|
|
|
* to enable this feature without adding new interface
|
|
|
|
*/
|
|
|
|
invalid_flags = RADEON_VM_PAGE_VALID | RADEON_VM_PAGE_SYSTEM;
|
|
|
|
if ((args->flags & invalid_flags)) {
|
|
|
|
dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
|
|
|
|
args->flags, invalid_flags);
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (args->operation) {
|
|
|
|
case RADEON_VA_MAP:
|
|
|
|
case RADEON_VA_UNMAP:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(&dev->pdev->dev, "unsupported operation %d\n",
|
|
|
|
args->operation);
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2016-05-09 04:04:54 -06:00
|
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
if (gobj == NULL) {
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
rbo = gem_to_radeon_bo(gobj);
|
|
|
|
r = radeon_bo_reserve(rbo, false);
|
|
|
|
if (r) {
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
|
|
|
return r;
|
|
|
|
}
|
2012-09-11 08:10:04 -06:00
|
|
|
bo_va = radeon_vm_bo_find(&fpriv->vm, rbo);
|
|
|
|
if (!bo_va) {
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
2016-01-25 08:34:12 -07:00
|
|
|
radeon_bo_unreserve(rbo);
|
2012-09-11 08:10:04 -06:00
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
switch (args->operation) {
|
|
|
|
case RADEON_VA_MAP:
|
2014-07-30 09:49:56 -06:00
|
|
|
if (bo_va->it.start) {
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
args->operation = RADEON_VA_RESULT_VA_EXIST;
|
2014-07-30 09:49:56 -06:00
|
|
|
args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE;
|
2014-11-19 06:01:20 -07:00
|
|
|
radeon_bo_unreserve(rbo);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
goto out;
|
|
|
|
}
|
2012-09-11 08:10:04 -06:00
|
|
|
r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
break;
|
|
|
|
case RADEON_VA_UNMAP:
|
2012-09-11 08:10:04 -06:00
|
|
|
r = radeon_vm_bo_set_addr(rdev, bo_va, 0, 0);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2014-09-12 04:25:45 -06:00
|
|
|
if (!r)
|
|
|
|
radeon_gem_va_update_vm(rdev, bo_va);
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
args->operation = RADEON_VA_RESULT_OK;
|
|
|
|
if (r) {
|
|
|
|
args->operation = RADEON_VA_RESULT_ERROR;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
2009-06-23 17:48:08 -06:00
|
|
|
return r;
|
2014-03-01 16:56:17 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
|
|
|
|
struct drm_file *filp)
|
|
|
|
{
|
|
|
|
struct drm_radeon_gem_op *args = data;
|
|
|
|
struct drm_gem_object *gobj;
|
|
|
|
struct radeon_bo *robj;
|
|
|
|
int r;
|
|
|
|
|
2016-05-09 04:04:54 -06:00
|
|
|
gobj = drm_gem_object_lookup(filp, args->handle);
|
2014-03-01 16:56:17 -07:00
|
|
|
if (gobj == NULL) {
|
|
|
|
return -ENOENT;
|
|
|
|
}
|
|
|
|
robj = gem_to_radeon_bo(gobj);
|
drm/radeon: add userptr support v8
This patch adds an IOCTL for turning a pointer supplied by
userspace into a buffer object.
It imposes several restrictions upon the memory being mapped:
1. It must be page aligned (both start/end addresses, i.e ptr and size).
2. It must be normal system memory, not a pointer into another map of IO
space (e.g. it must not be a GTT mmapping of another object).
3. The BO is mapped into GTT, so the maximum amount of memory mapped at
all times is still the GTT limit.
4. The BO is only mapped readonly for now, so no write support.
5. List of backing pages is only acquired once, so they represent a
snapshot of the first use.
Exporting and sharing as well as mapping of buffer objects created by
this function is forbidden and results in an -EPERM.
v2: squash all previous changes into first public version
v3: fix tabs, map readonly, don't use MM callback any more
v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages,
pin/unpin pages on bind/unbind instead of populate/unpopulate
v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown
flags, better handle READONLY flag, improve permission check
v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin
v7: add warning about it's availability in the API definition
v8: drop access_ok check, fix VM mapping bits
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v4)
Reviewed-by: Jérôme Glisse <jglisse@redhat.com> (v4)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-07 01:36:00 -06:00
|
|
|
|
|
|
|
r = -EPERM;
|
|
|
|
if (radeon_ttm_tt_has_userptr(robj->tbo.ttm))
|
|
|
|
goto out;
|
|
|
|
|
2014-03-01 16:56:17 -07:00
|
|
|
r = radeon_bo_reserve(robj, false);
|
|
|
|
if (unlikely(r))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
switch (args->op) {
|
|
|
|
case RADEON_GEM_OP_GET_INITIAL_DOMAIN:
|
|
|
|
args->value = robj->initial_domain;
|
|
|
|
break;
|
|
|
|
case RADEON_GEM_OP_SET_INITIAL_DOMAIN:
|
|
|
|
robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM |
|
|
|
|
RADEON_GEM_DOMAIN_GTT |
|
|
|
|
RADEON_GEM_DOMAIN_CPU);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
r = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
radeon_bo_unreserve(robj);
|
|
|
|
out:
|
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
|
|
|
return r;
|
2009-06-23 17:48:08 -06:00
|
|
|
}
|
2011-02-06 19:16:14 -07:00
|
|
|
|
|
|
|
int radeon_mode_dumb_create(struct drm_file *file_priv,
|
|
|
|
struct drm_device *dev,
|
|
|
|
struct drm_mode_create_dumb *args)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
struct drm_gem_object *gobj;
|
2011-03-16 21:58:34 -06:00
|
|
|
uint32_t handle;
|
2011-02-06 19:16:14 -07:00
|
|
|
int r;
|
|
|
|
|
2016-10-17 16:41:18 -06:00
|
|
|
args->pitch = radeon_align_pitch(rdev, args->width,
|
|
|
|
DIV_ROUND_UP(args->bpp, 8), 0);
|
2011-02-06 19:16:14 -07:00
|
|
|
args->size = args->pitch * args->height;
|
|
|
|
args->size = ALIGN(args->size, PAGE_SIZE);
|
|
|
|
|
|
|
|
r = radeon_gem_object_create(rdev, args->size, 0,
|
2014-07-17 04:01:08 -06:00
|
|
|
RADEON_GEM_DOMAIN_VRAM, 0,
|
2014-07-21 05:27:27 -06:00
|
|
|
false, &gobj);
|
2011-02-06 19:16:14 -07:00
|
|
|
if (r)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2011-03-16 21:58:34 -06:00
|
|
|
r = drm_gem_handle_create(file_priv, gobj, &handle);
|
|
|
|
/* drop reference from allocate - handle holds it now */
|
|
|
|
drm_gem_object_unreference_unlocked(gobj);
|
2011-02-06 19:16:14 -07:00
|
|
|
if (r) {
|
|
|
|
return r;
|
|
|
|
}
|
2011-03-16 21:58:34 -06:00
|
|
|
args->handle = handle;
|
2011-02-06 19:16:14 -07:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2013-04-25 20:29:27 -06:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
static int radeon_debugfs_gem_info(struct seq_file *m, void *data)
|
|
|
|
{
|
|
|
|
struct drm_info_node *node = (struct drm_info_node *)m->private;
|
|
|
|
struct drm_device *dev = node->minor->dev;
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
struct radeon_bo *rbo;
|
|
|
|
unsigned i = 0;
|
|
|
|
|
|
|
|
mutex_lock(&rdev->gem.mutex);
|
|
|
|
list_for_each_entry(rbo, &rdev->gem.objects, list) {
|
|
|
|
unsigned domain;
|
|
|
|
const char *placement;
|
|
|
|
|
|
|
|
domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type);
|
|
|
|
switch (domain) {
|
|
|
|
case RADEON_GEM_DOMAIN_VRAM:
|
|
|
|
placement = "VRAM";
|
|
|
|
break;
|
|
|
|
case RADEON_GEM_DOMAIN_GTT:
|
|
|
|
placement = " GTT";
|
|
|
|
break;
|
|
|
|
case RADEON_GEM_DOMAIN_CPU:
|
|
|
|
default:
|
|
|
|
placement = " CPU";
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
|
|
|
|
i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20,
|
|
|
|
placement, (unsigned long)rbo->pid);
|
|
|
|
i++;
|
|
|
|
}
|
|
|
|
mutex_unlock(&rdev->gem.mutex);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct drm_info_list radeon_debugfs_gem_list[] = {
|
|
|
|
{"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL},
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
|
|
|
int radeon_gem_debugfs_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|