2009-06-05 06:42:42 -06:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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2012-10-02 11:01:07 -06:00
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#include <drm/drmP.h>
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2009-06-05 06:42:42 -06:00
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#include "radeon.h"
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2012-10-02 11:01:07 -06:00
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#include <drm/radeon_drm.h>
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2012-08-09 08:34:17 -06:00
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#include "radeon_asic.h"
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2009-06-05 06:42:42 -06:00
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2010-01-31 22:38:10 -07:00
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#include <linux/vga_switcheroo.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2012-09-16 22:40:31 -06:00
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#include <linux/pm_runtime.h>
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2014-03-11 13:02:30 -06:00
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2014-07-15 04:53:32 -06:00
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#include "radeon_kfd.h"
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2014-03-11 13:02:30 -06:00
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#if defined(CONFIG_VGA_SWITCHEROO)
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2014-04-10 20:29:01 -06:00
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bool radeon_has_atpx(void);
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2014-03-11 13:02:30 -06:00
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#else
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2014-04-10 20:29:01 -06:00
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static inline bool radeon_has_atpx(void) { return false; }
|
2014-03-11 13:02:30 -06:00
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#endif
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2012-07-17 12:02:34 -06:00
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/**
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* radeon_driver_unload_kms - Main unload function for KMS.
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*
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* @dev: drm dev pointer
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*
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* This is the main unload function for KMS (all asics).
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* It calls radeon_modeset_fini() to tear down the
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* displays, and radeon_device_fini() to tear down
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* the rest of the device (CP, writeback, etc.).
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* Returns 0 on success.
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*/
|
2017-01-06 10:57:31 -07:00
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void radeon_driver_unload_kms(struct drm_device *dev)
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2009-12-09 10:21:55 -07:00
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{
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struct radeon_device *rdev = dev->dev_private;
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if (rdev == NULL)
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2017-01-06 10:57:31 -07:00
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return;
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2012-09-16 22:40:31 -06:00
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2013-04-12 17:15:52 -06:00
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if (rdev->rmmio == NULL)
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goto done_free;
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2012-09-16 22:40:31 -06:00
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2016-06-08 10:47:27 -06:00
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if (radeon_is_px(dev)) {
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pm_runtime_get_sync(dev->dev);
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2016-06-08 10:47:27 -06:00
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pm_runtime_forbid(dev->dev);
|
2016-06-08 10:47:27 -06:00
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}
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2012-09-16 22:40:31 -06:00
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2014-07-15 04:53:32 -06:00
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radeon_kfd_device_fini(rdev);
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2012-07-31 15:14:35 -06:00
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radeon_acpi_fini(rdev);
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2012-09-16 22:40:31 -06:00
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2009-12-09 10:21:55 -07:00
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radeon_modeset_fini(rdev);
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radeon_device_fini(rdev);
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2013-04-12 17:15:52 -06:00
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done_free:
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2009-12-09 10:21:55 -07:00
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kfree(rdev);
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dev->dev_private = NULL;
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}
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2009-06-05 06:42:42 -06:00
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2012-07-17 12:02:34 -06:00
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/**
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* radeon_driver_load_kms - Main load function for KMS.
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*
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* @dev: drm dev pointer
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* @flags: device flags
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*
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* This is the main load function for KMS (all asics).
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* It calls radeon_device_init() to set up the non-display
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* parts of the chip (asic init, CP, writeback, etc.), and
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* radeon_modeset_init() to set up the display parts
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* (crtcs, encoders, hotplug detect, etc.).
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* Returns 0 on success, error on failure.
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*/
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2009-06-05 06:42:42 -06:00
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
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{
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struct radeon_device *rdev;
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2010-07-06 09:40:24 -06:00
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int r, acpi_status;
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2009-06-05 06:42:42 -06:00
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rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
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if (rdev == NULL) {
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return -ENOMEM;
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}
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dev->dev_private = (void *)rdev;
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/* update BUS flag */
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2017-01-24 23:26:52 -07:00
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if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP)) {
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2009-06-05 06:42:42 -06:00
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flags |= RADEON_IS_AGP;
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2011-06-27 10:07:50 -06:00
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} else if (pci_is_pcie(dev->pdev)) {
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2009-06-05 06:42:42 -06:00
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flags |= RADEON_IS_PCIE;
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} else {
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flags |= RADEON_IS_PCI;
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}
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2014-04-15 10:44:35 -06:00
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if ((radeon_runtime_pm != 0) &&
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radeon_has_atpx() &&
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2017-03-10 13:23:45 -07:00
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((flags & RADEON_IS_IGP) == 0) &&
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2017-05-18 13:33:44 -06:00
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!pci_is_thunderbolt_attached(dev->pdev))
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2014-04-10 20:29:01 -06:00
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flags |= RADEON_IS_PX;
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2009-09-10 13:46:48 -06:00
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/* radeon_device_init should report only fatal error
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* like memory allocation failure or iomapping failure,
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* or memory manager initialization failure, it must
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* properly initialize the GPU MC controller and permit
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* VRAM allocation
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*/
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2009-06-05 06:42:42 -06:00
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r = radeon_device_init(rdev, dev, dev->pdev, flags);
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if (r) {
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2009-12-09 10:21:55 -07:00
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dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
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goto out;
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2009-09-10 13:46:48 -06:00
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}
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2010-07-06 09:40:24 -06:00
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2009-09-10 13:46:48 -06:00
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/* Again modeset_init should fail only on fatal error
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* otherwise it should provide enough functionalities
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* for shadowfb to run
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*/
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r = radeon_modeset_init(rdev);
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2009-12-09 10:21:55 -07:00
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if (r)
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dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
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2012-07-30 13:20:35 -06:00
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/* Call ACPI methods: require modeset init
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* but failure is not fatal
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*/
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if (!r) {
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acpi_status = radeon_acpi_init(rdev);
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if (acpi_status)
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dev_dbg(&dev->pdev->dev,
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"Error during ACPI methods call\n");
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}
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|
2014-07-15 04:53:32 -06:00
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radeon_kfd_device_probe(rdev);
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radeon_kfd_device_init(rdev);
|
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|
2014-04-10 20:29:01 -06:00
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if (radeon_is_px(dev)) {
|
2012-09-16 22:40:31 -06:00
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pm_runtime_use_autosuspend(dev->dev);
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pm_runtime_set_autosuspend_delay(dev->dev, 5000);
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pm_runtime_set_active(dev->dev);
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pm_runtime_allow(dev->dev);
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pm_runtime_mark_last_busy(dev->dev);
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pm_runtime_put_autosuspend(dev->dev);
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}
|
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|
2009-12-09 10:21:55 -07:00
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out:
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if (r)
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radeon_driver_unload_kms(dev);
|
2012-09-16 22:40:31 -06:00
|
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2009-12-09 10:21:55 -07:00
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return r;
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2009-06-05 06:42:42 -06:00
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}
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|
2012-07-17 12:02:34 -06:00
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/**
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|
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* radeon_set_filp_rights - Set filp right.
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*
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* @dev: drm dev pointer
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* @owner: drm file
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* @applier: drm file
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* @value: value
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*
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* Sets the filp rights for the device (all asics).
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*/
|
2011-01-04 21:46:48 -07:00
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static void radeon_set_filp_rights(struct drm_device *dev,
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struct drm_file **owner,
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struct drm_file *applier,
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uint32_t *value)
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|
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{
|
2015-10-15 01:36:34 -06:00
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struct radeon_device *rdev = dev->dev_private;
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mutex_lock(&rdev->gem.mutex);
|
2011-01-04 21:46:48 -07:00
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if (*value == 1) {
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/* wants rights */
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if (!*owner)
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*owner = applier;
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|
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} else if (*value == 0) {
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|
|
|
/* revokes rights */
|
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|
|
if (*owner == applier)
|
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|
|
*owner = NULL;
|
|
|
|
}
|
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*value = *owner == applier ? 1 : 0;
|
2015-10-15 01:36:34 -06:00
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|
|
mutex_unlock(&rdev->gem.mutex);
|
2011-01-04 21:46:48 -07:00
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/*
|
2011-01-04 21:46:48 -07:00
|
|
|
* Userspace get information ioctl
|
2009-06-05 06:42:42 -06:00
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*/
|
2012-07-17 12:02:34 -06:00
|
|
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/**
|
|
|
|
* radeon_info_ioctl - answer a device specific request.
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
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* @data: request object
|
|
|
|
* @filp: drm filp
|
|
|
|
*
|
|
|
|
* This function is used to pass device specific parameters to the userspace
|
|
|
|
* drivers. Examples include: pci device id, pipeline parms, tiling params,
|
|
|
|
* etc. (all asics).
|
|
|
|
* Returns 0 on success, -EINVAL on failure.
|
|
|
|
*/
|
2014-01-06 08:23:07 -07:00
|
|
|
static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2012-08-09 08:34:17 -06:00
|
|
|
struct drm_radeon_info *info = data;
|
2010-05-12 10:01:13 -06:00
|
|
|
struct radeon_mode_info *minfo = &rdev->mode_info;
|
2013-04-09 09:17:08 -06:00
|
|
|
uint32_t *value, value_tmp, *value_ptr, value_size;
|
|
|
|
uint64_t value64;
|
2010-05-12 10:01:13 -06:00
|
|
|
struct drm_crtc *crtc;
|
|
|
|
int i, found;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
value_ptr = (uint32_t *)((unsigned long)info->value);
|
2013-04-09 09:17:08 -06:00
|
|
|
value = &value_tmp;
|
|
|
|
value_size = sizeof(uint32_t);
|
2010-08-01 17:43:52 -06:00
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
switch (info->request) {
|
|
|
|
case RADEON_INFO_DEVICE_ID:
|
2013-10-04 05:53:40 -06:00
|
|
|
*value = dev->pdev->device;
|
2009-06-05 06:42:42 -06:00
|
|
|
break;
|
|
|
|
case RADEON_INFO_NUM_GB_PIPES:
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->num_gb_pipes;
|
2009-06-05 06:42:42 -06:00
|
|
|
break;
|
2009-08-19 17:11:39 -06:00
|
|
|
case RADEON_INFO_NUM_Z_PIPES:
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->num_z_pipes;
|
2009-08-19 17:11:39 -06:00
|
|
|
break;
|
2009-09-16 07:24:21 -06:00
|
|
|
case RADEON_INFO_ACCEL_WORKING:
|
2010-06-03 17:00:03 -06:00
|
|
|
/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
|
|
|
|
if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = false;
|
2010-06-03 17:00:03 -06:00
|
|
|
else
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->accel_working;
|
2009-09-16 07:24:21 -06:00
|
|
|
break;
|
2010-05-12 10:01:13 -06:00
|
|
|
case RADEON_INFO_CRTC_FROM_ID:
|
2013-12-11 03:34:44 -07:00
|
|
|
if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
|
2013-04-09 09:17:08 -06:00
|
|
|
DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
2010-05-12 10:01:13 -06:00
|
|
|
for (i = 0, found = 0; i < rdev->num_crtc; i++) {
|
|
|
|
crtc = (struct drm_crtc *)minfo->crtcs[i];
|
2013-04-09 09:17:08 -06:00
|
|
|
if (crtc && crtc->base.id == *value) {
|
2010-07-21 12:05:35 -06:00
|
|
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = radeon_crtc->crtc_id;
|
2010-05-12 10:01:13 -06:00
|
|
|
found = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (!found) {
|
2013-04-09 09:17:08 -06:00
|
|
|
DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
|
2010-05-12 10:01:13 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2010-06-03 17:00:03 -06:00
|
|
|
case RADEON_INFO_ACCEL_WORKING2:
|
2014-08-01 12:05:30 -06:00
|
|
|
if (rdev->family == CHIP_HAWAII) {
|
2014-08-01 12:05:32 -06:00
|
|
|
if (rdev->accel_working) {
|
|
|
|
if (rdev->new_fw)
|
|
|
|
*value = 3;
|
|
|
|
else
|
|
|
|
*value = 2;
|
|
|
|
} else {
|
2014-08-01 12:05:30 -06:00
|
|
|
*value = 0;
|
2014-08-01 12:05:32 -06:00
|
|
|
}
|
2014-08-01 12:05:30 -06:00
|
|
|
} else {
|
|
|
|
*value = rdev->accel_working;
|
|
|
|
}
|
2010-06-03 17:00:03 -06:00
|
|
|
break;
|
2010-06-04 11:10:12 -06:00
|
|
|
case RADEON_INFO_TILING_CONFIG:
|
2012-07-06 15:40:32 -06:00
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
*value = rdev->config.cik.tile_config;
|
|
|
|
else if (rdev->family >= CHIP_TAHITI)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.si.tile_config;
|
2012-03-20 15:18:26 -06:00
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.cayman.tile_config;
|
2011-03-02 18:07:29 -07:00
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.evergreen.tile_config;
|
2010-06-04 11:10:12 -06:00
|
|
|
else if (rdev->family >= CHIP_RV770)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.rv770.tile_config;
|
2010-06-04 11:10:12 -06:00
|
|
|
else if (rdev->family >= CHIP_R600)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.r600.tile_config;
|
2010-06-04 11:10:12 -06:00
|
|
|
else {
|
2010-08-01 18:42:55 -06:00
|
|
|
DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
|
2010-06-04 11:10:12 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2010-08-12 06:25:47 -06:00
|
|
|
break;
|
2010-07-12 19:11:11 -06:00
|
|
|
case RADEON_INFO_WANT_HYPERZ:
|
2010-08-06 19:36:34 -06:00
|
|
|
/* The "value" here is both an input and output parameter.
|
|
|
|
* If the input value is 1, filp requests hyper-z access.
|
|
|
|
* If the input value is 0, filp revokes its hyper-z access.
|
|
|
|
*
|
|
|
|
* When returning, the value is 1 if filp owns hyper-z access,
|
|
|
|
* 0 otherwise. */
|
2013-12-11 03:34:44 -07:00
|
|
|
if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
|
2013-04-09 09:17:08 -06:00
|
|
|
DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
if (*value >= 2) {
|
|
|
|
DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
|
2010-08-06 19:36:34 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2013-04-09 09:17:08 -06:00
|
|
|
radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
|
2011-01-04 21:46:48 -07:00
|
|
|
break;
|
|
|
|
case RADEON_INFO_WANT_CMASK:
|
|
|
|
/* The same logic as Hyper-Z. */
|
2013-12-11 03:34:44 -07:00
|
|
|
if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
|
2013-04-09 09:17:08 -06:00
|
|
|
DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
if (*value >= 2) {
|
|
|
|
DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
|
2011-01-04 21:46:48 -07:00
|
|
|
return -EINVAL;
|
2010-07-12 19:11:11 -06:00
|
|
|
}
|
2013-04-09 09:17:08 -06:00
|
|
|
radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
|
2010-06-04 11:10:12 -06:00
|
|
|
break;
|
2011-01-24 15:14:26 -07:00
|
|
|
case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
|
|
|
|
/* return clock value in KHz */
|
2013-02-14 08:04:02 -07:00
|
|
|
if (rdev->asic->get_xclk)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = radeon_get_xclk(rdev) * 10;
|
2013-02-14 08:04:02 -07:00
|
|
|
else
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->clock.spll.reference_freq * 10;
|
2011-01-24 15:14:26 -07:00
|
|
|
break;
|
2011-02-28 21:32:27 -07:00
|
|
|
case RADEON_INFO_NUM_BACKENDS:
|
2012-07-06 15:40:32 -06:00
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
*value = rdev->config.cik.max_backends_per_se *
|
|
|
|
rdev->config.cik.max_shader_engines;
|
|
|
|
else if (rdev->family >= CHIP_TAHITI)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.si.max_backends_per_se *
|
2012-03-20 15:18:26 -06:00
|
|
|
rdev->config.si.max_shader_engines;
|
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.cayman.max_backends_per_se *
|
2011-03-02 18:07:29 -07:00
|
|
|
rdev->config.cayman.max_shader_engines;
|
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.evergreen.max_backends;
|
2011-02-28 21:32:27 -07:00
|
|
|
else if (rdev->family >= CHIP_RV770)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.rv770.max_backends;
|
2011-02-28 21:32:27 -07:00
|
|
|
else if (rdev->family >= CHIP_R600)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.r600.max_backends;
|
2011-02-28 21:32:27 -07:00
|
|
|
else {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2011-04-26 11:27:43 -06:00
|
|
|
case RADEON_INFO_NUM_TILE_PIPES:
|
2012-07-06 15:40:32 -06:00
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
*value = rdev->config.cik.max_tile_pipes;
|
|
|
|
else if (rdev->family >= CHIP_TAHITI)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.si.max_tile_pipes;
|
2012-03-20 15:18:26 -06:00
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.cayman.max_tile_pipes;
|
2011-04-26 11:27:43 -06:00
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.evergreen.max_tile_pipes;
|
2011-04-26 11:27:43 -06:00
|
|
|
else if (rdev->family >= CHIP_RV770)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.rv770.max_tile_pipes;
|
2011-04-26 11:27:43 -06:00
|
|
|
else if (rdev->family >= CHIP_R600)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.r600.max_tile_pipes;
|
2011-04-26 11:27:43 -06:00
|
|
|
else {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2011-05-03 17:28:02 -06:00
|
|
|
case RADEON_INFO_FUSION_GART_WORKING:
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = 1;
|
2011-05-03 17:28:02 -06:00
|
|
|
break;
|
2011-07-15 13:53:52 -06:00
|
|
|
case RADEON_INFO_BACKEND_MAP:
|
2012-07-06 15:40:32 -06:00
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
2013-11-18 02:25:59 -07:00
|
|
|
*value = rdev->config.cik.backend_map;
|
2012-07-06 15:40:32 -06:00
|
|
|
else if (rdev->family >= CHIP_TAHITI)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.si.backend_map;
|
2012-03-20 15:18:26 -06:00
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.cayman.backend_map;
|
2011-07-15 13:53:52 -06:00
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.evergreen.backend_map;
|
2011-07-15 13:53:52 -06:00
|
|
|
else if (rdev->family >= CHIP_RV770)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.rv770.backend_map;
|
2011-07-15 13:53:52 -06:00
|
|
|
else if (rdev->family >= CHIP_R600)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.r600.backend_map;
|
2011-07-15 13:53:52 -06:00
|
|
|
else {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
case RADEON_INFO_VA_START:
|
|
|
|
/* this is where we report if vm is supported or not */
|
|
|
|
if (rdev->family < CHIP_CAYMAN)
|
|
|
|
return -EINVAL;
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = RADEON_VA_RESERVED_SIZE;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
break;
|
|
|
|
case RADEON_INFO_IB_VM_MAX_SIZE:
|
|
|
|
/* this is where we report if vm is supported or not */
|
|
|
|
if (rdev->family < CHIP_CAYMAN)
|
|
|
|
return -EINVAL;
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = RADEON_IB_VM_MAX_SIZE;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
break;
|
2012-03-20 15:17:55 -06:00
|
|
|
case RADEON_INFO_MAX_PIPES:
|
2012-07-06 15:40:32 -06:00
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
*value = rdev->config.cik.max_cu_per_sh;
|
|
|
|
else if (rdev->family >= CHIP_TAHITI)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.si.max_cu_per_sh;
|
2012-03-20 15:18:26 -06:00
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.cayman.max_pipes_per_simd;
|
2012-03-20 15:17:55 -06:00
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.evergreen.max_pipes;
|
2012-03-20 15:17:55 -06:00
|
|
|
else if (rdev->family >= CHIP_RV770)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.rv770.max_pipes;
|
2012-03-20 15:17:55 -06:00
|
|
|
else if (rdev->family >= CHIP_R600)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.r600.max_pipes;
|
2012-03-20 15:17:55 -06:00
|
|
|
else {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2013-04-09 09:17:08 -06:00
|
|
|
case RADEON_INFO_TIMESTAMP:
|
|
|
|
if (rdev->family < CHIP_R600) {
|
|
|
|
DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
value = (uint32_t*)&value64;
|
|
|
|
value_size = sizeof(uint64_t);
|
|
|
|
value64 = radeon_get_gpu_clock_counter(rdev);
|
|
|
|
break;
|
2012-12-04 10:55:37 -07:00
|
|
|
case RADEON_INFO_MAX_SE:
|
2012-07-06 15:40:32 -06:00
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
*value = rdev->config.cik.max_shader_engines;
|
|
|
|
else if (rdev->family >= CHIP_TAHITI)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.si.max_shader_engines;
|
2012-12-04 10:55:37 -07:00
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.cayman.max_shader_engines;
|
2012-12-04 10:55:37 -07:00
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.evergreen.num_ses;
|
2012-12-04 10:55:37 -07:00
|
|
|
else
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = 1;
|
2012-12-04 10:55:37 -07:00
|
|
|
break;
|
|
|
|
case RADEON_INFO_MAX_SH_PER_SE:
|
2012-07-06 15:40:32 -06:00
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
*value = rdev->config.cik.max_sh_per_se;
|
|
|
|
else if (rdev->family >= CHIP_TAHITI)
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->config.si.max_sh_per_se;
|
2012-12-04 10:55:37 -07:00
|
|
|
else
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
2013-04-08 15:25:47 -06:00
|
|
|
case RADEON_INFO_FASTFB_WORKING:
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->fastfb_working;
|
2013-04-08 15:25:47 -06:00
|
|
|
break;
|
2013-04-09 08:35:42 -06:00
|
|
|
case RADEON_INFO_RING_WORKING:
|
2013-12-11 03:34:44 -07:00
|
|
|
if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
|
2013-04-09 09:17:08 -06:00
|
|
|
DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
switch (*value) {
|
2013-04-09 08:35:42 -06:00
|
|
|
case RADEON_CS_RING_GFX:
|
|
|
|
case RADEON_CS_RING_COMPUTE:
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
|
2013-04-09 08:35:42 -06:00
|
|
|
break;
|
|
|
|
case RADEON_CS_RING_DMA:
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
|
|
|
|
*value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
|
2013-04-09 08:35:42 -06:00
|
|
|
break;
|
|
|
|
case RADEON_CS_RING_UVD:
|
2013-04-09 09:17:08 -06:00
|
|
|
*value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
|
2013-04-09 08:35:42 -06:00
|
|
|
break;
|
2014-01-27 10:16:06 -07:00
|
|
|
case RADEON_CS_RING_VCE:
|
|
|
|
*value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
|
|
|
|
break;
|
2013-04-09 08:35:42 -06:00
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2013-04-09 09:17:08 -06:00
|
|
|
case RADEON_INFO_SI_TILE_MODE_ARRAY:
|
2012-07-06 15:40:32 -06:00
|
|
|
if (rdev->family >= CHIP_BONAIRE) {
|
2013-04-10 11:41:25 -06:00
|
|
|
value = rdev->config.cik.tile_mode_array;
|
|
|
|
value_size = sizeof(uint32_t)*32;
|
|
|
|
} else if (rdev->family >= CHIP_TAHITI) {
|
|
|
|
value = rdev->config.si.tile_mode_array;
|
|
|
|
value_size = sizeof(uint32_t)*32;
|
|
|
|
} else {
|
|
|
|
DRM_DEBUG_KMS("tile mode array is si+ only!\n");
|
2012-07-06 15:40:32 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2013-04-09 09:17:08 -06:00
|
|
|
break;
|
2013-11-18 02:26:00 -07:00
|
|
|
case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
|
|
|
|
if (rdev->family >= CHIP_BONAIRE) {
|
|
|
|
value = rdev->config.cik.macrotile_mode_array;
|
|
|
|
value_size = sizeof(uint32_t)*16;
|
|
|
|
} else {
|
|
|
|
DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
break;
|
2013-08-16 15:47:39 -06:00
|
|
|
case RADEON_INFO_SI_CP_DMA_COMPUTE:
|
|
|
|
*value = 1;
|
|
|
|
break;
|
2013-12-21 18:18:01 -07:00
|
|
|
case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
|
|
|
|
if (rdev->family >= CHIP_BONAIRE) {
|
|
|
|
*value = rdev->config.cik.backend_enable_mask;
|
|
|
|
} else if (rdev->family >= CHIP_TAHITI) {
|
|
|
|
*value = rdev->config.si.backend_enable_mask;
|
|
|
|
} else {
|
|
|
|
DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
|
|
|
|
}
|
|
|
|
break;
|
2014-01-20 16:20:29 -07:00
|
|
|
case RADEON_INFO_MAX_SCLK:
|
|
|
|
if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
|
|
|
|
rdev->pm.dpm_enabled)
|
|
|
|
*value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
|
|
|
|
else
|
|
|
|
*value = rdev->pm.default_sclk * 10;
|
|
|
|
break;
|
2014-01-23 09:50:49 -07:00
|
|
|
case RADEON_INFO_VCE_FW_VERSION:
|
|
|
|
*value = rdev->vce.fw_version;
|
|
|
|
break;
|
|
|
|
case RADEON_INFO_VCE_FB_VERSION:
|
|
|
|
*value = rdev->vce.fb_version;
|
|
|
|
break;
|
2014-03-01 16:56:18 -07:00
|
|
|
case RADEON_INFO_NUM_BYTES_MOVED:
|
|
|
|
value = (uint32_t*)&value64;
|
|
|
|
value_size = sizeof(uint64_t);
|
|
|
|
value64 = atomic64_read(&rdev->num_bytes_moved);
|
|
|
|
break;
|
|
|
|
case RADEON_INFO_VRAM_USAGE:
|
|
|
|
value = (uint32_t*)&value64;
|
|
|
|
value_size = sizeof(uint64_t);
|
|
|
|
value64 = atomic64_read(&rdev->vram_usage);
|
|
|
|
break;
|
|
|
|
case RADEON_INFO_GTT_USAGE:
|
|
|
|
value = (uint32_t*)&value64;
|
|
|
|
value_size = sizeof(uint64_t);
|
|
|
|
value64 = atomic64_read(&rdev->gtt_usage);
|
|
|
|
break;
|
2014-06-02 14:13:21 -06:00
|
|
|
case RADEON_INFO_ACTIVE_CU_COUNT:
|
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
*value = rdev->config.cik.active_cus;
|
|
|
|
else if (rdev->family >= CHIP_TAHITI)
|
|
|
|
*value = rdev->config.si.active_cus;
|
|
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
|
|
|
*value = rdev->config.cayman.active_simds;
|
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
|
|
|
*value = rdev->config.evergreen.active_simds;
|
|
|
|
else if (rdev->family >= CHIP_RV770)
|
|
|
|
*value = rdev->config.rv770.active_simds;
|
|
|
|
else if (rdev->family >= CHIP_R600)
|
|
|
|
*value = rdev->config.r600.active_simds;
|
|
|
|
else
|
|
|
|
*value = 1;
|
|
|
|
break;
|
2014-09-30 08:04:40 -06:00
|
|
|
case RADEON_INFO_CURRENT_GPU_TEMP:
|
|
|
|
/* get temperature in millidegrees C */
|
|
|
|
if (rdev->asic->pm.get_temperature)
|
|
|
|
*value = radeon_get_temperature(rdev);
|
|
|
|
else
|
|
|
|
*value = 0;
|
|
|
|
break;
|
2014-09-30 09:33:30 -06:00
|
|
|
case RADEON_INFO_CURRENT_GPU_SCLK:
|
|
|
|
/* get sclk in Mhz */
|
|
|
|
if (rdev->pm.dpm_enabled)
|
|
|
|
*value = radeon_dpm_get_current_sclk(rdev) / 100;
|
|
|
|
else
|
|
|
|
*value = rdev->pm.current_sclk / 100;
|
|
|
|
break;
|
|
|
|
case RADEON_INFO_CURRENT_GPU_MCLK:
|
|
|
|
/* get mclk in Mhz */
|
|
|
|
if (rdev->pm.dpm_enabled)
|
|
|
|
*value = radeon_dpm_get_current_mclk(rdev) / 100;
|
|
|
|
else
|
|
|
|
*value = rdev->pm.current_mclk / 100;
|
|
|
|
break;
|
2014-10-01 09:26:50 -06:00
|
|
|
case RADEON_INFO_READ_REG:
|
|
|
|
if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
|
|
|
|
DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
if (radeon_get_allowed_info_register(rdev, *value, value))
|
|
|
|
return -EINVAL;
|
|
|
|
break;
|
2015-06-16 02:28:16 -06:00
|
|
|
case RADEON_INFO_VA_UNMAP_WORKING:
|
|
|
|
*value = true;
|
|
|
|
break;
|
2015-04-29 11:40:33 -06:00
|
|
|
case RADEON_INFO_GPU_RESET_COUNTER:
|
|
|
|
*value = atomic_read(&rdev->gpu_reset_counter);
|
|
|
|
break;
|
2009-06-05 06:42:42 -06:00
|
|
|
default:
|
2010-08-01 18:42:55 -06:00
|
|
|
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
|
2009-06-05 06:42:42 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2013-12-11 03:34:44 -07:00
|
|
|
if (copy_to_user(value_ptr, (char*)value, value_size)) {
|
2012-08-09 08:34:17 -06:00
|
|
|
DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
|
2009-06-05 06:42:42 -06:00
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Outdated mess for old drm with Xorg being in charge (void function now).
|
|
|
|
*/
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
2015-10-02 14:52:58 -06:00
|
|
|
* radeon_driver_lastclose_kms - drm callback for last close
|
2012-07-17 12:02:34 -06:00
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
*
|
2015-09-05 03:14:43 -06:00
|
|
|
* Switch vga_switcheroo state after last close (all asics).
|
2012-07-17 12:02:34 -06:00
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_driver_lastclose_kms(struct drm_device *dev)
|
|
|
|
{
|
2015-10-02 14:52:58 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
|
|
|
radeon_fbdev_restore_mode(rdev);
|
2010-01-31 22:38:10 -07:00
|
|
|
vga_switcheroo_process_delayed_switch();
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_driver_open_kms - drm callback for open
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @file_priv: drm file
|
|
|
|
*
|
|
|
|
* On device open, init vm on cayman+ (all asics).
|
|
|
|
* Returns 0 on success, error on failure.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|
|
|
{
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2012-09-16 22:40:31 -06:00
|
|
|
int r;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
|
|
|
|
file_priv->driver_priv = NULL;
|
|
|
|
|
2012-09-16 22:40:31 -06:00
|
|
|
r = pm_runtime_get_sync(dev->dev);
|
|
|
|
if (r < 0)
|
|
|
|
return r;
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
/* new gpu have virtual address space support */
|
|
|
|
if (rdev->family >= CHIP_CAYMAN) {
|
|
|
|
struct radeon_fpriv *fpriv;
|
2014-07-18 05:48:10 -06:00
|
|
|
struct radeon_vm *vm;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
|
|
|
|
fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
|
|
|
|
if (unlikely(!fpriv)) {
|
2016-08-31 15:27:03 -06:00
|
|
|
r = -ENOMEM;
|
|
|
|
goto out_suspend;
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
}
|
|
|
|
|
2014-05-07 14:35:24 -06:00
|
|
|
if (rdev->accel_working) {
|
2015-01-28 12:36:26 -07:00
|
|
|
vm = &fpriv->vm;
|
|
|
|
r = radeon_vm_init(rdev, vm);
|
|
|
|
if (r) {
|
|
|
|
kfree(fpriv);
|
2016-08-31 15:27:03 -06:00
|
|
|
goto out_suspend;
|
2015-01-28 12:36:26 -07:00
|
|
|
}
|
|
|
|
|
2014-05-07 14:35:24 -06:00
|
|
|
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
|
|
|
if (r) {
|
2014-07-18 05:48:10 -06:00
|
|
|
radeon_vm_fini(rdev, vm);
|
2014-05-07 14:35:24 -06:00
|
|
|
kfree(fpriv);
|
2016-08-31 15:27:03 -06:00
|
|
|
goto out_suspend;
|
2014-05-07 14:35:24 -06:00
|
|
|
}
|
2014-02-20 09:34:06 -07:00
|
|
|
|
2014-05-07 14:35:24 -06:00
|
|
|
/* map the ib pool buffer read only into
|
|
|
|
* virtual address space */
|
2014-07-18 05:48:10 -06:00
|
|
|
vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
|
|
|
|
rdev->ring_tmp_bo.bo);
|
|
|
|
r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
|
|
|
|
RADEON_VA_IB_OFFSET,
|
2014-05-07 14:35:24 -06:00
|
|
|
RADEON_VM_PAGE_READABLE |
|
|
|
|
RADEON_VM_PAGE_SNOOPED);
|
|
|
|
if (r) {
|
2014-07-18 05:48:10 -06:00
|
|
|
radeon_vm_fini(rdev, vm);
|
2014-05-07 14:35:24 -06:00
|
|
|
kfree(fpriv);
|
2016-08-31 15:27:03 -06:00
|
|
|
goto out_suspend;
|
2014-05-07 14:35:24 -06:00
|
|
|
}
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
}
|
|
|
|
file_priv->driver_priv = fpriv;
|
|
|
|
}
|
2012-09-16 22:40:31 -06:00
|
|
|
|
2016-08-31 15:27:03 -06:00
|
|
|
out_suspend:
|
2012-09-16 22:40:31 -06:00
|
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
|
|
pm_runtime_put_autosuspend(dev->dev);
|
2016-08-31 15:27:03 -06:00
|
|
|
return r;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_driver_postclose_kms - drm callback for post close
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @file_priv: drm file
|
|
|
|
*
|
2017-03-08 07:12:48 -07:00
|
|
|
* On device close, tear down hyperz and cmask filps on r1xx-r5xx
|
|
|
|
* (all asics). And tear down vm on cayman+ (all asics).
|
2012-07-17 12:02:34 -06:00
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_driver_postclose_kms(struct drm_device *dev,
|
|
|
|
struct drm_file *file_priv)
|
|
|
|
{
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
2017-03-08 07:12:48 -07:00
|
|
|
pm_runtime_get_sync(dev->dev);
|
|
|
|
|
|
|
|
mutex_lock(&rdev->gem.mutex);
|
|
|
|
if (rdev->hyperz_filp == file_priv)
|
|
|
|
rdev->hyperz_filp = NULL;
|
|
|
|
if (rdev->cmask_filp == file_priv)
|
|
|
|
rdev->cmask_filp = NULL;
|
|
|
|
mutex_unlock(&rdev->gem.mutex);
|
|
|
|
|
|
|
|
radeon_uvd_free_handles(rdev, file_priv);
|
|
|
|
radeon_vce_free_handles(rdev, file_priv);
|
|
|
|
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
/* new gpu have virtual address space support */
|
|
|
|
if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
|
|
|
|
struct radeon_fpriv *fpriv = file_priv->driver_priv;
|
2014-07-18 05:48:10 -06:00
|
|
|
struct radeon_vm *vm = &fpriv->vm;
|
2012-10-09 05:31:18 -06:00
|
|
|
int r;
|
|
|
|
|
2014-05-07 14:35:24 -06:00
|
|
|
if (rdev->accel_working) {
|
|
|
|
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
|
|
|
if (!r) {
|
2014-07-18 05:48:10 -06:00
|
|
|
if (vm->ib_bo_va)
|
|
|
|
radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
|
2014-05-07 14:35:24 -06:00
|
|
|
radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
|
|
|
|
}
|
2015-01-28 12:36:26 -07:00
|
|
|
radeon_vm_fini(rdev, vm);
|
2012-10-09 05:31:18 -06:00
|
|
|
}
|
drm/radeon: GPU virtual memory support v22
Virtual address space are per drm client (opener of /dev/drm).
Client are in charge of virtual address space, they need to
map bo into it by calling DRM_RADEON_GEM_VA ioctl.
First 16M of virtual address space is reserved by the kernel.
Once using 2 level page table we should be able to have a small
vram memory footprint for each pt (there would be one pt for all
gart, one for all vram and then one first level for each virtual
address space).
Plan include using the sub allocator for a common vm page table
area and using memcpy to copy vm page table in & out. Or use
a gart object and copy things in & out using dma.
v2: agd5f fixes:
- Add vram base offset for vram pages. The GPU physical address of a
vram page is FB_OFFSET + page offset. FB_OFFSET is 0 on discrete
cards and the physical bus address of the stolen memory on
integrated chips.
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR covers all vmid's >= 1
v3: agd5f:
- integrate with the semaphore/multi-ring stuff
v4:
- rebase on top ttm dma & multi-ring stuff
- userspace is now in charge of the address space
- no more specific cs vm ioctl, instead cs ioctl has a new
chunk
v5:
- properly handle mem == NULL case from move_notify callback
- fix the vm cleanup path
v6:
- fix update of page table to only happen on valid mem placement
v7:
- add tlb flush for each vm context
- add flags to define mapping property (readable, writeable, snooped)
- make ring id implicit from ib->fence->ring, up to each asic callback
to then do ring specific scheduling if vm ib scheduling function
v8:
- add query for ib limit and kernel reserved virtual space
- rename vm->size to max_pfn (maximum number of page)
- update gem_va ioctl to also allow unmap operation
- bump kernel version to allow userspace to query for vm support
v9:
- rebuild page table only when bind and incrementaly depending
on bo referenced by cs and that have been moved
- allow virtual address space to grow
- use sa allocator for vram page table
- return invalid when querying vm limit on non cayman GPU
- dump vm fault register on lockup
v10: agd5f:
- Move the vm schedule_ib callback to a standalone function, remove
the callback and use the existing ib_execute callback for VM IBs.
v11:
- rebase on top of lastest Linus
v12: agd5f:
- remove spurious backslash
- set IB vm_id to 0 in radeon_ib_get()
v13: agd5f:
- fix handling of RADEON_CHUNK_ID_FLAGS
v14:
- fix va destruction
- fix suspend resume
- forbid bo to have several different va in same vm
v15:
- rebase
v16:
- cleanup left over of vm init/fini
v17: agd5f:
- cs checker
v18: agd5f:
- reworks the CS ioctl to better support multiple rings and
VM. Rather than adding a new chunk id for VM, just re-use the
IB chunk id and add a new flags for VM mode. Also define additional
dwords for the flags chunk id to define the what ring we want to use
(gfx, compute, uvd, etc.) and the priority.
v19:
- fix cs fini in weird case of no ib
- semi working flush fix for ni
- rebase on top of sa allocator changes
v20: agd5f:
- further CS ioctl cleanups from Christian's comments
v21: agd5f:
- integrate CS checker improvements
v22: agd5f:
- final cleanups for release, only allow VM CS on cayman
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-01-05 20:11:05 -07:00
|
|
|
|
|
|
|
kfree(fpriv);
|
|
|
|
file_priv->driver_priv = NULL;
|
|
|
|
}
|
2016-08-31 15:23:31 -06:00
|
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
|
|
pm_runtime_put_autosuspend(dev->dev);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* VBlank related functions.
|
|
|
|
*/
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_get_vblank_counter_kms - get frame count
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
2015-12-16 07:31:47 -07:00
|
|
|
* @pipe: crtc to get the frame count from
|
2012-07-17 12:02:34 -06:00
|
|
|
*
|
|
|
|
* Gets the frame count on the requested crtc (all asics).
|
|
|
|
* Returns frame count on success, -EINVAL on failure.
|
|
|
|
*/
|
2015-12-16 07:31:47 -07:00
|
|
|
u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many
vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core
more fragile to drivers which don't update hw vblank counters and
vblank timestamps in sync with firing of the vblank irq and
essentially at leading edge of vblank.
This exposed a problem with radeon-kms/amdgpu-kms which do not
satisfy above requirements:
The vblank irq fires a few scanlines before start of vblank, but
programmed pageflips complete at start of vblank and
vblank timestamps update at start of vblank, whereas the
hw vblank counter increments only later, at start of vsync.
This leads to problems like off by one errors for vblank counter
updates, vblank counters apparently going backwards or vblank
timestamps apparently having time going backwards. The net result
is stuttering of graphics in games, or little hangs, as well as
total failure of timing sensitive applications.
See bug #93147 for an example of the regression on Linux 4.4-rc:
https://bugs.freedesktop.org/show_bug.cgi?id=93147
This patch tries to align all above events better from the
viewpoint of the drm core / of external callers to fix the problem:
1. The apparent start of vblank is shifted a few scanlines earlier,
so the vblank irq now always happens after start of this extended
vblank interval and thereby drm_update_vblank_count() always samples
the updated vblank count and timestamp of the new vblank interval.
To achieve this, the reporting of scanout positions by
radeon_get_crtc_scanoutpos() now operates as if the vblank starts
radeon_crtc->lb_vblank_lead_lines before the real start of the hw
vblank interval. This means that the vblank timestamps which are based
on these scanout positions will now update at this earlier start of
vblank.
2. The driver->get_vblank_counter() function will bump the returned
vblank count as read from the hw by +1 if the query happens after
the shifted earlier start of the vblank, but before the real hw increment
at start of vsync, so the counter appears to increment at start of vblank
in sync with the timestamp update.
3. Calls from vblank irq-context and regular non-irq calls are now
treated identical, always simulating the shifted vblank start, to
avoid inconsistent results for queries happening from vblank irq vs.
happening from drm_vblank_enable() or vblank_disable_fn().
4. The radeon_flip_work_func will delay mmio programming a pageflip until
the start of the real vblank iff it happens to execute inside the shifted
earlier start of the vblank, so pageflips now also appear to execute at
start of the shifted vblank, in sync with vblank counter and timestamp
updates. This to avoid some races between updates of vblank count and
timestamps that are used for swap scheduling and pageflip execution which
could cause pageflips to execute before the scheduled target vblank.
The lb_vblank_lead_lines "fudge" value is calculated as the size of
the display controllers line buffer in scanlines for the given video
mode: Vblank irq's are triggered by the line buffer logic when the line
buffer refill for a video frame ends, ie. when the line buffer source read
position enters the hw vblank. This means that a vblank irq could fire at
most as many scanlines before the current reported scanout position of the
crtc timing generator as the number of scanlines the line buffer can
maximally hold for a given video mode.
This patch has been successfully tested on a RV730 card with DCE-3 display
engine and on a evergreen card with DCE-4 display engine, in single-display
and dual-display configuration, with different video modes.
A similar patch is needed for amdgpu-kms to fix the same problem.
Limitations:
- Line buffer sizes in pixels are hard-coded on < DCE-4 to a value
i just guessed to be high enough to work ok, lacking info on the true
sizes atm.
Fixes: fdo#93147
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
(v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net>
(v2) Refine radeon_flip_work_func() for better efficiency:
In radeon_flip_work_func, replace the busy waiting udelay(5)
with event lock held by a more performance and energy efficient
usleep_range() until at least predicted true start of hw vblank,
with some slack for scheduler happiness. Release the event lock
during waits to not delay other outputs in doing their stuff, as
the waiting can last up to 200 usecs in some cases.
Retested on DCE-3 and DCE-4 to verify it still works nicely.
(v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-25 12:14:31 -07:00
|
|
|
int vpos, hpos, stat;
|
|
|
|
u32 count;
|
2009-08-13 03:10:51 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
|
2016-01-04 10:19:12 -07:00
|
|
|
if (pipe >= rdev->num_crtc) {
|
2015-12-16 07:31:47 -07:00
|
|
|
DRM_ERROR("Invalid crtc %u\n", pipe);
|
2009-08-13 03:10:51 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many
vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core
more fragile to drivers which don't update hw vblank counters and
vblank timestamps in sync with firing of the vblank irq and
essentially at leading edge of vblank.
This exposed a problem with radeon-kms/amdgpu-kms which do not
satisfy above requirements:
The vblank irq fires a few scanlines before start of vblank, but
programmed pageflips complete at start of vblank and
vblank timestamps update at start of vblank, whereas the
hw vblank counter increments only later, at start of vsync.
This leads to problems like off by one errors for vblank counter
updates, vblank counters apparently going backwards or vblank
timestamps apparently having time going backwards. The net result
is stuttering of graphics in games, or little hangs, as well as
total failure of timing sensitive applications.
See bug #93147 for an example of the regression on Linux 4.4-rc:
https://bugs.freedesktop.org/show_bug.cgi?id=93147
This patch tries to align all above events better from the
viewpoint of the drm core / of external callers to fix the problem:
1. The apparent start of vblank is shifted a few scanlines earlier,
so the vblank irq now always happens after start of this extended
vblank interval and thereby drm_update_vblank_count() always samples
the updated vblank count and timestamp of the new vblank interval.
To achieve this, the reporting of scanout positions by
radeon_get_crtc_scanoutpos() now operates as if the vblank starts
radeon_crtc->lb_vblank_lead_lines before the real start of the hw
vblank interval. This means that the vblank timestamps which are based
on these scanout positions will now update at this earlier start of
vblank.
2. The driver->get_vblank_counter() function will bump the returned
vblank count as read from the hw by +1 if the query happens after
the shifted earlier start of the vblank, but before the real hw increment
at start of vsync, so the counter appears to increment at start of vblank
in sync with the timestamp update.
3. Calls from vblank irq-context and regular non-irq calls are now
treated identical, always simulating the shifted vblank start, to
avoid inconsistent results for queries happening from vblank irq vs.
happening from drm_vblank_enable() or vblank_disable_fn().
4. The radeon_flip_work_func will delay mmio programming a pageflip until
the start of the real vblank iff it happens to execute inside the shifted
earlier start of the vblank, so pageflips now also appear to execute at
start of the shifted vblank, in sync with vblank counter and timestamp
updates. This to avoid some races between updates of vblank count and
timestamps that are used for swap scheduling and pageflip execution which
could cause pageflips to execute before the scheduled target vblank.
The lb_vblank_lead_lines "fudge" value is calculated as the size of
the display controllers line buffer in scanlines for the given video
mode: Vblank irq's are triggered by the line buffer logic when the line
buffer refill for a video frame ends, ie. when the line buffer source read
position enters the hw vblank. This means that a vblank irq could fire at
most as many scanlines before the current reported scanout position of the
crtc timing generator as the number of scanlines the line buffer can
maximally hold for a given video mode.
This patch has been successfully tested on a RV730 card with DCE-3 display
engine and on a evergreen card with DCE-4 display engine, in single-display
and dual-display configuration, with different video modes.
A similar patch is needed for amdgpu-kms to fix the same problem.
Limitations:
- Line buffer sizes in pixels are hard-coded on < DCE-4 to a value
i just guessed to be high enough to work ok, lacking info on the true
sizes atm.
Fixes: fdo#93147
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
(v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net>
(v2) Refine radeon_flip_work_func() for better efficiency:
In radeon_flip_work_func, replace the busy waiting udelay(5)
with event lock held by a more performance and energy efficient
usleep_range() until at least predicted true start of hw vblank,
with some slack for scheduler happiness. Release the event lock
during waits to not delay other outputs in doing their stuff, as
the waiting can last up to 200 usecs in some cases.
Retested on DCE-3 and DCE-4 to verify it still works nicely.
(v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-25 12:14:31 -07:00
|
|
|
/* The hw increments its frame counter at start of vsync, not at start
|
|
|
|
* of vblank, as is required by DRM core vblank counter handling.
|
|
|
|
* Cook the hw count here to make it appear to the caller as if it
|
|
|
|
* incremented at start of vblank. We measure distance to start of
|
|
|
|
* vblank in vpos. vpos therefore will be >= 0 between start of vblank
|
|
|
|
* and start of vsync, so vpos >= 0 means to bump the hw frame counter
|
|
|
|
* result by 1 to give the proper appearance to caller.
|
|
|
|
*/
|
2015-12-16 07:31:47 -07:00
|
|
|
if (rdev->mode_info.crtcs[pipe]) {
|
drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many
vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core
more fragile to drivers which don't update hw vblank counters and
vblank timestamps in sync with firing of the vblank irq and
essentially at leading edge of vblank.
This exposed a problem with radeon-kms/amdgpu-kms which do not
satisfy above requirements:
The vblank irq fires a few scanlines before start of vblank, but
programmed pageflips complete at start of vblank and
vblank timestamps update at start of vblank, whereas the
hw vblank counter increments only later, at start of vsync.
This leads to problems like off by one errors for vblank counter
updates, vblank counters apparently going backwards or vblank
timestamps apparently having time going backwards. The net result
is stuttering of graphics in games, or little hangs, as well as
total failure of timing sensitive applications.
See bug #93147 for an example of the regression on Linux 4.4-rc:
https://bugs.freedesktop.org/show_bug.cgi?id=93147
This patch tries to align all above events better from the
viewpoint of the drm core / of external callers to fix the problem:
1. The apparent start of vblank is shifted a few scanlines earlier,
so the vblank irq now always happens after start of this extended
vblank interval and thereby drm_update_vblank_count() always samples
the updated vblank count and timestamp of the new vblank interval.
To achieve this, the reporting of scanout positions by
radeon_get_crtc_scanoutpos() now operates as if the vblank starts
radeon_crtc->lb_vblank_lead_lines before the real start of the hw
vblank interval. This means that the vblank timestamps which are based
on these scanout positions will now update at this earlier start of
vblank.
2. The driver->get_vblank_counter() function will bump the returned
vblank count as read from the hw by +1 if the query happens after
the shifted earlier start of the vblank, but before the real hw increment
at start of vsync, so the counter appears to increment at start of vblank
in sync with the timestamp update.
3. Calls from vblank irq-context and regular non-irq calls are now
treated identical, always simulating the shifted vblank start, to
avoid inconsistent results for queries happening from vblank irq vs.
happening from drm_vblank_enable() or vblank_disable_fn().
4. The radeon_flip_work_func will delay mmio programming a pageflip until
the start of the real vblank iff it happens to execute inside the shifted
earlier start of the vblank, so pageflips now also appear to execute at
start of the shifted vblank, in sync with vblank counter and timestamp
updates. This to avoid some races between updates of vblank count and
timestamps that are used for swap scheduling and pageflip execution which
could cause pageflips to execute before the scheduled target vblank.
The lb_vblank_lead_lines "fudge" value is calculated as the size of
the display controllers line buffer in scanlines for the given video
mode: Vblank irq's are triggered by the line buffer logic when the line
buffer refill for a video frame ends, ie. when the line buffer source read
position enters the hw vblank. This means that a vblank irq could fire at
most as many scanlines before the current reported scanout position of the
crtc timing generator as the number of scanlines the line buffer can
maximally hold for a given video mode.
This patch has been successfully tested on a RV730 card with DCE-3 display
engine and on a evergreen card with DCE-4 display engine, in single-display
and dual-display configuration, with different video modes.
A similar patch is needed for amdgpu-kms to fix the same problem.
Limitations:
- Line buffer sizes in pixels are hard-coded on < DCE-4 to a value
i just guessed to be high enough to work ok, lacking info on the true
sizes atm.
Fixes: fdo#93147
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
(v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net>
(v2) Refine radeon_flip_work_func() for better efficiency:
In radeon_flip_work_func, replace the busy waiting udelay(5)
with event lock held by a more performance and energy efficient
usleep_range() until at least predicted true start of hw vblank,
with some slack for scheduler happiness. Release the event lock
during waits to not delay other outputs in doing their stuff, as
the waiting can last up to 200 usecs in some cases.
Retested on DCE-3 and DCE-4 to verify it still works nicely.
(v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-25 12:14:31 -07:00
|
|
|
/* Repeat readout if needed to provide stable result if
|
|
|
|
* we cross start of vsync during the queries.
|
|
|
|
*/
|
|
|
|
do {
|
2015-12-16 07:31:47 -07:00
|
|
|
count = radeon_get_vblank_counter(rdev, pipe);
|
drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many
vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core
more fragile to drivers which don't update hw vblank counters and
vblank timestamps in sync with firing of the vblank irq and
essentially at leading edge of vblank.
This exposed a problem with radeon-kms/amdgpu-kms which do not
satisfy above requirements:
The vblank irq fires a few scanlines before start of vblank, but
programmed pageflips complete at start of vblank and
vblank timestamps update at start of vblank, whereas the
hw vblank counter increments only later, at start of vsync.
This leads to problems like off by one errors for vblank counter
updates, vblank counters apparently going backwards or vblank
timestamps apparently having time going backwards. The net result
is stuttering of graphics in games, or little hangs, as well as
total failure of timing sensitive applications.
See bug #93147 for an example of the regression on Linux 4.4-rc:
https://bugs.freedesktop.org/show_bug.cgi?id=93147
This patch tries to align all above events better from the
viewpoint of the drm core / of external callers to fix the problem:
1. The apparent start of vblank is shifted a few scanlines earlier,
so the vblank irq now always happens after start of this extended
vblank interval and thereby drm_update_vblank_count() always samples
the updated vblank count and timestamp of the new vblank interval.
To achieve this, the reporting of scanout positions by
radeon_get_crtc_scanoutpos() now operates as if the vblank starts
radeon_crtc->lb_vblank_lead_lines before the real start of the hw
vblank interval. This means that the vblank timestamps which are based
on these scanout positions will now update at this earlier start of
vblank.
2. The driver->get_vblank_counter() function will bump the returned
vblank count as read from the hw by +1 if the query happens after
the shifted earlier start of the vblank, but before the real hw increment
at start of vsync, so the counter appears to increment at start of vblank
in sync with the timestamp update.
3. Calls from vblank irq-context and regular non-irq calls are now
treated identical, always simulating the shifted vblank start, to
avoid inconsistent results for queries happening from vblank irq vs.
happening from drm_vblank_enable() or vblank_disable_fn().
4. The radeon_flip_work_func will delay mmio programming a pageflip until
the start of the real vblank iff it happens to execute inside the shifted
earlier start of the vblank, so pageflips now also appear to execute at
start of the shifted vblank, in sync with vblank counter and timestamp
updates. This to avoid some races between updates of vblank count and
timestamps that are used for swap scheduling and pageflip execution which
could cause pageflips to execute before the scheduled target vblank.
The lb_vblank_lead_lines "fudge" value is calculated as the size of
the display controllers line buffer in scanlines for the given video
mode: Vblank irq's are triggered by the line buffer logic when the line
buffer refill for a video frame ends, ie. when the line buffer source read
position enters the hw vblank. This means that a vblank irq could fire at
most as many scanlines before the current reported scanout position of the
crtc timing generator as the number of scanlines the line buffer can
maximally hold for a given video mode.
This patch has been successfully tested on a RV730 card with DCE-3 display
engine and on a evergreen card with DCE-4 display engine, in single-display
and dual-display configuration, with different video modes.
A similar patch is needed for amdgpu-kms to fix the same problem.
Limitations:
- Line buffer sizes in pixels are hard-coded on < DCE-4 to a value
i just guessed to be high enough to work ok, lacking info on the true
sizes atm.
Fixes: fdo#93147
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
(v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net>
(v2) Refine radeon_flip_work_func() for better efficiency:
In radeon_flip_work_func, replace the busy waiting udelay(5)
with event lock held by a more performance and energy efficient
usleep_range() until at least predicted true start of hw vblank,
with some slack for scheduler happiness. Release the event lock
during waits to not delay other outputs in doing their stuff, as
the waiting can last up to 200 usecs in some cases.
Retested on DCE-3 and DCE-4 to verify it still works nicely.
(v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-25 12:14:31 -07:00
|
|
|
/* Ask radeon_get_crtc_scanoutpos to return vpos as
|
|
|
|
* distance to start of vblank, instead of regular
|
|
|
|
* vertical scanout pos.
|
|
|
|
*/
|
|
|
|
stat = radeon_get_crtc_scanoutpos(
|
2015-12-16 07:31:47 -07:00
|
|
|
dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
|
drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many
vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core
more fragile to drivers which don't update hw vblank counters and
vblank timestamps in sync with firing of the vblank irq and
essentially at leading edge of vblank.
This exposed a problem with radeon-kms/amdgpu-kms which do not
satisfy above requirements:
The vblank irq fires a few scanlines before start of vblank, but
programmed pageflips complete at start of vblank and
vblank timestamps update at start of vblank, whereas the
hw vblank counter increments only later, at start of vsync.
This leads to problems like off by one errors for vblank counter
updates, vblank counters apparently going backwards or vblank
timestamps apparently having time going backwards. The net result
is stuttering of graphics in games, or little hangs, as well as
total failure of timing sensitive applications.
See bug #93147 for an example of the regression on Linux 4.4-rc:
https://bugs.freedesktop.org/show_bug.cgi?id=93147
This patch tries to align all above events better from the
viewpoint of the drm core / of external callers to fix the problem:
1. The apparent start of vblank is shifted a few scanlines earlier,
so the vblank irq now always happens after start of this extended
vblank interval and thereby drm_update_vblank_count() always samples
the updated vblank count and timestamp of the new vblank interval.
To achieve this, the reporting of scanout positions by
radeon_get_crtc_scanoutpos() now operates as if the vblank starts
radeon_crtc->lb_vblank_lead_lines before the real start of the hw
vblank interval. This means that the vblank timestamps which are based
on these scanout positions will now update at this earlier start of
vblank.
2. The driver->get_vblank_counter() function will bump the returned
vblank count as read from the hw by +1 if the query happens after
the shifted earlier start of the vblank, but before the real hw increment
at start of vsync, so the counter appears to increment at start of vblank
in sync with the timestamp update.
3. Calls from vblank irq-context and regular non-irq calls are now
treated identical, always simulating the shifted vblank start, to
avoid inconsistent results for queries happening from vblank irq vs.
happening from drm_vblank_enable() or vblank_disable_fn().
4. The radeon_flip_work_func will delay mmio programming a pageflip until
the start of the real vblank iff it happens to execute inside the shifted
earlier start of the vblank, so pageflips now also appear to execute at
start of the shifted vblank, in sync with vblank counter and timestamp
updates. This to avoid some races between updates of vblank count and
timestamps that are used for swap scheduling and pageflip execution which
could cause pageflips to execute before the scheduled target vblank.
The lb_vblank_lead_lines "fudge" value is calculated as the size of
the display controllers line buffer in scanlines for the given video
mode: Vblank irq's are triggered by the line buffer logic when the line
buffer refill for a video frame ends, ie. when the line buffer source read
position enters the hw vblank. This means that a vblank irq could fire at
most as many scanlines before the current reported scanout position of the
crtc timing generator as the number of scanlines the line buffer can
maximally hold for a given video mode.
This patch has been successfully tested on a RV730 card with DCE-3 display
engine and on a evergreen card with DCE-4 display engine, in single-display
and dual-display configuration, with different video modes.
A similar patch is needed for amdgpu-kms to fix the same problem.
Limitations:
- Line buffer sizes in pixels are hard-coded on < DCE-4 to a value
i just guessed to be high enough to work ok, lacking info on the true
sizes atm.
Fixes: fdo#93147
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
(v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net>
(v2) Refine radeon_flip_work_func() for better efficiency:
In radeon_flip_work_func, replace the busy waiting udelay(5)
with event lock held by a more performance and energy efficient
usleep_range() until at least predicted true start of hw vblank,
with some slack for scheduler happiness. Release the event lock
during waits to not delay other outputs in doing their stuff, as
the waiting can last up to 200 usecs in some cases.
Retested on DCE-3 and DCE-4 to verify it still works nicely.
(v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-25 12:14:31 -07:00
|
|
|
&vpos, &hpos, NULL, NULL,
|
2015-12-16 07:31:47 -07:00
|
|
|
&rdev->mode_info.crtcs[pipe]->base.hwmode);
|
|
|
|
} while (count != radeon_get_vblank_counter(rdev, pipe));
|
drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many
vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core
more fragile to drivers which don't update hw vblank counters and
vblank timestamps in sync with firing of the vblank irq and
essentially at leading edge of vblank.
This exposed a problem with radeon-kms/amdgpu-kms which do not
satisfy above requirements:
The vblank irq fires a few scanlines before start of vblank, but
programmed pageflips complete at start of vblank and
vblank timestamps update at start of vblank, whereas the
hw vblank counter increments only later, at start of vsync.
This leads to problems like off by one errors for vblank counter
updates, vblank counters apparently going backwards or vblank
timestamps apparently having time going backwards. The net result
is stuttering of graphics in games, or little hangs, as well as
total failure of timing sensitive applications.
See bug #93147 for an example of the regression on Linux 4.4-rc:
https://bugs.freedesktop.org/show_bug.cgi?id=93147
This patch tries to align all above events better from the
viewpoint of the drm core / of external callers to fix the problem:
1. The apparent start of vblank is shifted a few scanlines earlier,
so the vblank irq now always happens after start of this extended
vblank interval and thereby drm_update_vblank_count() always samples
the updated vblank count and timestamp of the new vblank interval.
To achieve this, the reporting of scanout positions by
radeon_get_crtc_scanoutpos() now operates as if the vblank starts
radeon_crtc->lb_vblank_lead_lines before the real start of the hw
vblank interval. This means that the vblank timestamps which are based
on these scanout positions will now update at this earlier start of
vblank.
2. The driver->get_vblank_counter() function will bump the returned
vblank count as read from the hw by +1 if the query happens after
the shifted earlier start of the vblank, but before the real hw increment
at start of vsync, so the counter appears to increment at start of vblank
in sync with the timestamp update.
3. Calls from vblank irq-context and regular non-irq calls are now
treated identical, always simulating the shifted vblank start, to
avoid inconsistent results for queries happening from vblank irq vs.
happening from drm_vblank_enable() or vblank_disable_fn().
4. The radeon_flip_work_func will delay mmio programming a pageflip until
the start of the real vblank iff it happens to execute inside the shifted
earlier start of the vblank, so pageflips now also appear to execute at
start of the shifted vblank, in sync with vblank counter and timestamp
updates. This to avoid some races between updates of vblank count and
timestamps that are used for swap scheduling and pageflip execution which
could cause pageflips to execute before the scheduled target vblank.
The lb_vblank_lead_lines "fudge" value is calculated as the size of
the display controllers line buffer in scanlines for the given video
mode: Vblank irq's are triggered by the line buffer logic when the line
buffer refill for a video frame ends, ie. when the line buffer source read
position enters the hw vblank. This means that a vblank irq could fire at
most as many scanlines before the current reported scanout position of the
crtc timing generator as the number of scanlines the line buffer can
maximally hold for a given video mode.
This patch has been successfully tested on a RV730 card with DCE-3 display
engine and on a evergreen card with DCE-4 display engine, in single-display
and dual-display configuration, with different video modes.
A similar patch is needed for amdgpu-kms to fix the same problem.
Limitations:
- Line buffer sizes in pixels are hard-coded on < DCE-4 to a value
i just guessed to be high enough to work ok, lacking info on the true
sizes atm.
Fixes: fdo#93147
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
(v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net>
(v2) Refine radeon_flip_work_func() for better efficiency:
In radeon_flip_work_func, replace the busy waiting udelay(5)
with event lock held by a more performance and energy efficient
usleep_range() until at least predicted true start of hw vblank,
with some slack for scheduler happiness. Release the event lock
during waits to not delay other outputs in doing their stuff, as
the waiting can last up to 200 usecs in some cases.
Retested on DCE-3 and DCE-4 to verify it still works nicely.
(v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-25 12:14:31 -07:00
|
|
|
|
|
|
|
if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
|
|
|
|
(DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
|
|
|
|
DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
|
|
|
|
}
|
|
|
|
else {
|
2015-12-16 07:31:47 -07:00
|
|
|
DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
|
|
|
|
pipe, vpos);
|
drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many
vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core
more fragile to drivers which don't update hw vblank counters and
vblank timestamps in sync with firing of the vblank irq and
essentially at leading edge of vblank.
This exposed a problem with radeon-kms/amdgpu-kms which do not
satisfy above requirements:
The vblank irq fires a few scanlines before start of vblank, but
programmed pageflips complete at start of vblank and
vblank timestamps update at start of vblank, whereas the
hw vblank counter increments only later, at start of vsync.
This leads to problems like off by one errors for vblank counter
updates, vblank counters apparently going backwards or vblank
timestamps apparently having time going backwards. The net result
is stuttering of graphics in games, or little hangs, as well as
total failure of timing sensitive applications.
See bug #93147 for an example of the regression on Linux 4.4-rc:
https://bugs.freedesktop.org/show_bug.cgi?id=93147
This patch tries to align all above events better from the
viewpoint of the drm core / of external callers to fix the problem:
1. The apparent start of vblank is shifted a few scanlines earlier,
so the vblank irq now always happens after start of this extended
vblank interval and thereby drm_update_vblank_count() always samples
the updated vblank count and timestamp of the new vblank interval.
To achieve this, the reporting of scanout positions by
radeon_get_crtc_scanoutpos() now operates as if the vblank starts
radeon_crtc->lb_vblank_lead_lines before the real start of the hw
vblank interval. This means that the vblank timestamps which are based
on these scanout positions will now update at this earlier start of
vblank.
2. The driver->get_vblank_counter() function will bump the returned
vblank count as read from the hw by +1 if the query happens after
the shifted earlier start of the vblank, but before the real hw increment
at start of vsync, so the counter appears to increment at start of vblank
in sync with the timestamp update.
3. Calls from vblank irq-context and regular non-irq calls are now
treated identical, always simulating the shifted vblank start, to
avoid inconsistent results for queries happening from vblank irq vs.
happening from drm_vblank_enable() or vblank_disable_fn().
4. The radeon_flip_work_func will delay mmio programming a pageflip until
the start of the real vblank iff it happens to execute inside the shifted
earlier start of the vblank, so pageflips now also appear to execute at
start of the shifted vblank, in sync with vblank counter and timestamp
updates. This to avoid some races between updates of vblank count and
timestamps that are used for swap scheduling and pageflip execution which
could cause pageflips to execute before the scheduled target vblank.
The lb_vblank_lead_lines "fudge" value is calculated as the size of
the display controllers line buffer in scanlines for the given video
mode: Vblank irq's are triggered by the line buffer logic when the line
buffer refill for a video frame ends, ie. when the line buffer source read
position enters the hw vblank. This means that a vblank irq could fire at
most as many scanlines before the current reported scanout position of the
crtc timing generator as the number of scanlines the line buffer can
maximally hold for a given video mode.
This patch has been successfully tested on a RV730 card with DCE-3 display
engine and on a evergreen card with DCE-4 display engine, in single-display
and dual-display configuration, with different video modes.
A similar patch is needed for amdgpu-kms to fix the same problem.
Limitations:
- Line buffer sizes in pixels are hard-coded on < DCE-4 to a value
i just guessed to be high enough to work ok, lacking info on the true
sizes atm.
Fixes: fdo#93147
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
(v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net>
(v2) Refine radeon_flip_work_func() for better efficiency:
In radeon_flip_work_func, replace the busy waiting udelay(5)
with event lock held by a more performance and energy efficient
usleep_range() until at least predicted true start of hw vblank,
with some slack for scheduler happiness. Release the event lock
during waits to not delay other outputs in doing their stuff, as
the waiting can last up to 200 usecs in some cases.
Retested on DCE-3 and DCE-4 to verify it still works nicely.
(v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-25 12:14:31 -07:00
|
|
|
|
|
|
|
/* Bump counter if we are at >= leading edge of vblank,
|
|
|
|
* but before vsync where vpos would turn negative and
|
|
|
|
* the hw counter really increments.
|
|
|
|
*/
|
|
|
|
if (vpos >= 0)
|
|
|
|
count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/* Fallback to use value as is. */
|
2015-12-16 07:31:47 -07:00
|
|
|
count = radeon_get_vblank_counter(rdev, pipe);
|
drm/radeon: Fixup hw vblank counter/ts for new drm_update_vblank_count() (v2)
commit 4dfd6486 "drm: Use vblank timestamps to guesstimate how many
vblanks were missed" introduced in Linux 4.4-rc1 makes the drm core
more fragile to drivers which don't update hw vblank counters and
vblank timestamps in sync with firing of the vblank irq and
essentially at leading edge of vblank.
This exposed a problem with radeon-kms/amdgpu-kms which do not
satisfy above requirements:
The vblank irq fires a few scanlines before start of vblank, but
programmed pageflips complete at start of vblank and
vblank timestamps update at start of vblank, whereas the
hw vblank counter increments only later, at start of vsync.
This leads to problems like off by one errors for vblank counter
updates, vblank counters apparently going backwards or vblank
timestamps apparently having time going backwards. The net result
is stuttering of graphics in games, or little hangs, as well as
total failure of timing sensitive applications.
See bug #93147 for an example of the regression on Linux 4.4-rc:
https://bugs.freedesktop.org/show_bug.cgi?id=93147
This patch tries to align all above events better from the
viewpoint of the drm core / of external callers to fix the problem:
1. The apparent start of vblank is shifted a few scanlines earlier,
so the vblank irq now always happens after start of this extended
vblank interval and thereby drm_update_vblank_count() always samples
the updated vblank count and timestamp of the new vblank interval.
To achieve this, the reporting of scanout positions by
radeon_get_crtc_scanoutpos() now operates as if the vblank starts
radeon_crtc->lb_vblank_lead_lines before the real start of the hw
vblank interval. This means that the vblank timestamps which are based
on these scanout positions will now update at this earlier start of
vblank.
2. The driver->get_vblank_counter() function will bump the returned
vblank count as read from the hw by +1 if the query happens after
the shifted earlier start of the vblank, but before the real hw increment
at start of vsync, so the counter appears to increment at start of vblank
in sync with the timestamp update.
3. Calls from vblank irq-context and regular non-irq calls are now
treated identical, always simulating the shifted vblank start, to
avoid inconsistent results for queries happening from vblank irq vs.
happening from drm_vblank_enable() or vblank_disable_fn().
4. The radeon_flip_work_func will delay mmio programming a pageflip until
the start of the real vblank iff it happens to execute inside the shifted
earlier start of the vblank, so pageflips now also appear to execute at
start of the shifted vblank, in sync with vblank counter and timestamp
updates. This to avoid some races between updates of vblank count and
timestamps that are used for swap scheduling and pageflip execution which
could cause pageflips to execute before the scheduled target vblank.
The lb_vblank_lead_lines "fudge" value is calculated as the size of
the display controllers line buffer in scanlines for the given video
mode: Vblank irq's are triggered by the line buffer logic when the line
buffer refill for a video frame ends, ie. when the line buffer source read
position enters the hw vblank. This means that a vblank irq could fire at
most as many scanlines before the current reported scanout position of the
crtc timing generator as the number of scanlines the line buffer can
maximally hold for a given video mode.
This patch has been successfully tested on a RV730 card with DCE-3 display
engine and on a evergreen card with DCE-4 display engine, in single-display
and dual-display configuration, with different video modes.
A similar patch is needed for amdgpu-kms to fix the same problem.
Limitations:
- Line buffer sizes in pixels are hard-coded on < DCE-4 to a value
i just guessed to be high enough to work ok, lacking info on the true
sizes atm.
Fixes: fdo#93147
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Cc: Harry Wentland <Harry.Wentland@amd.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
(v1) Tested-by: Dave Witbrodt <dawitbro@sbcglobal.net>
(v2) Refine radeon_flip_work_func() for better efficiency:
In radeon_flip_work_func, replace the busy waiting udelay(5)
with event lock held by a more performance and energy efficient
usleep_range() until at least predicted true start of hw vblank,
with some slack for scheduler happiness. Release the event lock
during waits to not delay other outputs in doing their stuff, as
the waiting can last up to 200 usecs in some cases.
Retested on DCE-3 and DCE-4 to verify it still works nicely.
(v2) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2015-11-25 12:14:31 -07:00
|
|
|
DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
return count;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_enable_vblank_kms - enable vblank interrupt
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @crtc: crtc to enable vblank interrupt for
|
|
|
|
*
|
|
|
|
* Enable the interrupt on the requested crtc (all asics).
|
|
|
|
* Returns 0 on success, -EINVAL on failure.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
|
|
|
|
{
|
2009-08-13 03:10:51 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2012-05-16 17:33:30 -06:00
|
|
|
unsigned long irqflags;
|
|
|
|
int r;
|
2009-08-13 03:10:51 -06:00
|
|
|
|
2010-04-22 21:21:58 -06:00
|
|
|
if (crtc < 0 || crtc >= rdev->num_crtc) {
|
2009-08-13 03:10:51 -06:00
|
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2012-05-16 17:33:30 -06:00
|
|
|
spin_lock_irqsave(&rdev->irq.lock, irqflags);
|
2009-08-13 03:10:51 -06:00
|
|
|
rdev->irq.crtc_vblank_int[crtc] = true;
|
2012-05-16 17:33:30 -06:00
|
|
|
r = radeon_irq_set(rdev);
|
|
|
|
spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
|
|
|
|
return r;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:34 -06:00
|
|
|
/**
|
|
|
|
* radeon_disable_vblank_kms - disable vblank interrupt
|
|
|
|
*
|
|
|
|
* @dev: drm dev pointer
|
|
|
|
* @crtc: crtc to disable vblank interrupt for
|
|
|
|
*
|
|
|
|
* Disable the interrupt on the requested crtc (all asics).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
|
|
|
|
{
|
2009-08-13 03:10:51 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2012-05-16 17:33:30 -06:00
|
|
|
unsigned long irqflags;
|
2009-08-13 03:10:51 -06:00
|
|
|
|
2010-04-22 21:21:58 -06:00
|
|
|
if (crtc < 0 || crtc >= rdev->num_crtc) {
|
2009-08-13 03:10:51 -06:00
|
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-05-16 17:33:30 -06:00
|
|
|
spin_lock_irqsave(&rdev->irq.lock, irqflags);
|
2009-08-13 03:10:51 -06:00
|
|
|
rdev->irq.crtc_vblank_int[crtc] = false;
|
|
|
|
radeon_irq_set(rdev);
|
2012-05-16 17:33:30 -06:00
|
|
|
spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2013-08-02 11:27:49 -06:00
|
|
|
const struct drm_ioctl_desc radeon_ioctls_kms[] = {
|
2015-09-08 05:56:26 -06:00
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
|
2009-06-05 06:42:42 -06:00
|
|
|
/* KMS */
|
2015-09-08 05:56:30 -06:00
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
|
2009-06-05 06:42:42 -06:00
|
|
|
};
|
2014-06-09 07:39:49 -06:00
|
|
|
int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);
|